POLITECNICO DI MILANO
Facoltà di Ingegneria
Dipartimento di Elettronica e Informazione
ON THE DEVELOPMENT OF
FULLY-INTEGRATED LC-TUNED VCOS
FOR WIRELESS APPLICATIONS
Advisor:
Prof. Andrea L. LACAITA
Co-advisor: Dr. Carlo SAMORI
Ph.D. Dissertation of
Alfio ZANCHI
N. D00443
Ph.D. Course in Electronics and Communications Engineering – XII, 1997-1999
POLITECNICO DI MILANO
- December 1999 -
ON THE DEVELOPMENT OF
FULLY-INTEGRATED LC-TUNED VCOS
FOR WIRELESS APPLICATIONS
by
Alfio ZANCHI
A dissertation presented in partial fulfillment
of the requirements for the Ph.D. Degree
XII Course in Electronics and Communications Engineering
1997-1999
the Advisor,
the Supervisory Committee
Chairperson,
the Author,
Prof. A.L. Lacaita
Prof. G. Ripamonti
Ing. Alfio Zanchi
To my mother, and all of her sacrifices
To my father, and the mountains he is walking on now
If you wish to gain an idea of what
revolution is, call it Progress; and
if you wish to acquire an idea of the
nature of progress, call it To-morrow.
(Victor-Marie Hugo, Les Misérables,
Pt. II, Bk. 1, Ch. XVII - 1862)
Index of contents
Index of contents
I
II
III
IV
Index of Contents
…I
Introduction
…1
Framework and motivations of the work
Main results of the research activity
The map of this document
About the style of exposition
Chapter 1
A non-linear phase noise theory
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
The starting point
Working principle of the LC-tank oscillator
Linear analysis of the oscillator noise
Harmonic transfer in non-linear systems
Noise due to the base spreading resistors
Noise due to the tail generator
Wrap-up of the analysis’ results
The role of AM-to-PM conversion
Chapter 2
Measurements vs. predictions and Q-loading
2.1
2.2
2.3
2.3.1
2.3.2
2.4
2.4.1
2.4.2
2.4.3
Chronology of the test VCO sequence
A glimpse at the HSB2 technology
Phase noise analysis of the VCO TIBIA
Structure of the oscillator
SSCR prediction
Phase noise analysis of the VCO STARMAN-CUT 1
SSCR prediction
Deeper phase noise analysis - AAC turned off
The SSCR experimental data
…1
…3
…4
…5
…6
…6
…7
…8
… 11
… 14
… 18
… 21
… 21
… 23
… 23
… 24
… 24
24
26
… 28
28
31
33
I
Index of contents
2.5
2.6
2.7
2.8
2.8.1
2.8.2
2.8.3
2.8.4
2.9
2.10
2.11
Accordance of the phase noise theory with SpectreRF
Phase noise analysis of the VCO STARMAN-CUT 1.1
Discrepancy with measurements and need for an extended theory
Decomposition of the overall Q of the VCO
Q set by the transconductor
Q set by the varactors
Q set by the inductor
Q set by external loads
Amplitude-dependent Q-loading due to the transconductor
Q-loading evaluation by harmonic decomposition
Q extraction from ITAIL → A0 measurements
Chapter 3
Investigation on AM-to-PM conversion effects
3.1
3.1.1
3.1.2
3.1.2.1
3.1.2.2
3.2
3.3
3.4
3.5
3.6
3.7
3.7.1
3.7.2
3.7.3
3.8
3.8.1
3.8.2
3.8.3
3.9
3.10
Contributors to the tail current noise
AAC noise injection
BGR noise injection
Output driving capability of the BGR
Output voltage noise of the reference
Behavioral static estimation of AM-to-PM conversion
Corrections due to PLL feedback
Estimation by electrical tank simulation
Varactor dynamics implication on AM-to-PM conversion
Planar structure of the junction
“Reverse engineering” of the planar varactor
Materials and geometry of the varactor
Static DC-AC tests
Doping profiles after reconstruction
Oscillation-driven carrier motion within the junction
Low frequency: f0 = 1 Hz
Intermediate frequency: f0 = 1 MHz
RF frequency: f0 = 2.64 GHz
The dynamic characteristic of the capacitance
AM-to-PM variation with frequency
Chapter 4
Importance of Indirect stability
4.1 Phase noise degradation at high oscillation amplitudes
4.2 What do previous theories say?
II
… 34
… 34
… 36
… 38
39
39
41
41
… 42
… 44
… 47
… 48
… 48
48
50
52
53
… 54
… 57
… 58
… 59
… 60
… 61
61
62
65
… 67
67
73
75
… 77
… 79
… 81
… 81
… 82
Index of contents
4.3 Additional phase noise generation mechanisms to be inspected
4.4 Ranking the stability: the Kζ coefficients
4.5 The KTAIL – Definition and direct measurement
4.6 Fast evaluation technique for KTAIL
4.7 The key effect: impact of tail current sensitivity on SSCR
4.8 BGR insertion countercheck
4.9 Other sensitivities: to amplitude, tuning, and supply noise
4.10 Fast simulation techniques for phase noise assessment
4.10.1 The traditional tone-insertion approach
4.10.2 Optimization for sensitivity method
4.10.3 Frequency demodulation method
4.11
4.12
4.13
4.14
Circuit interpretation of indirect instability
The role of the transconductor poles
Simulative validation of the instability concept
The last unknown
Chapter 5
Time-varying analysis of noise in the AAC servo-loop
5.1
5.2
5.3
5.4
5.4.1
5.4.2
5.4.3
5.5
5.5.1
5.5.2
5.6
5.6.1
5.6.2
5.7
5.8
5.9
5.10
5.10.1
5.10.2
5.10.3
5.11
Usefulness of the AAC loop
Potential jeopardy of the AAC on SSCR performance
Peak detector as chief noise contributor
Switched noise as time-varying stochastic process – The theory
The background: weighing functions and autocorrelation
Application of the concepts in the case of peak detector
Further refinements of the analysis
Behavioral simulations of noise in the peak detector
Switched-noise modeling technique
The numerical procedure
Crosscheck of the theory through simulations
Duty cycle modulation
Peak detector gm modulation
Correction for real averaging filters – An additional pole
A simple rule for noise density vs. duty cycle prediction
Setup of discrete-components test board
Switched noise measurements
Duty cycle sweep
Rectifier gm sweep
Input waveform frequency sweep
Design suggestions and SSCR correction inferred
… 83
… 85
… 86
… 89
… 90
… 93
… 94
… 96
96
98
100
… 102
… 103
… 103
… 107
… 109
… 109
… 111
… 112
… 113
114
117
119
… 120
120
121
… 124
124
127
… 128
… 129
… 131
… 136
137
138
138
… 139
III
Index of contents
Chapter 6
From concepts to circuit design
6.1
6.2
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.3
6.4
6.5
6.6
6.7
The key guideline
Improvements proposed on the STARMAN cell
Cell core optimization
Tail current optimization
Base biasing voltage optimization
Transistor sizing and its benefits on FRAME6
Decoupling issues – The output voltage follower
Inductor enhancement
Design of the new Widlar AAC
A pre-warped solution for linearized differential tuning
VCO with synthesized inductance - tuning capabilities
Mirrored-Colpitts oscillator and output buffer issues
Chapter 7
Layout of the new structures
7.1
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.2.8
7.2.9
7.2.10
7.2.11
7.2.12
7.2.13
IV
Package-driven test chips organization
Layout issues of the test VCOs
Layout A – Standalone STARMAN
Layout B – Standalone STARMAN with improved-Q inductor:
Metal1 plate
Layout L – Standalone STARMAN with improved-Q inductor:
Metal1 patterned shield
Layout N – Standalone STARMAN with improved-Q inductor:
Metal3-only spiral
Layout C – Standalone STARMAN with improved-Q inductor:
Single-turn Metal3 spiral
Layout M – Standalone STARMAN with improved-Q inductor:
Metal1 patterned shield and Metal3-only spiral
Layout D – Standalone STARMAN with
modified trenches surface shielding
Layout F – STARMAN with enhanced AAC servo-circuit
Layout G – STARMAN with enhanced AAC servo-circuit and
Noise-filtered current sources
Layout Q – STARMAN with enhanced AAC servo-circuit and
Metal1 patterned shield
Layout H – Mirrored Colpitts
Layout I – Mirrored Colpitts with improved-Q inductor:
Metal1 patterned ground shield
Layout P – Mirrored Colpitts with improved-Q inductor:
… 141
… 141
… 142
142
143
144
144
147
… 148
… 149
… 158
… 160
… 162
… 166
… 166
… 167
168
171
173
174
175
176
176
177
179
180
180
182
Index of contents
7.2.14
7.2.15
7.2.16
7.2.17
7.2.18
7.3
Metal3-only spiral
Layout O – Mirrored Colpitts with improved-Q inductor:
Single-turn Metal3 spiral
Layout E – Standalone STARMAN with central symmetry
Layout J – Synthesized inductance tunable oscillator
Layout K – Differential-tuning STARMAN
A tentative layout in MOS technology
Chip floorplanning and the I/O ring
Chapter 8
The test setup – design of RF boards
8.1
8.1.1
8.1.2
8.1.2.1
8.1.2.2
8.1.2.3
8.1.2.4
8.1.3
8.1.4
8.2
8.2.1
8.2.2
8.2.2.1
8.2.2.2
8.2.2.3
8.2.2.4
8.2.3
8.2.4
8.2.5
A.1
A.2
A.2.1
A.2.2
RF board for FRAME6
182
182
183
184
186
187
… 188
… 191
… 191
Preliminary design choices
The rationale behind the physical PCB design
192
193
Left chip side
Bottom chip side
Right chip side
Top chip side
194
194
195
196
Trace-matching issues
Physical design of the PCB
197
200
RF board for Run 07/99
Main features of the socket
General organization of the PCB
Fabrication constraints
PCB drilling issues
Stacked layer assignment
Floorplan of the board
The chip leads arrangement
Components for on-board wrap-around
The final product – Ready for the tests
… 203
203
206
206
209
209
210
212
214
215
Conclusions
… 217
Appendix A
Realization of the low-noise voltage amplifier
… 218
Necessity of a low-noise voltage amplifier
Circuit description – The two feedback loops
First feedback loop: the main working principle
Second feedback loop: for offset abatement
… 218
… 219
220
221
V
Index of contents
A.3
A.4
A.4.1
A.4.2
A.4.3
A.5
A.6
CMRR performance
The input-referred noise
Noise due to passive components
Noise due to active components
Noise minimization
PCB fabrication
Test of the amplifier performance
Appendix B
Temperature influence on sensitivity
B.1 Oscillation frequency characterization
in temperature-controlled environment
B.2 Thermal adjustments on KTAIL
Appendix C
Some math behind the time-varying Syy(0)
C.1
Calculations and approximations
for the spectral density noise level
Appendix D
Component list for the RF boards
D.1
D.2
Discrete components for the DAB-FRAME6 board
Discrete components for the RUN0799 board
224
225
226
… 227
… 229
… 233
… 233
… 235
… 240
… 240
… 242
… 242
… 243
Bibliography
… 244
Acknowledgments
… 253
Tables a-d
The 4 new circuits
Tables A-Q
The 17 VCO versions
VI
… 222
… 224
Index of contents
Tables I-VI
The 6 test chips
VII
Introduction
Introduction
I Framework and motivations of the work
T
he steadily growing interest for the wireless communications field has triggered a
host of research efforts, both in the industrial and in the academic world, aimed at
exploring the feasibility of miniaturized, power-efficient transceivers for mobile
terminals.
The essentials of a transceiver front-end are proposed in Fig. 1. The insets pinpoint the
capital importance of the local oscillator performance, which is recognized to be the bottleneck
of the whole receiver chain. The presence of unwanted signals, for instance isotropically radiated
broadcasting (TV, at 900 MHz) near the frequency bands assigned to cellular protocols, threatens
in fact the wanted data through the so-called reciprocal mixing with the skirts of the local
oscillator spectrum. The intermediate microwave passive filters feature considerable selectivity,
but could not remove the interferers to the desired extent.
The divergence of the real oscillation spectra from the ideal Dirac delta is due to the
fundamental phenomenon of phase noise. Analog RF designers are nowadays striving to devise
new frequency synthesizers structures, capable to cope with the tight spectral pureness
specifications set forth by cellular protocols, and the low-power requirements that the hand-held
operation of these circuits implies [1,2]. The frequency reference is usually obtained by a PLL
(Phase Locked Loop), into which the phase noise contributed by the VCO (Voltage Controlled
Oscillator) plays the leading role. This Ph.D. work addresses the oscillator topology that, up to
now, is reputed the best suited to achieving the lowest phase noise: the LC-resonator VCO
scheme (compare for example the ring in [3] with the LC oscillators in [4-8]). Unfortunately
enough, the reactive tank approach imposes either to adopt an off-chip, bulky inductor (as in
[4,5]) or to lay out a metal spiral inductor featuring a very poor quality factor Q (as done in [68]; for inductor analysis and technology, see for example [9-11]). The first option is by far the
least repeatable and the most power-hungry, and badly matches a battery-operated system
scenario; then a major struggle is actually carried out towards the realization of low phase noise
but fully-integrated LC-tank oscillators.
The work is embedded in this operating frame: the RF ICs are to be implemented on
silicon, for sake of cost effectiveness; in a bipolar technology, that still represents the standard
choice for the integration of oscillators, due to flicker noise concerns. We had access to a highspeed bipolar technology (HSB2) by STMicroelectronics - Catania site, whose fT is about 18
GHz; nonetheless, the frequency range explored was around 2.5-2.6 GHz, and the active devices
in the VCO were brought to their knees. Such a frequency range is employed for DAB (Digital
Audio Broadcasting) applications, and includes the ISM (Industrial, Scientific and Medical)
1
Introduction
bands, where many spread-spectrum standards suitable for 3-Generation wireless applications
are allocated. Although the practical VCO is a simple circuit, its inherent non-linearity and the
high frequencies of operation make the optimization of it a unique challenge. As we will see, the
phase noise topic lent itself to the development of various theoretical, simulation, and design
considerations.
Blocker
TV Broadcast
Wanted signal
Blocker
Wanted
signal
LNA
DIPX
Rx
LO
LO
SAW FILT
PLL
PA
Tx
Fig. 1 General scheme of a wireless transceiver, and intermodulation effect of the phase noise.
A widely accepted way to quote the phase noise performance of an oscillator is to
determine its SSCR(α): Single Sideband to Carrier Ratio, or the ratio between the phase noise
lying in a 1 Hz band at a frequency α away from the carrier, and the power of the carrier itself.
This figure of merit – sometimes denoted also with (α) - must comply with precise
specifications imposed by the standardization organizations, which set suitable “masks” of noise
under which the parameter must always be kept. The specs taken as reference in this work are
the ones of the European standards, cordless (DECT, Digital European Cordless Telephone) and
cellular (GSM, Global Standard for Mobile communications):
DECT →
GSM
→
SSCR < -98 dBc/Hz @ 100 kHz
SSCR < -112 dBc/Hz @ 100 kHz
The parameter is measured in dBc/Hz, or dB relative to the carrier power, in 1 Hz
bandwidth. These limits descend from the worst-case interference between a strong sinusoidal
tone lying in the neighbor channels (blocker) and a feeble wanted signal. For example, Fig. 2
illustrates the 3 MHz-blocker condition that imposes the most stringent requirement on SSCR, in
the GSM case.
2
Introduction
-23 dBm
Max. interference
-160 dBm/Hz
α===2π 100 kHz
3 MHz
200 kHz channel
Blocker
Fig. 2 GSM spec on the phase noise of the Local Oscillator (LO).
The specifications assure that the BER (Bit Error Rate) at the DSP end of the receiver
chain is < 10-3, and the quality of the received voice signal is compliant with the classical
Fletcher-Munson audio curves. From 3 MHz, the SSCR figure can be translated to the more
popular 100 kHz offset by assuming that the phase noise skirts follow the classical α-2
dependence.
Throughout the Dissertation, unless otherwise stated, we will refer to the SSCR as
directly measured at the output of the VCO. However, some of the test chips performed a
frequency division by 2 before exporting the signal off-chip, leading to a 6-dB enhancement of
the real external performance.
II Main results of the research activity
From general phase noise analyses [12,13] that have been revised in critical manner, it
comes out that the SSCR worsens linearly when the loaded quality factor Q of the tank is
decreased, but it improves quadratically with the oscillation amplitude A0. Therefore, a
straightforward way to counterbalance the poor quality factor of integrated spiral inductors
seems to be the rise in the oscillation amplitude of the VCO.
While the phase noise performance enhancement was attempted, pursuing A0 increase on
an embedded test-VCO chip available, it was discovered that the improvement predicted by the
theory is no longer attained over determinate amplitude. From there on, the SSCR is surprisingly
worsening with the increase in A0. This effect cannot be simply ascribed to changes in the nonlinearities of the transconductor driving the LC tank, nor to increased loading of the quality
factor. An extensive investigation led also to assert that the AM-to-PM conversion effects could
not explain this behavior in turn.
Experimental evidences provided by ad-hoc tests suggest that the SSCR is spoiled by a
modulation of the phase delay along the oscillator feedback loop, due to the noise affecting the
transconductor bias current: the so-called indirect instability. This latter arises since the RF
oscillation frequencies are not several decades lower than the other singularities, introduced by
the active elements of the stage. This interpretation has been validated by simulations and
quantified with appropriate sensitivity coefficients, which can be evaluated either experimentally
3
Introduction
or via circuit simulations. Some other potential phase noise sources have been characterized via
the sensitivity analysis, turning out to be non-limiting. Moreover two novel simulation
techniques are proposed, allowing for fast and accurate predictions of the phase noise in
oscillators, that can be carried out adopting inexpensive software such as PSpice.
A simplified formula for the prediction of the noise spectral density coming out of the
AAC (Automatic Amplitude Control, a feedback amplitude regulator often associated to the
VCO) has also been devised. Despite the time-varying fashion of such a noise, the problem has
been effectively reduced into a 1-dimensional, back-of-the-envelope tractable paradigm.
The last products of this work are of course the new designs of the AAC, the mirroredColpitts oscillator, the inductor synthesis VCO, and some layout alternatives for Q improvement
of the spiral inductor. Also some ideas about how to widen the tuning range led to an integrated
solution. A total of 6 test chips and 17 VCO versions has been laid out, and two RF boards
suitable for the testing phase have been designed and successfully employed.
III The map of this document
This Ph.D. dissertation will be organized following two tracks: a horizontal progression,
and a vertical one. The horizontal “watermark” of the Thesis is given by the chronological
sequence of analysis, measurements, new test chip versions and new test boards we performed,
or designed. The vertical dimension is the progressive understanding of the effects that limit the
phase noise performance of the VCO: this will be actually developed throughout the Chapter
sequence, dictating the proper way of partitioning the horizontal flow.
In Chapter 1 a non-linear theory for the phase noise accounting in LC-tank VCOs is
briefly summarized, developed at Politecnico di Milano in part during prior work and extended
during this Ph.D. Course. The basic concepts of noise folding are highlighted, and some tangible
simulation results are provided at once. The oscillators TIBIA and STARMAN (chips, and
demonstrator boards) that were initially delivered to us by STMicroelectronics will be then
characterized from a SSCR standpoint. In Chapter 2 an unpredicted feature of the SSCR at
increasing oscillation amplitudes will lead us to approach the quality factor loading phenomena.
This effect will be eventually ruled out, however, together with the AM-to-PM conversion
mechanisms that are analyzed in Chapter 3, with the aid of behavioral (Matlab), schematic
(STSpice, Eldo) and also device-level (Dessis) simulators. The non-linearities of the
varactors used to tune the resonating frequency of the tank will be addressed there.
The measured data will however remain unexplained till Chapter 4, when the indirect
sensitivity concept will permit to achieve an excellent matching between predictions and reality,
even in experiments purposely set up. Such an extended analysis was made possible by the
availability of the board named STARMAN-CUT 1.1, the richest in testing inlets and outlets
provided by ST on our demand. The complicated assessment of the time-varying noise typical of
the AAC regulating the VCO will be focused in Chapter 5. Starting from the theoretical
investigation of the autocorrelation of the AAC switched noise, and after Matlab-Simulink
simulation of the random process, we devised a simple formula capable of predicting the noise
amount in various switching regimes. This analysis called for confirmations from the
experimental evidence, provided by means of a low-frequency, discrete-components test circuit,
and led to explain further measurements on the integrated VCOs.
Further on, the test chip FRAME6 will testify the validity of the first design modifications
described in Chapter 6, and will run onto the first RF board internally designed at Politecnico
(Chapter 8). The principles inspiring the design of some other VCO test circuits are reported in
4
Introduction
Chapter 6, too. The dissertation is concluded with the 6 chips, for 17 VCO versions, of the
RUN0799 project; entirely designed within the course of this Ph.D. work, they exploit the
principles developed throughout the 3-years long activity. The layout essentials along with some
tricks, especially inductor improvement techniques, have been collected in Chapter 7, and the
board used to test them is engineered in Chapter 8 again.
IV About the style of exposition
I will spend the last few words about the style of writing adopted in this text.
We have tried to preserve a practical approach in the exposition of the work that has been
done. For example, congruous space has been devoted to the description of the final test chip
schematic design and layout realization, trying to put into evidence the various RF peculiar
techniques exploited. The design flow of the two test PCBs that have been fabricated in order to
accommodate the test chips has been thoroughly described too. The Politecnico di Milano
Electronics Group was in fact relatively novice in this field, and this Ph.D. Dissertation will
hopefully be useful as starting documentation for my forthcoming colleagues.
5
Chapter 1
A non-linear phase noise theory
Chapter 1
A non-linear phase noise theory
In [12] a theory of the noise transfers in negative-resistance LC-tank voltage controlled
oscillators was presented, capable of accounting for the non-linear operation of the
transconductor. In this Chapter we recall how the switching regime of the transconductor
causes a folding of the wide-band noise, such as the thermal noise of the spreading resistance of
the BJT transistors of the transconductor and the noise of the tail current generator. The
phenomenon is similar to what happens in sampled systems; however, for a careful evaluation
of the oscillator phase noise, the study of correlations between the folded terms is of chief
importance. The rationale behind the effects, and how to account for them, is first given; a
sample assessment of their impact on the oscillator noise performance on a 1-GHz LC VCO is
then proposed here.
1.1 The starting point
O
ne of the aims of this Ph.D. Thesis work is to clarify how the noise sources of the
active and passive devices contribute to the output phase noise of the oscillator,
giving some handy guidelines for the circuit optimization and applying the
devised concepts to alternative test structures. The starting point of the whole activity has been
the theoretical analysis of the operation of a typical LC-tank differential oscillator structure,
frequency-tuned by means of varactors. Its topology is depicted in Fig. 1-1, and will be used as
reference in the following of the Chapter.
Fig. 1-1 Schematic structure of a differential LC-tuned oscillator.
6
Chapter 1
A non-linear phase noise theory
For sake of simplicity, throughout this work we will often use the term “frequency” for
“angular frequency”, represented with w rather than f and measured in rad/sec. Moreover, the
noise will be represented by using the double-sided power spectral density; for instance, the
Johnson noise of resistors will be written with a power spectral density 2kTR, but with both
positive and negative frequency components.
1.2 Working principle of the LC-tank oscillator
First of all, let us briefly recall the operating principles acting in the negative resistance
oscillators, and establish some common ground on the terminology used hereinafter. Fig. 1-2
represents the single-ended equivalent of the oscillator under study. In the small-signal regime
the cross-coupled bipolar pair features a negative resistance equal to -2/gm, where we indicate
with gm the transconductance of each transistor. The figure also reports the input-output current
characteristic of the transconductor, with the input and output variables normalized to the
thermal voltage VT and to the tail current ITAIL respectively. The symbol w0 =1/ÖLC denotes the
central frequency of the bandpass loop filter, while the overall losses of the passive resonator are
represented by the equivalent conductance g0t in parallel to the tank, given by:
g 0t = g pC + g pL +
w 0 C 2
g sC
+
1
w 0 L 2 g sL
(1.1)
In the previous calculation, the terms gsC and gsL are the parasitic conductances in series
to C and L respectively, whereas gpC and gpL account for the conductances in parallel to the same
reactive elements. The quality factor of the tank is computed through the simplest definition
[3],[14], Q = w0/BW where BW = g0t/C is the bandwidth of the loop filter taken at -3 dB.
Fig. 1-2 Single-ended equivalent of Fig. 1 with current noise source accounting for additive noise. The
I-V characteristic of the transconductor is shown, with the output current normalized to the bias current
of the differential stage. The input voltage is normalized to the thermal voltage.
7
Chapter 1
A non-linear phase noise theory
The self-sustaining oscillation occurs for w = w0, and as the differential pair is driven
well beyond its input linear range the transconductor output current resembles a square wave at
w0. However, it could be noted that the harmonic component at w0 is the only component of the
signal passing through the loop filter. Provided the Q is high enough, all the other harmonic
components are cut off by the filter; in Chapter 4 a brief discussion of what happens otherwise
will be proposed. Therefore, the real transconductor transfer may be quantitatively characterized
by introducing an effective transconductance, denoted by gmEFF, given by the ratio between the
output current component at w0 and the input voltage amplitude at the same frequency. If the
amplitude of the voltage signal is small, the remaining current harmonics virtually do not exist
and the effective transconductance coincides with the small signal parameter gm/2=ITAIL/(4VT).
As the input amplitude - the oscillation peak A0 - increases beyond the input linear range, the
output power is transferred in part to the higher harmonics and the effective transconductance
decreases below gm/2. In the hard limiting regime, when the current output waveform is a square
wave, it approaches the value gmEFF = 2ITAIL/(pA0). This latter result is easily derived by taking
into account that, the amplitude of the fundamental component of a square wave ranging
between ±ITAIL/2, is given by 2/p×ITAIL. In the circuit in Fig. 1-2, the amplitude of the oscillating
differential signal A0 gets clamped at about 0.7 V by the saturation of the base-collector junctions
of the bipolar transistors.
Finally, the oscillation is self-sustaining when the loop gain at w0 is equal to one, i.e.
gmEFF/g0t = 1, as stated by Barkhausen criterion for oscillators. This means that the losses g0t are
perfectly counterbalanced by the transconductance of the positive feedback transconductor, and
the tank reduces to a parallel connection between the inductor and the capacitance. Then the
following relation is inferred:
2 I TAIL
×
p g 0t
A0 =
(1.2)
At startup, the negative small-signal transconductance must of course be superior to the
final gmEFF at equilibrium.
1.3 Linear analysis of the oscillator noise
The noise spectral density of the output voltage, Snv, is usually estimated by representing
the overall circuit noise with a current noise source Sni in parallel to the tank. This noise is
usually referred to as additive noise. The equivalent current noise generator forces a reactive
impedance Z(w) given by the parallel of L and C, as shown in Fig. 1-2. By labeling a as the
frequency offset from w0 , for a << w0 it may be written:
Z w 0 ± a »
2
1
2aC 2
(1.3)
and therefore:
S nv a =
S ni a 2aC 2
=
1 S ni w 0 1
4 g 0t C Q a 2
(1.4)
8
Chapter 1
A non-linear phase noise theory
Due to the sharp Bode diagram of the LC resonator, the output spectrum shows typical
tails decreasing from w0 as a2: these represent a kind of signature of the phase noise presence
onto an oscillation.
Notice that the phase noise profile given by (1.4) goes to infinity as a ® 0, i.e. as the
carrier is progressively approached, in this simplified model. The real phase noise spectrum
features instead a Lorentzian (single-pole) behavior close to the central frequency: this can be
formally treated as in [15], or tracked back to the work by Edson [16], and has been more
recently studied in [17] from a noise amplitude distribution standpoint. The ultimate reason
behind this fact can be understood by considering a sinusoid with white gaussian frequency
noise. The width of the distribution of its zero-crossing occurrences instants is bounded with
respect to the observation time, because the phase is inherently circular, and cannot exceed 2p;
even bringing to infinity the time of observation of the noisy sinusoid, the zero-crossing position
variance does not burst. If each zero-crossing could be univocally labeled, so as to make it
distinguishable from all the others, the variance of its occurrence time will instead diverge - and
so will do its spectrum near the carrier.1
A first contribution to Sni in Eq. (1.4) arises from the thermal noise 2kT/g0t due to the
ohmic parasitics of the loop filter. Otherwise stated, the equivalent conductance g0t given by Eq.
(1.1) not only determines the quality factor of the filter, but it can also account for the thermal
noise deriving from the parasitic resistances of the tank.
The noise of the transconductor can be effectively represented by relating it to the tank
noise contribution, i.e. by adding a current spectral density 2kTg0t×F, where F is a suitable noise
factor. Therefore we have Sni = 2kTg0t×(1+F), and from Eq. (1.4) the output voltage noise may
read:
S nv a =
1 kT w 0 1
1 + F 2 C Q a2
(1.5)
All the difficulty of the noise calculations is now “hidden” within F, the noise factor of
the differential stage. Usually, F is estimated by considering the circuit in the linear region, with
the differential stage perfectly balanced. Despite the wide popularity of such an oversimplified
procedure, it lacks of theoretical support. For example, by taking into account the noise sources
modeled as in Fig. 1-3 and their mutual correlation in output, simple calculations give:
I
I
æ
2kTg 0t F = 2çç 2kTrbb ' g 02t + q TAIL + q TAIL
8b
8
è
1
ö
÷÷
ø
(1.6)
A further, very elegant alternative view is an exquisitely stochastic one. Since the phase noise can be regarded as
the integral of the frequency noise, in many cases it happens to be the integral of a white spectrum process (just
imagine a white voltage noise affecting the tuning node of a VCO). In these cases the phase noise is the classical
random-walk, or Wiener process, also used to model Brownian motion in physics. The “particles” (or, zero
crossings) involved in the phase Wiener process are not infinitely light, but have instead a certain “mass” (or,
displacement limitation mechanism) that depends on the Q of the system, as can be inferred from [16]. This inertia
prevents the phase noise spectra from going to infinity near the carrier.
9
Chapter 1
A non-linear phase noise theory
Fig. 1-3 The oscillator circuit completed with noise sources.
The first term on the right hand side is the equivalent current noise due to the spreading
resistance; the second term considers the shot noise of the base current, while the third one
comes out from the shot noise of the collector current ITAIL/2. The shot noise of the base current
plays a negligible role. The factor 2 out of brackets accounts for the presence of two transistors.
Finally, the noise factor is given by:
I
q
F = 2 rbb' g 0t + TAIL
(1.7)
g 0t 8kT
and the SSCR is:
SSCR a =
2 S nv a 2 kT w 0 1
1 + F = 2
A02 / 2
A0 C Q a 2
(1.8)
where the factor 2 before Snv accounts for the double-sided noise spectrum.
From this expression it turns out that, independently of the F value, an improvement of
the SSCR requires:
1. obviously enough, the increase of the Q factor of the tank (enhanced selectivity)
2. the adoption of a large capacitance C
3. a large signal amplitude A0 to reinforce the carrier.
The second requirement would make the tank varactors outweigh the capacitive
parasitics, and is thus desirable from a tunability standpoint. Nevertheless, it leads the designer to
spend more current to achieve a given A0, and trades off with the latter guideline. The last
requirement suggests driving the transconductor in a highly non-linear regime, and thus it makes
substantially not satisfactory the noise calculations based on the linear theory framework. In the
following, the linear approach is shown to either underestimate or completely neglect some
important noise sources. A non-linear theory for the phase noise transfers is needed.
10
Chapter 1
A non-linear phase noise theory
1.4 Harmonic transfer in non-linear systems
Consider the transconductor input signal given by a sinusoidal tone Vl(t) at frequency w0a, superimposed to the carrier V0(t) = A0×cos(w0t). If the transconductor characteristic is I = I(V)
as depicted in Fig. 1-2 and the amplitude of the tone Vl(t) is a small signal with respect to A0, the
transconductor output signal can be approximated to first order with:
I V0 t + Vl t » I V0 t +
dI
dV
Vl t (1.9)
V 0 (t )
The derivative dI/dV is the static transconductance g(V), which in the above equation is
evaluated in presence of the carrier only, V0(t), by following a perturbation approach. It is
important to note that, within the cosinusoidal carrier frame, g(V0(t)) is an even function of the
time with a fundamental component at 2w0. The corresponding Fourier expansion results in:
g V0 t =
+¥
g
å
= -¥
( 2n )
× e j 2 nw 0 t
(1.10)
n
where all of the coefficients g(2n) are real. Furthermore, g(V0(t)) has an odd symmetry within each
period, thus the coefficients feature alternated signs.
Despite a much more lengthy and rigorous derivation is possible, the most immediate
way to grasp the working principle of the entire transconductor analysis is to note that, since the
current is:
I 0 t = g V0 t × V0 t (1.11)
the output current harmonics are given by the convolution of the voltage harmonics with the
transconductance coefficients. The concept is intuitively understood from Fig. 1-4, in which also
an upper tone Vu(t) at w0+a has been inserted in the oscillator loop.
Fig. 1-4 Convolution between the voltage noise spectrum at the output of the loop filter a), and the g(n)
terms b). c) shows the first contribution, resulting from g(0) , d) results from the lower g(2).
11
Chapter 1
A non-linear phase noise theory
The Eulerian voltage components capable to map over the current component at w0, after
the convolution with the g2n expansion, are only two: V0(w0) and its complex conjugate V0(-w0)*.
Thus the expression for I0 becomes:
I 0 t = g (0) - g (2) × V0 t (1.12)
In the last step, we exploited the definition of the effective transconductance as the ratio of the
harmonic quantities at w0.
Let us devote to the second term in the right hand side of Eq. (1.9): it gives rise to the
intermodulation tones at frequency nw0±a. Again, they can be calculated by means of the
convolution:
æ Vl j w 0 -a t Vl * - j w 0 -a t ö + ¥
÷ * å g ( n ) V0 × e jnw 0t
I 0 t = ç e
e
+
(1.13)
ç2
÷ n = -¥
2
è
ø
(
)
(
)
into which, this time, 4 terms play a role. According to this equation the input tone Vl at w0-a
generates two intermodulation terms: Il at w0-a, given by g(0)Vl, and Iu at w0+a, given by g(2)Vl.
Symmetrical terms are generated by the input tone Vu at w0+a.
Fig. 1-4 schematically shows how the transconductor transforms the entire input noise
spectrum limited by the loop-filter bandwidth. The convolution let us appreciate how the g(2n)
expansion taps perform a mixing action on the tones; even if Vl and Vu represent two
uncorrelated noise components at the transconductor input, the output tones at w0±a are instead
correlated.
When a small-amplitude sinusoidal tone is superimposed to a carrier, it creates an
amplitude and a phase modulation (AM and PM). This fact is well known in communication
theory, and the adoption of the orthogonal decomposition of the noise into AM and PM
components has generated a whole class of noise simulation methods (see for example [18][20]).
It may be worthwhile to derive the expressions of the AM and the PM transfers of the
noise due to the injection of Vl and Vu. The first type of transfer can be easily rejected at the
output by using a hard-limiter, sensitive only to the zero-crossings of the waveform; the last is
instead more difficult to treat, and is the one we are interested to. Let us consider the presence of
a single tone, for instance Vl, superimposed to the carrier. The resulting voltage signal can be
represented with the aid of phasors as in Fig. 1-5, which shows the phasor of the tone rotating in
the iso-frequency frame synchronous to the carrier at w0.
Fig. 1-5 AM and PM components resulting from an interfering noise tone. The phasors refer to the
carrier rotating at w0 .
12
Chapter 1
A non-linear phase noise theory
A similar decomposition holds for Vu also. The same expressions hold for the output current of
the transconductor: the counter-rotating current phasors are obtained by converting the voltage
tones via their relative periodic transconductance expansion coefficients. For example, the AM
can be obtained from:
I l w 0 - a I l* w 0 + a V w - a V * - w 0 + a +
= g (0) l 0
+ g (2) l
2
2
2
2
(1.14)
and then it is gAM = g(0) + g(2). Analogously proceeding for the PM, we have:
I l w 0 - a I l* w 0 + a Vl w 0 - a Vl* - w 0 + a = g ( 0)
- g ( 2)
2
2
2
2
(1.15)
and gPM = g(0) - g(2). From Eq. (1.12), moreover, it is recognized that gPM = gmEFF.
Fig. 1-6 reports the dependence of gAM and gPM as functions of the input signal amplitude
for a bipolar differential stage. When the input voltage peak exceeds the linear range, the stage
behaves like a limiter and becomes nearly insensitive to the amplitude variations: the AM
component is cut off, and gAM ® 0. In fact the output current waveform always resembles a
square wave, and any change in the input amplitude brings no influence on the clamped output.
On the contrary, the transitions of the current square wave occur when the input signal crosses
the zero level. Any time displacement of the input waveform causes a time shift of the output
transitions, then the PM component of the input voltage is transmitted at the transconductor
output, and eventually gPM = gmEFF.
Fig. 1-6 Dependence of the AM and PM transfer coefficients of a bipolar differential pair biased with 1
mA, as a function of the amplitude of the input signal.
These results lead to a well known correction to the (1.8): for totally uncorrelated noise,
one half of the total noise power contributes to the amplitude modulation, while only the other
half pertains to phase modulation. When A0 >> 2VT, the differential stage modeled in Fig. 1-2
behaves as a hard limiter and only the PM component is passed to the output. It follows that the
noise power spectral density in (1.8) must be divided by 2, obtaining:
13
Chapter 1
A non-linear phase noise theory
S nv a =
1 kT w 0 1
1 + F 4 C Q a2
(1.16)
The non-linear behavior of the active element of the oscillator implies consequences
much more profound than the simple introduction of the above factor 2. By exploiting Eq. (1.13)
it can be demonstrated that the intermodulations between the carrier and wide band noise sources
cause noise folding effects that worsen the transconductor noise factor F.
1.5 Noise due to the base spreading resistors
Let us pay attention first to the thermal voltage noise due to the spreading resistance of
the bipolar transistors, depicted in Fig. 1-3. This source has double-sided spectral density 2kTrbb’.
Provided Eq. (1.11) holds (and, for the small perturbations inherent in a noise analysis, this is an
assumption always valid) the voltage source can be convoluted with the taps of the Fourier
expansion of time-varying transconductance of Eq. (1.10). Even if the system is a non-linear one,
to a first order it can be studied with slightly increased effort than for linear analysis. Since the
system is non-linear, the current noise in(t) produced on the tank should be non-linearly related to
the voltage noise stimulus. The non-linearities are taken into account by the term g(V0(t)),
however, while the convolution practice is still correct.
If the transconductor operates as an ideal hard limiter, the output current is a square
wave, and g(V0(t)) reduces to a sequence of Dirac-delta functions at frequency 2w0. The Fourier
spectrum of g(V0(t)) features infinite terms given by (-1)n·d(w-2nw0 )×g0t/2, and the
transconductor current spectrum is obtained by convoluting these delta sequence with the
wideband noise. Fig. 1-7 schematically shows the thermal noise spectrum with a wide bandwidth
0 ® Nw0. The convolution entails a noise folding, similarly to what happens in sampled systems.
The noise components that fold within the filter bandwidth are the ones close to the frequencies
±(2n+1)×w0, indicated by the dashed areas in Fig. 1-7. Each folded replica is weighted by the
g(2n) factor reported on the right side of the corresponding spectrum.
Fig. 1-7 Folding of the noise spectrum of the spreading resistance. The different spectra represent the
folded contributions, while the dashed vertical lines identify the equivalent bandwidth of the loop filter.
14
Chapter 1
A non-linear phase noise theory
The correlation between the terms folded at w0±a needs some remarks. If one considers
the noise terms at frequencies (2n+1)w0±a, they are downconverted around the central
frequency w0 by the Fourier coefficients g(2n) and g(2n+2) lying near them. Also (1.12) derived
from this convolution of multiple terms, considered in the DC proximity. In order to understand
that the modulation obtained is entirely of PM kind, we can depict the result of the convolution
for the noise component Vu as in Fig. 1-8.
The Vu noise component at (2n+1)w0+a gives rise to current tones at the transconductor
output both at w0+a and at w0-a, together with other beating terms not represented in the figure.
Since g(2n+2) and g(2n) have the same module g0t/2, but opposite signs, the tones rising at w0±a are
always orthogonal to the carrier, thus leading to a phase modulation. The magnitude of the
Fourier coefficient g0t/2 can be directly inferred by the balance gmEFF = g0t stated at w0. The
resulting contribution to the single sideband phase noise, measured for example at w0-a, is:
2
æ g 0t ö Vu ( 2 n +1)
ç
÷
2
è 2 ø
2
2
æg ö
= ç 0t ÷ 2kTrbb '
è 2 ø
(1.17)
Fig. 1-8 Phase modulation of the carrier due to a single noise tone at the transconductor input.
Taking into account that a similar term results from the symmetrical Vl at (2n+1)w0-a,
and that the number of folded replicas is N/2, we compute the overall noise power spectrum as:
2 × 2kTrbb '
g 02t N
2 2
(1.18)
where the first doubling factor is due to the presence of two transistors. The contribution of the
term to the F factor in (1.16) is obtained dividing Eq. (1.18) by kTg0t, i.e. the reference phase
noise caused by the loss conductance alone:
F = 2rbb' g 0t
N
2
(1.19)
This derivation holds under the assumption that the transconductor behaves as an ideal
hard limiter. In reality, the folding factor that multiplies the expression 2rbb'g0t will depend on
both the slope of the I(V) characteristic of the transconductor, and on its bandwidth. The effect of
the I(V) characteristic can be discussed while looking at Fig. 1-9.
The figure shows the folding factor extracted after the behavioral simulation of an ideal
bipolar differential pair. The coefficients g(2n) have been numerically derived as a function of the
oscillation amplitude, when the transcharacteristic is modeled with an ideal hyperbolic tangent
I(V). The lower continuous line in Fig. 1-9 shows the folding factor computed by summing all
the contributions up to g(10): this corresponds to assuming a stage bandwidth of Nw0, with N =
10.
15
Chapter 1
A non-linear phase noise theory
As the amplitude increases, the current transitions become steeper and steeper, the g(2n)
coefficients approach the limit value g0t/2 explained above, and even the high frequency noise is
folded within the loop filter bandwidth. Correspondingly, the folding factor approaches the ideal
N/2 value as A0 is raised. The dashed line in figure shows instead the folding factor obtained by
assuming infinite bandwidth: as A0 increases, progressively higher-order g(V0(t)) harmonics
become significant, and capable of downconverting the noise components lying at higher and
higher frequencies. The dashed curve may be regarded as a worst case prediction, and is useful
for conservative first-order estimates.
Fig. 1-9 Folding factor of the base noise for a bipolar differential pair versus the amplitude of the input
signal. The continuous line refers to a noise bandwidth of 10×w0, while the dashed line is obtained for no
bandwidth cut-off (worst case).
The folding factor has also been derived after transistor-level simulations; STSpice
accounted for bipolar device models and parasitics in detail.
The thermal noise of the spreading resistance can be modeled as a superposition of
harmonics, according to Campbell’s theorem [21]. Therefore, the transfer of each noise
component to the output of the oscillator can be studied by placing a sinusoidal voltage
generator, with small amplitude, in series to the transistor base. This approach was devised
already in [22] and has been applied in [3] to characterize the performance of ring oscillators.
Fig. 1-10 shows the results of a simulation carried on by means of STSpice on a circuit having
the same structure reported in Fig. 1-1. The tank has 2×C = 10 pF, L/2 = 2.36 nH with quality
factor Q = 10, leading to an oscillation frequency of 0.997 GHz with a loss conductance g0t =
(w0C)/Q » 320 W-1. The transistor models were the ones pertaining to the high-speed bipolar
technology for wireless communications that will be used throughout the Thesis (HSB2 by
STMicroelectronics), and featuring a fT = 18 GHz.
Fig. 1-10a illustrates the output spectrum obtained when the stage has been biased with
ITAIL = 2 mA, and 1 mV voltage tone is injected in series to one of the transistors at w0+a - with
a = 2p×5 Mrad/sec. In order to consider only the phase modulation, the oscillator output was fed
into a hard limiter; the image reports the FFT of the signal at the limiter output. As expected,
there is no phase modulation arising within the bandwidth of the loop filter, near the carrier. The
same happens when the tone frequency is shifted to even multiples 2nw0±a, in agreement with
the insights achieved with the folding theory discussed above.
16
Chapter 1
A non-linear phase noise theory
a)
b)
Fig. 1-10 Spectrum of the oscillator output after cut-off given by a hard limiter. Voltage side-tones are
forced in series to the base of transistors: a) - at even, b) - at odd multiples of w0.
According to the theory, the phase modulation must arise instead when tones are injected
close to the odd harmonics, at (2n+1)w0±a. Fig. 1-10b clarifies that this is effectively the case.
The folding factor can be quantified by performing similar simulations. A single tone of
amplitude Vb (1 mV in our case) has been forced at (2n+1)w0±a, and the power of its replica
folded at w0±a could be consequently derived. Fig. 1-11 depicts the ratio between the power
folded within the loop filter bandwidth, and the maximum theoretical voltage value achievable if
the transconductor operated as an ideal hard limiter, that can be figured out as:
æ g 0t Vb 1 ö
ç
÷
è 2 2 2aC ø
2
(1.20)
Fig. 1-11 Folding of the power of a single harmonic tone at (2n+1)w0+a as obtained from STSpice
simulations. Solid squares refer to the oscillation amplitude A0 = 430 mV, triangles stand for A0 =80 mV.
17
Chapter 1
A non-linear phase noise theory
The results marked with square blocks refer to the case ITAIL = 2 mA, A0 = 430 mV. As
expected, the folding efficiency smoothes down at higher harmonic indexes, and rises with
higher oscillation amplitudes. By reducing ITAIL to 0.4 mA the oscillation amplitude A0 decreases
down to 80 mV, and the folding effects are negligible already after the 7th harmonic tone.
The sum of the values in Fig. 1-11 is precisely the folding factor h to be applied to the white rbb’induced base noise, that should replace the ideal N/2 factor in Eq. (1.19). In our examples, this
factor equals 3.5 for A0 = 430 mV and 1.2 for A0 = 80 mV; these values fall slightly below the
dashed line in Fig. 1-9, due to the unavoidable non-idealities in the real transconductor transfer.
1.6 Noise due to the tail generator
Let us now consider the shot noise, both the one of the two transistors and that of the tail
current generator. Eq. (1.7) contains a term due to the collector shot noise, while the noise of the
tail current is neglected since it acts as common mode source. However, if the oscillation
amplitude reaches values > 300 mV, the differential stage is completely switched during most of
the oscillation period, with a single transistor of the pair conducting the current delivered by the
bias generator. Then the local feedback due to the high impedance of the current source
quenches the fluctuations due to the shot noise of the collector current. In other words, as the
transconductor enters the hard non-linear regime the relative weight of the noise sources
becomes completely swapped. The noise of the bias generator, negligible in the small signal
regime, progressively gains importance whereas the contribution of the collector shot noise is
decreased. The analytical solution can be found at least when the transconductor behaves as a
hard limiter, and relies on the convolution concept previously exploited. Each noise component
of the bias current generator is delivered to the tank via the switching action of the
transconductor, i.e. multiplied by a ±1/2 level square wave with frequency w0. Since the chopper
action of the transconductor can be modeled with mixing in time domain, the resulting
contribution to the additive noise can be computed with the aid of convolution in the frequency
domain.
Notice that, in principle, one may say that the tail generator should contribute only to the
amplitude noise at the output, due to the effect of the mixing on the oscillation envelope. This
conclusion is wrong because of the correlation of the folded components, which held paramount
importance also during the rbb’ noise treatment above. Based on Eq. (1.13), this time it can be
written:
*
æI
ö +¥
I
I 0 t = ç n e jwt + n e - jwt ÷ * å T( 2 n +1) t × e j ( 2 n +1)w 0t
(1.21)
ç 2
÷ n = -¥
2
è
ø
where In represents the generic noise tone from the tail, and T(2n+1) indicates the decreasing
coefficients of the well known Fourier expansion of the square wave, ejnp/p(2n+1). As for the
base spreading resistance, the convolution given is applied to a wideband spectrum. It eventually
turns out that the noise tones folded at frequency w0±a are due to the noise components found
around the even harmonics of w0, i.e. 2nw0±a. This time the folded tones are no longer of the
same amplitude, because the combining T(2n+1) coefficients have no longer the same magnitude;
the phasors can be anyway decomposed into AM and PM contributions. For example, let us
consider the effect of the noise component at 2nw0-a; the AM output sinusoid is given by
18
Chapter 1
A non-linear phase noise theory
I 0- AM t = T( 2 n +1) + T( 2 n -1) × I n* 2nw 0 + a (1.22)
because the sum of a phasor and of its conjugate lies parallel to the cosine carrier; whereas the
PM output needs the inversion of the conjugate phasor, or
I 0- PM t = T( 2 n +1) - T( 2 n -1) × I n* 2nw 0 + a (1.23)
Finally, taking into account signs and other factors we obtain:
I 0- AM t =
4n × e jnp
× I n* 2nw 0 + a p 4n 2 - 1
(1.24)
Similar calculations lead to the expression of the modulations due to the noise at
2nw0+a, that are morphologically identical to the formulas in (1.24), and must be composed
with them to get the whole contribution to the phase and amplitude noise. The amplitude
modulation is:
I l - AM w 0 - a =
1
1
× I n a +
p
p
I n* 2nw 0 - a + I n 2nw 0 + a j n -1 p
×e
å
4n 2 - 1
n =1
+¥
(
)
(1.25)
while the phase modulation can be expressed as:
I l - PM w 0 - a =
1
p
+¥
å 2n n =1
I n* 2nw 0 - a + I n 2nw 0 + a jnp
×e
4n 2 - 1
(1.26)
Hence Il-PM and Il-AM are correlated (which was intuitive) but they are the sum of uncorrelated
terms. Provided the noise spectral density of the tail generator is white, denoting it with SiT
(double-sided) it can be written:
S iPM w 0 - a =
S iT
p2
+¥
å= 2n 2
n 1
4n
2
2
- 1
2
=
S iT
8
(1.27)
A similar expression is found by summing all the coefficient combinations giving birth to
the amplitude modulation. The contribution to the noise factor F is, as usual, the ratio between
the phase noise power SiT/8 and the phase noise power given by the loss conductance:
F=
S iT
8kTg 0t
(1.28)
Performing circuit simulations similar to the ones discussed for the base noise, the
folding of the tail noise in a real oscillator can be quantitatively assessed. The harmonic tones
should now be injected from a current generator placed in parallel to the tail generator. One
single tone must be inserted in the circuit at a time, so as to prevent any distortion of the final
effects on the tank, due to possible correlation.
19
Chapter 1
A non-linear phase noise theory
First of all, it can be verified that the side tones at (2n+1)w0±a are not folded within the
bandwidth of the loop filter, as expected. Phase modulation arises from the tones at 2nw0±a with
n > 0 (inset of Fig. 1-12).
Fig. 1-12 Folding of the power of a single harmonic tone at (2nw0 + a) obtained from STSpice. Square
blocks refer to A0 = 430 mV, triangles to A0 = 80 mV. The crosses show instead the limit values
attainable when the transconductor stage behaves as ideal hard limiter. The inset shows the side-tones (in
milliVolts) arising when a 10 mA current sinusoid at (2w0 ±a) is added in parallel to the tail generator.
The folding factor relative to each tone can be derived by following the same procedure
leading to Fig. 1-11. Fig. 1-12 shows the fraction of the power that gets folded within the loop
filter bandwidth, as a function of the index (2n) of the current tone at 2nw0+a. For phase noise
evaluation purposes, the figure has been derived from the FFT of the signal at the output of the
final hard limiter. The square dots refer to the case of A0 = 430 mV, the triangles to A0 = 80 mV.
The crosses show instead the limit values attainable if the transconductor stage behaves as an
ideal hard limiter. These latter ones are exactly the coefficients:
2n 2
p 2 4n 2 - 1
2
(1.29)
encountered in (1.27). Since the switching regime of the simulated transconductor is not ideal,
instead of the fixed factor 1/8 it is obtained a slightly reduced coefficient, that we will indicate
with s, that is 0.075 when A0 = 430 mV. When A0 = 80 mV it is instead s = 0.034, therefore the
result of Eq. (1.28) will be more properly indicated with s×SiT/kTg0t .
From the above analysis, it comes out that the tones injected at low-frequency a give rise
only to amplitude modulation. In fact they are upconverted in the band of the loop filter by
means of a single coefficient, and they retain their conjugate characteristic without undergoing
the sign inversion necessary to translate into phase noise. This initial finding will be extensively
revised during the Dissertation, and fundamental exceptions will be raised in order to explain the
experimental SSCR measurements available for some test VCOs.
20
Chapter 1
A non-linear phase noise theory
1.7 Wrap-up of the analysis’ results
Concluding the presentation of the non-linear theory for the transfer of the noise sources
in a differential LC-tank VCO, it can be asserted that the switching operation of the
transconductor stage can be properly accounted for by introducing spectrum folding. The doublesided power spectrum of the output voltage noise, at a frequency offset a from the carrier, may
take a general formulation such as:
S nv a =
1 kT w 0 1
1 + F 4 C Q a2
(1.30)
The non-linearities have been concentrated inside the noise factor F, which is given by:
F = 2rbb ' g 0th +
sS iT
kTg 0 t
(1.31)
where the factors h and s have been given suitable values for different oscillation amplitudes A0,
and safe overestimate (N/2 and 1/8 respectively) that may be used in a first-order prediction of
the noise factor. The numerical procedure to be followed in order to get more precise evaluations
of the factors for a generic differential VCO, based on Spice-like simulators, has been briefly
outlined. The final expression for the SSCR is quite different from the one derived from the
linear analysis, as it highlights how the SSCR depends on the folding of the broadband noise
sources. It is of capital importance to note that, while even unexpected as long as the linear
theory is followed, the noise of the tail generator cannot be neglected and may also become
dominant if not properly minimized.
1.8 The role of AM-to-PM conversion
This analysis has been focused directly on phase noise, since the amplitude noise was
assumed as completely cut off by the trailing limiter. However, the non-linearities of reactive
elements like the varactors can cause a conversion of the amplitude modulation into phase
modulation.
Consider as a reference the non-linear C(V) static characteristic of the varactors reported
in Fig. 1-13. The presence of these reactive elements transforms the tank into a non-linear
network, with the instantaneous capacitance C(t) that is function of the oscillation amplitude.
The resonance frequency w0 of such a bandpass filter should be figured out by solving a nonlinear differential equations problem (the Van der Pol oscillator, [23]). Fortunately, the
interaction between amplitude and phase can be qualitatively understood in much easier way, by
taking:
1
w0 =
(1.32)
L C (t )
where <C(t)> indicates the time average of the capacitance over the period; this is far from
rigorous practice, but it furnishes indeed the order of magnitude of the AM ® PM conversion.
<C(t)> can be taken as a sort of “effective” capacitance, Ceff.
21
Chapter 1
A non-linear phase noise theory
C(V)
<C(t)>
V
V0
V tune
Fig. 1-13 The AM-to-PM conversion mechanism caused by rectification effects due to the non-linearity
of the C-V varactor characteristic.
Imagine that the sinusoidal stimulus is affected by amplitude modulation. The DC
average of the distorted capacitance curve will be displaced by the change in amplitude, owing to
rectification phenomena. Then the noise on A0 influences Ceff, it is translated into w0
perturbations, and ultimately into phase noise on the oscillating system.
A first formula that proved useful for attacking the problem relates the oscillation
amplitude to the capacitance, rather than directly to w0. By means of electrical simulators it is
easier to achieve the variations of Ceff with A0, and then translate these perturbations into phase.
This approach makes it natural to utilize the sensitivity definition in order to link capacitance and
amplitude, by defining a KAM-PM coefficient:
K AM -PM =
w 0 ¶ Ceff
×
2a Q Ceff
¶ A0
A0
(1.33)
To close the phase loop, the magnitude of the sensitivity factor is divided by the “loop
gain” of the oscillator: the input frequency deviation ® output phase deviation proportionality
term is 2aQ/w0, or the frequency offset a written as a fraction of the tank bandwidth (w0/2Q).
For oscillators such as the one of Fig. 1-2, this is the shaping factor to be applied to the parallel
sources in order to transfer them at the output (see also [20,24,25]). The typical 2Q/w0 slope in
proximity of w0 gives the qloop ® fOUT phase transfer for the well known LC-tank phase relation;
a-1 accounts for the phase accumulation over time. Since this is already a “closed loop”
standpoint, the squared (here is why the absolute value) coefficient in (1.33) does not need to be
complemented with other terms, to obtain the final SSCR. Once the AM voltage noise SvTANK
affecting the tank is known, the quotient with the carrier power can be immediately performed:
SSCRAM - PM =
2
SvTANK × K AM
- PM
2
A0 / 2
(1.34)
The definition of KAM-PM given in Eq. (1.33) is promptly applicable after the simulations, and
quantifies the real kernel of the AM-to-PM conversion [26]. It will be recalled and better
understood in Chapter 4, for comparison with the black-box sensitivity definition used to directly
assess the oscillator stability concept.
22
Chapter 2
Measurements vs. predictions and Q-loading
Chapter 2
Measurements vs. predictions
and Q-loading
This Chapter compares the theoretical phase noise predictions with the experimental results
available for some test VCOs of STMicroelectronics (TIBIA, STARMAN RF demonstrators). The
results are in good agreement with each other and with SpectreRF prediction, as far as the AAC
is switched off. Otherwise, under-estimates as high as 40 dB are observed, which progressively
increase at high amplitudes. The SSCR characterization with increasing oscillation amplitudes
A0 shows that the phase noise reaches a minimum and then starts rising. The analysis of the Q
degradation at high A0 does indicate a worsening in the efficiency of the VCO core (the negative
transconductor), which anyway is numerically not sufficient to explain the astonishing phase
noise spoiling observed.
2.1 Chronology of the test VCO sequence
T
he phase noise analysis began with the experimental characterization and
theoretical explanation of the performance of LC-tank bipolar VCOs. Fortunately,
our work did not start from scratch, but it was triggered by some pre-existing
structures of integrated oscillators. Those VCOs belong to STMicroelectronics and were part of
demonstrator transceivers for DECT and DAB (Digital Audio Broadcasting) applications.
The RF development evolved in 5 phases, the last 4 of which were shared with the
Politecnico di Milano: GIRAFE (VCO for CT2, a cordless communication standard), TIBIA (for
DECT deployment, cordless), and finally the STARMAN project (to meet DAB requirements, for
satellite-to-mobile-terminal communications). This last phase was in turn divided in three steps:
· CUT 1, of which we obtained a standard test board not customized for extended laboratory
analysis; these were the first RF characterization activities ever made in this University
· CUT 1.1, modified according to some results of the analysis of the former oscillator; we
received a modified test board, from which practically all of the critical nets of the VCO were
made available out of chip, thanks to the reassignment of the pins
· FRAME6, for which we designed a new RF test board by modifying the former ST boards
(originally engineered at the Fraunhofer IIS in Erlangen, Germany).
The successive pace has consisted of the silicon integration of the ICs fully designed at
Politecnico, that constitute one of the concrete products of the Ph.D. Thesis. Since the circuits
23
Chapter 2
Measurements vs. predictions and Q-loading
were actually realized with a run held in July 1999, in the following they will be globally
referred to as RUN0799.1
2.2 A glimpse at the HSB2 technology
The whole sequence of the circuits that have been characterized was realized in a HighSpeed Bipolar silicon technology, which migrated from HSB2-P46 to HSB2-P30 after the
innermost metal pitch was shrunk from 4.6 mm down to 3.0 mm. The process provides 3 levels of
metal, and dielectric trench isolation that will be used to separate the critical devices, blocks and
circuits [27].
The technology comprises 3 kinds of NPN bipolar transistors, depending on the electrode
placement: B-E-C for the area-optimal B-type, B-E-B-C for the speed-optimal and low-rbb’ Ctype, or the interdigitated C-B-E-B-E-B-C multi-base F-type devices for high current duties. The
emitter length ranges from 2 mm (F2) to 12 mm (F12). The bipolars are characterized by a
common transition frequency fT > 18 GHz; the parasitic capacitances vary with the area of
course, but remain in the range of tens of femtofarads. The base is shorter than 800 Å and can
put in jeopardy the noise performance due to flicker contribution. Lateral PNP transistors are
used for current sources only.
The capacitors can be high-quality, Metal2-to-Metal3 (10% tolerance); or area-effective,
Metal1-to-Polysilicon, contacting also the epi-layer (this is a unidirectional structure). The
capacitance-per-area ranges from 0.3 fF/mm2 up to 0.7 fF/mm2. The varactor is obtained from the
standard base-collector junction of a NPN, plus an additional pedestal implant to tailor the
linearity characteristics of the diode. CJ0 at 0 V bias is 1.0825pF, the built–in voltage fbi = 0.9 V.
This device will be thoroughly analyzed in Chapter 3.
The resistors are realized in polysilicon, with standard or increased resistivity (obtained
by suitable dopant shielding) up to about 1 kW/ . The contact resistivity is about 200 W·mm in
both resistor models, with an average tolerance about 5%.
The inductor was implemented with two parallel octagonal spirals, featuring about 680
pH of total inductance. The turns are in aluminum (hence the Q is potentially less than in [11]
process) distributed in Metal2 and Metal3 layers, paralleled to reduce the series loss. A cubicle
of trenches is drawn in the substrate underneath the metal, to optimize the quality factor of the
inductor against the capacitive losses.
2.3 Phase noise analysis of the VCO TIBIA
2.3.1 Structure of the oscillator
The first VCO considered, TIBIA, exploited the traditional cross-coupled pair to
implement a negative resistor and compensate for the tank losses. The tank is realized by using a
2-turn, 2-paralleled-metals octagonal inductor, and 4 to 6 varactors connected in parallel.
1
This latter part of the work has also been supported by MURST (the Italian Ministry of University and Scientific
and Technological Research) and by CNR (the Italian National Research Council), in the national framework of
“Progetto Finalizzato MADESS II”. All the technical interactions and know-how exchange happened with the RF
Design Group of STMicroelectronics, Catania site, under the Contract 8030.16.AB .
24
Chapter 2
Measurements vs. predictions and Q-loading
2C
R s /2
L/2
IT AIL
Fig. 2-1 The principle schematic of differential cross-coupled TIBIA VCO.
Fig. 2-1 shows the TIBIA oscillator principle structure. It is a typical realization of the
VCO schematic sketched in Fig. 1-2. The topology is fully differential: the tank is symmetrical,
with varactor diodes employed to tune the oscillation (angular) frequency w0=1/ÖLC. The output
waveform is taken as the difference between the two collector voltage signals. The crossedcoupled bipolars implement the active element in positive feedback, giving Gt = +gm/2, where
gm is the transconductance of a single transistor.
By increasing the bias current ITAIL, the transconductance of the devices and therefore the
oscillation amplitude grow. To maximize the amplitude A0 usually the tail current is raised until
the stage is driven to operate in hard-switching regime; i.e., one transistor of the pair is
alternatively off, while the other one is biased with the full ITAIL, as discussed in Chapter 1. The
non-linear mechanism setting the oscillation amplitude is provided by the saturation of basecollector junctions of BJTs. Notice that the same effect happens in CMOS versions of this
circuit, and in that case is named de-saturation.
The QL value of the inductor estimated by ST at 3.6 GHz was about 8 (through device
probing, and HFSS electromagnetic simulation). Supposing to be in the rising zone of the quality
factor graph of the inductor (see for example [28]), scaling the Q with frequency (down to the
oscillation f0 = 2.5 GHz) would give a value of 5.6 . This is the unloaded quality factor, hence it
should not be adopted in order to figure out the tank behavior, once the L has been embedded
into the oscillator; anyway, it was the only number set available to us. The tank equivalent
capacitance was easily recognized to be 2.27 pF directly from the Cadence schematic; after these
data, the inductor on each branch of the tank (that was not indicated on the original circuit draft)
is calculated as L/2 = 890 pH. Once the quality factor is known, we can suppose to have a
lumped resistive parasitic of 2.5 W; finally, the loss conductance is g0t = 1/156 W-1.
All the VCOs studied were also provided with an Automatic Amplitude Control system
(AAC), schematically outlined in Fig. 2-2:
25
Chapter 2
Measurements vs. predictions and Q-loading
V
Vtune
Vref
V0
2
V0
2
Vext
Ipol
AMP
RE
Fig. 2-2 A more detailed representation of TIBIA, indicating also the AAC blocks.
The first stage of the AAC is a peak detector, sensing the differential voltage signal on the
collectors of the bipolar pair. The detected amplitude is compared with the reference voltage; the
regulation error is amplified, and the oscillating cell bias current is consequently tuned. This feedback
loop assures a safer start-up of the oscillator and a well-defined value for the oscillation
amplitude, independently of the process spread affecting the quality factor of the integrated
inductors.
2.3.2 SSCR prediction
The STSpice simulation of the complete VCO (oscillator cell and AAC) gives an
oscillation amplitude of only 130 mV, against the 400 mV needed to balance the subtractor stage
of the amplitude control, and have the feedback settled. Otherwise stated, despite the AAC is
pumping the maximum available current into the cell, this still does not suffice to enhance the
oscillation swing up to the equilibrium value. In Fig. 2-3 the differential stage acting as
subtractor and amplifier is shown, together with the peak detector output:
VREF
1.850V
+
2.028V
ratio
450 : 1
peak partition
0.70V
0.85V
117 mA
Fig. 2-3 Unbalancing on the AAC subtractor stage. Due to the low oscillation amplitude of the VCO,
the regulating loop is out of linear range (in “on” saturation, to increase the amplitude).
26
Chapter 2
Measurements vs. predictions and Q-loading
The stage worked in unbalanced condition. Let us figure out the theoretical prediction of
the SSCR for the cell analyzed, based upon the formulas derived in Chapter 1. The relation to
use is:
SSCRa =
kT w 0 1
1 + F C Q a2
A02
2
(2.1)
Where
A0
C
w0
Q
a
: 130 mV
: 2.27 pF
: 2p · 2.5 GHz
: 5.6
: angular frequency offset from the carrier, 2p · 100 kHz
The noise factor F has been evaluated in both the completely linear working assumption
of the transconductor, and the completely switched one. Only 130 mV of oscillation do not give,
in fact, a full current switch out of the negative resistor, and we will better provide a suitable
range of predictions rather than one number alone. Here are the results:
·fully linear case:
since
F = 1.607
æ
q
I ö
× P ÷
F = 2 × ç rbb ' × got +
2 kT 8 × got ø
è
where the parameters are
rbb’ = 34.1 W
g0t = 1/156 W-1
ITAIL = 1.5 mA
·fully non-linear case:
since
(2.2)
F = 0.430
F » 2 × rbb ' × got ×h +
SP
8kT × got
(2.3)
The folding coefficient h was taken about 0.75 at 130 mV driving signal. The unilateral
spectral density SiT of the current noise for the degenerated tail source was figured out with:
qI TAIL æ
I
2b ö
÷÷ + q TAIL × 4
× çç1 +
g m × RE ø
b
2b
è
where the circuit parameters showed the values below:
b = 70
gm = 60 mA/V
RE = 750 W (the degeneration resistor of the tail current source)
S iT =
(2.4)
With such a values, the prediction comes out between -87 dBc/Hz @ 100 kHz (linear
case) and -89 dBc/Hz at the same offset (non-linear one). Unfortunately, a direct measurement of
the oscillation amplitude could not be arranged at this stage, because the chip was part of a
complete transceiver on-board demonstrator, and the pin-out of the die was predetermined and
not modifiable on demand. The measurements complied with the prediction with only 2 dB of
27
Chapter 2
Measurements vs. predictions and Q-loading
deviation [29], maybe due to slight loading effects acting on the tank; nevertheless, the phase
noise performance was even worse than the former VCO of GIRAFE project.
The conclusion is, the AAC ought to be redesigned in order to set it effective. This out-ofequilibrium working state assures a regulation loop gain of about 0.02 (!), manifestly inadequate
even to avoid the AM-to-PM-induced carrier instability. As a matter of fact, the phase noise
measurements of TIBIA could be made only inserting the VCO within an external PLL loop
(NTB07, the documentation of the procedure is reported in [30]) because of the poor carrier
stability.
2.4 Phase noise analysis of the VCO STARMAN-CUT 1
2.4.1 SSCR prediction
The first TIBIA oscillator could be considered as a benchmark for the phase noise theory,
and was brilliantly passed. The second oscillator is much more complete, and this time the AAC
gain was risen by diminishing degeneration on the tail current source, and redesigning the gain
of the differential stage. The VCO core features base-collector C-R decoupling, to guarantee
enhanced swing headroom to the oscillation. This is labeled STARMAN-CUT 1, and is the first
circuit of the DAB project series. Since it was possible to perform tests and also customize the
board directly in our labs at Politecnico, a much more comprehensive analysis could be carried
out on this VCO.
The schematic of the new VCO cell is reported in Fig. 2-4 to allow for an examination as
comfortable as possible. The essentials of the schematic can be summarized with:
VCC
VEE
VTUNE
VB (simulated)
VBB (simulated)
=3V
= 0.62 V (BandGap Reference voltage bias)
=1V
= 0.951 V
= 1.770 V (internally generated voltage bias)
For sake of clarity, the picture can be partitioned in 4 blocks, indicated as follows:
28
Chapter 2
Measurements vs. predictions and Q-loading
VCO
Tank
TANK
VCC=3V
CPD
RAGC
VTUNE
CAGC
V1
VAGC
RPD
VRIF
0.6V
VPD
V2
CB
RB
CB
VB
RB
CE
RE IPOL
BGR=0.6V
AMPLIFICATORE
DI PICCO
AAC Subtractor
+ Amplifier RILEVATORE
AAC Peak detector
TRANSCONDUTTORE
VCO
Transconductor
Fig. 2-4 The STARMAN-CUT 1 in details, partitioned into 4 main functional blocks.
The reference voltage for the AAC is set internally to the chip; with such a circuit
settings, the simulation run to test the oscillation amplitude gave 774 mV. The voltage oscillation
taken at one collector and the current IC circulating in one transistor of the couple are jointly
depicted in Fig. 2-5:
Fig. 2-5 Excerpt from the simulations: Xelga shows the oscillation onto one collector, and the profile of
the current flowing into the corresponding transistor. The current behavior is pulsed, resembling in effect
a square wave.
29
Chapter 2
Measurements vs. predictions and Q-loading
Three BJTs constitute each branch of the transconductor differential couple. The average
value of the current waveform in one time interval can be easily computed by exploiting XelgaÒ
capabilities (the waveform visualization tool of Anacad suite [31]), to give:
Multiplied for the 6 bipolars, this value reaches a total ITAIL » 7 mA. For what concerns
the unloaded quality factor Q of the inductor, we get:
QL =
w0 × L / 2 2p × 2.7GHz × 680nH
=
= 7.69
RS / 2
1.5W
(2.5)
The SSCR estimation performed in TIBIA case can be iterated, by adopting the formula
(2.1) in which, this time:
A0 : 770 mV
C
: 2.55 pF (shunt connection of 4 ½ varactors, 1.08 pF each, in series with metal-tometal 12 pF, again paralleled by 1.5 pF parasitics on the collector node)
w0 : 2p · 2.7 GHz
QVCO : QL–limited (g0t » 1/177 W-1), has a value of 7.69
a
: 2p · 100 kHz
The noise factor computation is nearly identical to the preceding case, but now we must
take into account the noise contribution of the base biasing resistors: it is indeed conveyed
directly at the output through the decoupling capacitors, that near w0 are short circuits. The
transconductor stage works this time in hard commutation regime, hence F can be computed in
non-linear fashion only:
SP
F » 2 × rbb ' × g0 t ×h +
(2.6)
8kT × g 0t
The h factor is about 4.5 at A0 = 770 mV. The white spectral density SiT is given by:
qI æ
I
2b ö
2 kT 1
SP = P × ç1 +
×
÷ + q P ×4 + 2×
gm × Rc ø
RB 4
b è
2b
(2.7)
into which:
b = 70
gm = 280 mA/V
g0t = 1/177 W-1
RE = 50 W (tail source degeneration)
RB = 2 kW (the C-R crossed high-pass decoupling)
The noise term due to the decoupling base resistors is really negligible (2×10-24 A2/Hz
against 2×10-22 A2/Hz of the other addenda). Unlike in TIBIA VCO, in this case the terms adding
up to determine F are of the same order of magnitude, 0.87 for the spreading and 1.13 for the
white current noise. Moreover, this time the AAC is fully operating. Nevertheless the lowpass
shape of its noise, due to the dominant pole filtering performed within the loop, should impair
30
Chapter 2
Measurements vs. predictions and Q-loading
any phase noise worsening - according to what stated in Chapter 1. The final limit for SSCR is
then estimated to be -103.4 dBc/Hz @ 100 kHz.
Amazingly enough, the experimental data are instead –76 dBc/Hz @ 100 kHz for A0 =
770 mV, as can be seen in Fig. 2-9. The discrepancy is really enormous, and calls for an
extensive revision of the theory as it has been conceived up to now.
2.4.2 Deeper phase noise analysis - AAC turned off
At this point, both the noise and the PM noise transfer have been studied and
quantitatively assessed. We can put the results together and check the accordance with the
unexpectedly bad SSCR data measured on the test board, on the entire A0 range. Fortunately, on
a board of the chip STARMAN-CUT 1 properly modified to meet phase noise characterization
aims, as well as on the board of STARMAN-CUT 1.1 specifically designed, it was possible to
further extend the experimental data characterization. We can directly assess the SSCR
dependence on the tail noise when the oscillation amplitude A0 is varied, contemporarily turning
the AAC off.
The first chip CUT 1 was in fact opened, and the final stages of the AAC were made
directly presettable through an external wire; this is the so-called FIB processing, that entails the
ion-beam disruption of some metal tracks on the die, and a successive platinum sputtering to
reroute signals. The experimental setup arranged in our lab to perform the measurements is
sketched in Fig. 2-6:
L = 4.6 mH
C = 100 nF
V CC
C PD
R AG C
C AG C
V BE
V AG C
R PD
V PD
V RIF
I PO L
VE
RE
BGR
Fig. 2-6
Experimental set-up for controlling the tail current, and thus the oscillation amplitude, in
STARMAN-CUT 1. Notice the second-order filtering performed on the external voltage bias.
The command node is of course very sensitive to external noise, then the sweeping
generator was lowpass filtered by discrete-components LC blocks. Not only the amplitude could
be changed by driving the tail and interrupting the AAC control; but the noise of the differential
stage of the regulator was also cut off, by adding a 220 nF capacitor on the node made available
and thus reducing the loop bandwidth to 25 Hz. The AAC noise will affect the carrier stability up
to 25 Hz away from w0, after upconversion has taken place, and is no longer perceptible at 100
kHz.
31
Chapter 2
Measurements vs. predictions and Q-loading
With AAC off it is much easier to apply the non-linear theory outlined in Chapter 1 to the
white noise components that the final stages of the AAC inject into the tail. The rising folding
coefficient s may induce a SSCR vs. A0 dependence unexpected a priori. The two non-linear
factors that describe the folding of the thermal noise (h) and of the tail current white components
(s) have been customarily simulated for this stage, and are represented in Fig. 2-7.
4
3
2
1
0.0
a)
FFolding
a tto re dfactor
i fo ldinIgTAIL
d e lla c orre nte I p o l
Folding
rbb’ g d ella r bb'
F a ttofactor
re d i foldin
0.10
0.2
0.4
0.6
0 .8
1 .0
0.08
0.06
0.04
0.02
0.0
1 .2
0.2
b)
A m p iezza differenziale
]
Differential
Amplitude A[V
[V]
0
0.4
0.6
0.8
1.0
1.2
A m p ie z za dAmplitude
iffe re n zia leA [V[V]
]
Differential
0
Fig. 2-7 Folding factors relative to a) rbb’ and b) ITAIL, of the VCO STARMAN-CUT 1, as derived from the
STSpice simulation of the non-linear transfer of noise sources, with the tone injection technique.
The behavior of the curves shows nothing unexpected, however. In effect, the VCO
under test is very similar to the 1-GHz prototype simulated in the previous Chapter.
The main noise contributors concurring to the wideband SiT are outlined in Fig. 2-8:
VCC
RAGC
CAGC
IPOL
VAGC
VRIF
VPD
VBIAS
RE
BGR
Fig. 2-8 The main noise sources still affecting the tail current, after the insertion of the external bias
network depicted in Fig. 2-6.
The various noise sources that still affect the tail current can be summarized in the
formula:
S
I
1
S iT @ 4kT
+ 2q T + vAAC
(2.8)
RE
b
R E2
32
Chapter 2
Measurements vs. predictions and Q-loading
where SvAAC represents the white voltage noise joining the base of the current generator, and
coming from the last stages. Like the folding factors, this term has been calculated through
Matlab simulations at various biasing voltages driving the last follower: it turns out to dominate
the other two addenda. Since it keeps quite constant over a wide range of current tail biases, we
conclude that SiT also remains constant. After calculations have been carried out, it results that
the presence of additional noise from the amplitude regulator limits the performance to –95.4
dBc/Hz @ 100 kHz, at the new reference A0 chosen (400 mV).
2.4.3 The SSCR experimental data
As will be seen in the next Chapter 3, the white residual noise of the last stages is much
inferior to the one filtered out, for we expect noticeable phase noise improvement. The
measurements confirm this first feeling. Thanks to the driving capability afforded by the new
FIB-provided inlet of the circuit, a complete sweep of the bias current supplied to the VCO cell
has been performed, recording the phase noise performance of the STARMAN-CUT 1 at each
oscillation amplitude. The final data are represented in Fig. 2-9. The SSCR was read at the
spectrum analyzer, after a hard limiter stage has rejected the AM components. To collect as
much data as possible, the only “input” of the VCO, the supply voltage, was varied on the former
board without FIB – then with the AAC loop active. Passing from 3 V down to 2.5 V (available
swing, once subtracted the bandgap reference: 2.4 V and 1.9 V) the SSCR changed in surprising
way: -76 dBc/Hz @ 2.4 V, and -88 dBc/Hz @ 1.9V! The two experimental points available are
also marked on Fig. 2-9.
AAC on – 2.4 V
AAC off
AAC on – 1.9 V
(1+F)
effect
Tank
noise
Differential Amplitude A0 [V]
Fig. 2-9 The log-log plot reports all the measured SSCR data on STARMAN-CUT 1, as compared with
the theoretical expectations. The discrepancies are of both qualitative and quantitative kind, and
especially remarkable when the AAC loop is set active.
The refined estimation fails anyway to match the measurements (-95.4 dBc/Hz predicted
against –93 dBc/Hz after test). What is worse, the experimental SSCR is lower than before, but it
does not show a progressive improvement with rising amplitudes. It decreases until about 300
mV, featuring a minimum between 300 and 400 mV (here is the reason for taking a reference A0
to 400 mV), then it starts worsening again. This behavior could not be ascribed to any effect
taken into account by the traditional phase noise theories: Fig. 2-9 reports in fact the fitting curve
provided by using the theory developed in Chapter 1. The prediction is always descending and
33
Chapter 2
Measurements vs. predictions and Q-loading
drifts away from the measurements, then it is structurally incorrect. Only the region of the graph
at intermediate amplitudes is accurately fitted by the theoretical calculations.
2.5 Accordance of the phase noise theory with SpectreRF
The result found by applying the non-linear phase noise theory to the oscillator, was
successfully compared with the prediction furnished by a widespread tool for VCO analysis:
Cadence SpectreRFÒ. This is software based upon the periodical steady-state algorithm [32,33],
capable of automatically taking into account any non-linearities of the network. Fig. 2-10
illustrates the data obtained by simulating STARMAN-CUT 1 with such a tool. The real amplitude
set to about 400 mV is recovered by the preliminary single-period analysis of the stable
oscillation (Fig. 2-10a). Then the composition of noise sources plotted versus the offset
frequency from the carrier gives the phase noise in Fig. 2-10b. The slope is almost precisely the–
40 dB/dec typical of phase noise (without flicker issues), and –95.3 dBc/Hz @ 100 kHz are
obtained that precisely match the theoretical estimate.
-2
a)
b)
Fig. 2-10 Results of the SpectreRF run performed on the CUT 1. The oscillation amplitude a) and the
SSCR prediction b) are in fair agreement with STSpice results and theoretical analysis, respectively.
After the matching with this high-end simulation countercheck has been performed, the
SSCR discrepancy observed could be no longer ascribed to any non-linearities of the system.
2.6 Phase noise analysis of the VCO STARMAN-CUT 1.1
The STARMAN-CUT 1.1 chip differs from the CUT 1 version only for minor adjustments in
the values of the passive components of the tank, and peak detector resize. As for the CUT 1
34
Chapter 2
Measurements vs. predictions and Q-loading
circuit, in this case too the SiT noise density keeps constant (at about 50 pA/ÖHz) when the bias
current is varied. In Fig. 2-11 we show the current noise terms transferred on the tank through
PM
the theoretical folding coefficients, found in Fig. 2-7 above (labeled S iTNK
in (2.9)). The curve
indicating sSiT is indeed overwhelming the other contributions, thus the AAC is demonstrated to
be a critical block in the overall phase noise accounting.
2 /H z]
Current
on the
tank
/Hz]
R u m o renoise
d i co rren
te su
l ta n[Ak 2[A
4 E -2 2
TOTAL
TOTALE
3 E -2 2
S nIp o l
2 E -2 2
r b b'
1 E -2 2
goT
0E +0
0 .0
0 .2
0.4
0 .6
0.8
1 .0
A m p ie zza Amplitude
d i o scilla zio
Differential
An0 e[V][V ]
Fig. 2-11 Discrimination of the different contributions towards the total current noise on the tank.
Now it is possible to estimate the global SSCR(a). The data in figure are already referred
to the tank, then the current is to be multiplied for the closed-loop impedance ZTNK(a) of the tank
and divided for the carrier power. For LC parallel tanks ZTNK(a) is classically given by 1/(2aC)
(see Eq. (1.3)), and eventually:
PM
SiTNK
w0 + a SSCR a =
2a C 2
=
2
0
A 2
1 kT w 0 1
1 + F A02 C Q a 2
(2.9)
-80
S S C R @ 1 0 0 kH z [d B c /H z ]
-84
-88
-92
-96
-100
0.1
2
3
4
5
6
7 8 9 1.0
A m p ie z z a Amplitude
d i o s c illa z ioA
n e [V]
[V ]
Differential
0
Fig. 2.12 The theoretical phase noise prevision curve in the case of STARMAN-CUT 1.1 VCO.
35
Chapter 2
Measurements vs. predictions and Q-loading
The phase noise at 100 kHz offset is plotted in Fig. 2.12, versus the oscillation amplitude.
The power law that fits the curve is:
SSCR a µ A0-1.6
(2.10)
slightly worse than the classical A0-2 behavior; this is precisely due to the non-linear folding
action.
2.7 Discrepancy with measurements and need for an extended theory
The SSCR performance estimated above reads –100 dBc/Hz @ 100 kHz at 1.1 V.
Unfortunately, this is already not suitable to meeting the specifications of the cellular wireless
standards, and when compared with the actual experimental measurements it turns out to be even
optimistic. The additional effects met in the CUT 1 still stand out in Fig. 2-13, where the phase
noise data relative to STARMAN-CUT 1.1 are shown:
-70
S S C R @ 1 00 kH z [d B c/H z]
-75
-80
-85
-90
-95
-100
0.1
2
3
4
5
6
7
8
9 1.0
A m pie zza dAmplitude
i osc illazion
[V ]
Differential
A0e [V]
Fig. 2-13 Also for the STARMAN-CUT 1.1 test chip the qualitative difference between the measurements
and the non-linear prediction is confirmed.
The data are not very different from the ones pertaining to STARMAN-CUT 1, that are
reported in Fig. 2-14 for further comparison. The extent up to which the theory fits the data is
always excellent in the descending region of the plot, while the successive ramping is unforeseen
and almost identical in the two cases.
36
Chapter 2
Measurements vs. predictions and Q-loading
(1+F)
effect
Tank
noise
Negus, ISSCC ‘97
Craninckx, ISSCC ‘97
0.1
0.2
0.3 0.4
0.6 0.8 1
Differential Amplitude A0 [V]
Fig. 2-14 Substantial agreement between the theory and the phase noise performance observed in other
standalone oscillators published. The blue triangle indicates the response given by SpectreRF.
Since the SSCR regrowth was also observed in similar cross-coupled topologies of MOS
VCOs embedded in complete communication systems, the phenomenon we are dealing with is
technology-independent. As observed before (blue triangle in Fig. 2-14), software packages such
as SpectreRF do not predict it [34]2, thus it cannot derive by additive noise or non-linear noise
folding. It may instead be due to the oscillator carrier’s instabilities forced by externally coupled
noise, and not modeled in the software. The two points displayed in the right bottom corner of
Fig. 2-14 are relative to [6] and [8], and instead lie very close to the noise prediction of
STARMAN, that is topologically similar to them. The major difference between these oscillators
and ours is the circumstance that they were both standalone, whereas STARMAN is embedded in a
complete front-end. This enforces the suspicion about an external (maybe, from substrate) noise
coupling, to be addressed in Chapter 4.
The option of a sensitivity effect surges when the KAM-PM is considered. In fact, the
striking characteristic of the coefficient is its steep rise with the carrier amplitude. The SSCR
formula (2.9), when completed with the additional noise conversion term:
AM
1 kT w 0 1 + F K AM - PM × S viTNK (a )
SSCR a = 2
+
2
A0 C Q a 2
A0 / 2
2
(2.11)
could be completely revolutionized: the strong dependence of KAM-PM on A0 can overstrike the
phase noise decrease found in (2.9), and instead make the SSCR growing for increasing
amplitudes. In Chapter 4 the sensitivity issues will be examined in depth, and the CUT 1.1 curve
depicted in Fig. 2-13 will be fitted with suitable precision.
2
This very valuable information was given us by Prof. A. Abidi, of UCLA, during a meeting held in Pavia (Italy) on
September 29th, 1998. He was in fact involved in phase noise analysis of full-CMOS auto-limiting VCOs, in the
framework of his Group’s activity of complete transceivers development. I wish gratefully thank him for his
exquisite gentleness and personal encouragement.
37
Chapter 2
Measurements vs. predictions and Q-loading
2.8 Decomposition of the overall Q of the VCO
The flaw affecting previous analyses is the use of the unloaded Q in order to figure out
the phase noise. As in microwave resonant cavity theory, also for LC tanks it is important to
realize that it is the loaded quality factor that establishes the real spectral purity characteristics of
the resonator, once it has been coupled to the external world (to build filters, or implement an
oscillator loop, or only for measurement purposes). In our case, we have a parallel LC tank that
suffers from the losses of:
1.
2.
3.
4.
the transconductor, whose non-ideality from the loading standpoint are seldom treated
in technical literature
the varactor
the inductor
the external stages, such as the peak detector of the AAC and the followers that read the
oscillation and deliver the signal on the output limiter-buffer.
Each loss effect can be modeled through a shunt resistor, adding a power dissipating path
for the reactively oscillating current (i.e., the energy stored in the tank). The general formula for
the composition of Qs is isomorphic to the simple conductance combination:
QVCO =
1
=
1
åQ
j
j
1
æ 1
1
1 ö
çQ + Q + Q
÷
VAR
TRANS . ø
è L
(2.12)
The different quality factors, linked to the single devices, can be isolated with ad-hoc
simulations. If a perfect switching behavior is assumed, the amplitude A0, the bias current ITAIL
and the quality factor Q are linked by:
w0 × C
ì
Q
=
ï
g0t
ï
í
ï g 0 t = g meff = 2 × I TAIL
ïî
p A0
hard - switching Þ Q=
w0 × C × p × A0
2 × I TAIL
(2.13)
We may wonder if the quality factor found through this technique is also the Q that is to
be substituted in the SSCR (2.11) formula, to quantify the amount of thermal noise. Since it
comes out from g0t, which in turn is given by an energy balance condition, the answer is
affirmative. In fact, the electro-magnetic energy losses can be either thermal or radiative; at our
frequencies, only the first mechanism can be reasonably active; but thermally-dissipative
mechanisms are also noisy, then are surely taken into account by the subsequent resistive-based
Q assessment methods. The entire question could be more easily approached from the tank
selectivity point of view: this vision is perhaps more subtle, but also better physically-based [35].
Next simulations have been made with constant ITAIL = 7 mA, and at the new f0 = 2.7
GHz; from the A0 values, the Q can be promptly inferred.
38
Chapter 2
Measurements vs. predictions and Q-loading
2.8.1 Q set by the transconductor
The oscillating core of the VCO, without AAC and output buffer, was simulated. The L
and C of the tank were set ideal, as well as the tail current generator; moreover, the bipolar
transistor bases were biased at a very low voltage, so as to prevent their saturation even at huge
oscillation swings. The result is:
A0 = 22.49 V to give QVCO = QTRANS = 153
This QTRANS represents the intrinsic losses of the differential couple, such as the base leakage. As
expected it is fairly high, but the adoption of a real tail generator and the saturation effects make
it rapidly worsen: the only saturation phenomena bring QTRANS down to 25.
2.8.2 Q set by the varactors
The same cell has been simulated, but with real varactors. The final oscillation features:
A0 = 7.56 V
then QVCO = 51.5
and thus QVAR > 50
The Q reduction due to the leakage of the cell also plays a role in the QVCO, but it is
marginal with respect to the losses in the junctions. Moreover, the achievement is supported by
two other investigations on the varactor.
· The first one consisted of a simple device analysis. The varactor was embedded within the
tank, as illustrated in Fig. 2-15:
TUNE
Fig. 2-15 Stimulus and voltage probing of the tank, left standalone, for the varactor Q analysis.
By recording the time transient of the voltage across the diode, and the current flowing in
it, straightforward phase displacement calculations can be carried out. By adopting forcing
sinusoids of 50 mV amplitude, and sweeping the DC reverse bias, we obtained:
VVARACTOR
0V
1.425 V
2.850 V
R// equivalent
2136 W
4384 W
6614 W
C// equivalent
1.08 pF
0.77 pF
0.63 pF
Q = w0RC
36.7
53.0
65.6
39
Chapter 2
Measurements vs. predictions and Q-loading
Also FFT I-V phase analysis is suitable for the purpose, but this is much more lengthy
procedure. The simulation performed above concerned diodes biased near -1 V, hence the
QVAR value is confirmed in full.
· The second technique considers the tank as a black box. The only assumption regards the
tank as second-order system; it is studied through its impulse response, like traditionally
done in system theory. The poles of the block are given by:
Im
poli H ( s) =
1
w
s 2 + 0 s + w 20
Q
(2.14)
- w0
- w0
2Q
Re
Fig. 2-16 Pole placement in the s-plane.
and depicted in the complex Argand-Gauss plane in Fig. 2-16. The inverse Laplace
transform gives the time expression for the impulse response h(t):
F » 2 × rbb ' × got ×
N
SP
+
2 8kT × got
(2.15)
Voltage across varactor [V]
The initial impulse can be suitably replaced by charging the inductor with the magnetic
flux F0×d(t), where F0 = L×I0 . The time constant of the exponential decay gives the sought
Q. Given the non-linear nature of the varactor, the losses (and thus the Q) change during
the damped transient; but we can fit the envelope of the decay at the desired amplitudes, to
get at least the order of magnitude of the parameter. The simulated h(t) is sketched in Fig.
2-17:
Time [ns]
Fig. 2-17
Damped oscillation transient issued on the tank for the assessment of the varactor Q by
means of the envelope slope analysis.
The green exponential fit was optimized in the proximity of A0 = 2 V; the envelope there
can be described by the decay:
40
Chapter 2
Measurements vs. predictions and Q-loading
t ö
æ
h (t ) » 3.3 × exp ç ÷
è 4.8ns ø
(2.16)
hence Re(p1,p2) = 1/tdecay = w0 /(2×Q)= 208.3 Mrad/sec, and finally it is:
QVARACTOR =
w 0t
= 40.7
2
(2.17)
The result is in substantial agreement with the previous estimations. It is confirmed that the
quality factor obtained by the STSpice model (labeled DV) is slightly superior to the ones
recently published in technical literature, that usually do not exceed 30 ([36]).
2.8.3 Q set by the inductor
This kind of loss is taken into account only through the series resistor RL in our models.
The parasitic element is used to model the ohmic drop in the metal (Metal2 and Metal3
connected in parallel by two via arrays at the extremes) as well as the energy dissipation in the
substrate. In fact, its value will be easily derived from the tank seen “from the outside”, i.e.
complete of all the Joule-fashion mechanisms that make the inductance lossy [35]. The two
spiral turns are laid out in octagonal topology, and respecting the rules suggested by [8] for the
hollow structures. However, some snapshots and a deeper technical discussion will be provided
during our layout definition, later in Chapter 7.
Unfortunately, neither 1- or 2-port scattering coefficients, nor scalable models for the
inductor [9] were set available from ST, hence we had to resort to simple parasitic networks such
as RS, using first-approximation parameters. All the simulations will be affected by this pitfall,
from the accuracy standpoint. Despite this, the aim of the Thesis was more a circuit approach to
phase noise than a device one, thus the scientific usefulness of the work will not be hindered.
The simulation of the VCO completed with the RL = 1.44 W gives
A0 = 953 mV,
or QVCO = 6.5 and then
QL > 7 (versus the known 7.7)
2.8.4 Q set by external loads
The external loads (follower, peak detector) were not added to the VCO. Since these
blocks will be always present in the next SSCR measurements, and the theory will give
predictions in fair agreement with the experimental data, the effect of these loads is deemed to be
irrelevant for the oscillator. The stages were carefully designed to avoid further tank loading, in
effect.
In conclusion, the fair agreement between theory and measurements in the descending
portion of the curve in Figs. 2-13 and 2-14 indicates that QL is the limiting term, and the SSCR
estimations done so far used the correct parameter. But the SSCR achieved is still not suitable for
wireless applications such as GSM. What is more, the experimental data measured on the board
is -76 dBc/Hz @ 2.4 V at high amplitudes, totally different from the theoretical estimation. This
region of the plot has been studied from the quality factor standpoint.
41
Chapter 2
Measurements vs. predictions and Q-loading
2.9 Amplitude-dependent Q-loading due to the transconductor
Let us now examine the active transconductor. As a first step the cell may be derived
from one of the three basic transistor schemes: Colpitts, Hartley, LC tuned-collector [37]. These
single-transistor topologies may be transformed into differential stages, in order to achieve larger
oscillation amplitudes, exploit the beneficial properties of the symmetrical layout and routing,
and suitably drive the many differential blocks fed by the synthesizer (i.e. image rejection
mixers). It is to be remarked however that any fully differential structure, when working in hard
switching regime, loses its potentially high rejection to supply noise.
The single-ended to differential translation may be accomplished by joining a cell with its
mirrored replica, and placing resistors between the supply voltages and the nodes lying on the
symmetry axis. These nodes are balanced with respect to a differential oscillation and the
resistors do not affect the differential dynamics of the system, whereas they prevent any common
mode oscillation (see Chapter 6). As an alternative, inherently differential stages may be
adopted. STARMAN is one of them; another solution resorts to transformers to decouple the
branches and tailor the loop gain [38]; all-capacitive voltage partition has also been tried [39].
Fig. 2-18 shows a solution in which the voltage shift is obtained by the base-emitter voltage of a
follower [6]; in this case the maximum A0 can reach about 1.2 V with VDD = 2.4 V.
VTUNE
VDD
IP
Fig. 2-18 Cross-coupled oscillator based on the emitter follower decoupling technique [6].
The point discussed here concerns the loading effect of these transconductor cells on the
Q factor of the VCO. This effect has seldom been considered; on the contrary, cell losses must
keep apace with technological improvement of the integrated tank, not to become in turn the
main shortcoming.
In the differential stages so far discussed, there is a parasitic current which flows into the
bases, which is inversely proportional to the impedance seen through them. This contribution can
be modeled with conductive and susceptive parts (GB+j·BB) in parallel to the negative
conductance: exactly like g0t, GB also can be responsible for QVCO degradation. At the oscillation
frequency this impedance is not so high as one may expect, and this statement also holds for
MOS stages. In fact, at the oscillation frequency the capacitors bypass the active devices (BJT or
MOS) and the resistances connected to the emitter of these elements load the tank. This effect is
much similar to what happens in a simple emitter - or source - follower.
42
Chapter 2
Measurements vs. predictions and Q-loading
VDD
RC
ZIN
ZIN(0)
W
fb
RE
RC// RE
Fig. 2-19 Input impedance of the simple emitter follower. The resistive part of the complex impedance
begins falling at fb,, which usually lies well below the RF oscillation frequency fosc.
Fig. 2-19 sketches the frequency dependence of the input impedance of a follower with a
resistor RC on the collector. The first pole of the impedance lies near fb = fT/>; for the MOS
transistor this value is zero, where the impedance ZIN is infinite. At high frequencies all the
capacitors are shorted and the impedance reduces to the parallel of RE and RC. In silicon
integrated VCOs it always happens that
fT/b < fosc < fT
(2.18)
(generally fosc is up to 3.6 GHz whereas fT is around 20 GHz), therefore the base impedance at fosc
is still falling, and a non negligible parasitic current is drawn from the bases. At low and high
frequencies the impedance is only resistive: then, for sake of continuity, not only impedance, but
also resistance (or, the inverse of loss) must be monotonically falling. The stage in Fig. 2-18 is a
benchmark of this behavior: when studied with the losses analysis we are going to propose for
STARMAN, it surprisingly leads to conclude that the followers does not improve the quality factor
of the transconductor, since the stages are bypassed through the Cp of the transistor.
The quantitative evaluation of the load effect of the oscillator cell is not easy, because the
stage is switching, and the equivalent resistance on the emitter of the two transistors (RE) is
periodically varying. Referring to the STARMAN VCO circuit:
- when the oscillation on the tank reaches a peak, one bipolar is on and the other off; thus the
emitter of the former sees its Early resistance r0 in parallel with the Early resistance of the
tail; the base eventually shunts this value with the RB depicted in Fig. 2-20a;
- when the oscillation is at the zero-crossing , the stage is in balanced state and each emitter
sees gm-1 in the other device (Fig. 2-20b).
43
Chapter 2
Measurements vs. predictions and Q-loading
1/gm
r0
RB
RB
IP
a)
IP
b)
Fig. 2-20 The two capital instants of the oscillation: peak a), with high transconductor input resistance,
and zero-crossing b) were the stage features the least input resistance. The dotted parts of the schematic
indicate “not active” devices or lines.
Moreover, at the oscillation frequency, the reactive part of the tank is resonated out and
the impedance load on each collector reduces to about RC=1/(2×g0t).
2.10 Q-loading evaluation by harmonic decomposition
The STARMAN-CUT 1.1 has been simulated with Eldo. Fig. 2-22a shows the differential
oscillation voltage when ITAIL = 10 mA, and the total parasitic current (difference of the base
currents) of the transconductor. The base currents are heavily non-harmonic because of the large
driving signal amplitude. Since the frequency is very high a large amount of the current is
reactive component due to Cp and Cm, and the dominant component in quadrature to the voltage
oscillation proves it. Since we are looking for a parasitic contribution given by an equivalent
resistive element, we have extracted only the component in phase with the driving signal.
Unfortunately we are not dealing with sinusoidal waves. Thus, we must:
- decompose the current waveform in series of harmonics at multiples of fosc
- find the component of every harmonic which is in phase with the driving voltage carrier
- reconstruct the “in-phase” parasitic current by superimposing all the contributions
previously found.
Strictly speaking, of course a sinusoid at 3×f0 could not be defined “in phase” nor “in
quadrature” with a carrier at f0; nevertheless, the phase difference can be derived taking the
nearest zero-crossings. To first order, the method pursued above shares some principles with the
harmonic balance techniques [40]. An example of application of the procedure is provided in
Fig. 2-21; + indicates a lead and - a lag of the parasitic IB with respect to the VIN.
44
Chapter 2
Measurements vs. predictions and Q-loading
IB vs.VIN
phase shift
Dj
+78.25°
+37.83°
+12.79°
-30.77°
-63.52°
-95.45°
Harmonic
under test
w0
3×w0
5×w0
7×w0
9×w0
11×w0
Dt
IB peak magnitude
[mA]
6.6649
1.5229
1.2804
0.9445
0.6334
0.3947
Time [s]
Fig. 2-21 Delay evaluation with the spectral decomposition technique. The sinusoid in thick solid line
is the first harmonic of the current wave dotted over it, and driven by the voltage drawn in thin solid line.
a)
b)
40
30
50 0
20
250
10
0
0
-2 5 0
-1 0
-5 00
-2 0
-7 5 0
-3 0
-1 0 00
-4 0
0.6
0.7
0 .8
0 .9
1 .0
1.1
1 .2
1 .3
1 .4
Total parasitic current [mA]
Oscillation voltage [mV]
750
4
In-phase parasitic current [mA]
1 00 0
3
2
1
0
-1
-2
-3
-4
0 .6
0 .7
0 .8
0 .9
1 .0
1 .1
1 .2
1 .3
1 .4
T im e [n s ]
T im e [n s ]
Fig. 2-22 Quadrature-dominant behavior of the parasitic current entering the transconductor, a);
extraction of the current component in-phase with the forcing voltage sinusoid, b).
Fig. 2-22b shows the extracted “in phase” current. Note the difference between the
vertical scales for the two currents: the impressive current flows drawn from the bases in Fig. 222a were almost completely in quadrature with the voltage, thus they were circulating mainly
into the capacitances and do not appear in Fig. 2-22b. From the ratio between the voltage carrier
and the corresponding parasitic current we compute the time-dependent values of the parasitic
resistance RIN. From Fig. 2-23 we can check, up to what extent the numerical results are close to
the theoretical predictions: with VEARLY = 50 V (i.e., r0 = 5 kW) and RB = 2 kW, the maxima of the
curve should all be:
RB // r0 = 2 kW // 5 kW = 1.4 kW
(2.19)
45
Measurements vs. predictions and Q-loading
Re(Zin) over time [Ohm]
Chapter 2
Time [ns]
Fig. 2-23
Reconstruction in the time domain of the parasitic resistance seen into the transconductor
base. The dips occur synchronously with the zero-crossings of the oscillation wave. For the Q evaluation
purposes, the average resistance should be considered.
In the figure, the sudden steps at the dips of the curve are caused by the zero-over-zero
condition given by the zero crossings of the driving voltage; the residual phase shifts still
affecting the current are responsible for a little distortion. Since the quality factor Q is a
parameter depending on the average behavior of the system, the QTRANS of the cell should be
computed by taking the time average value of RIN. For the case proposed we get <RIN> = 714 W,
and thus QTRANS = w0RINC = 30.5 . This value threatens worsening the overall performance of the
VCO, which is even sensitive to little variations of the quality factor. This implies that, striving
to enhance the quality factors of the passive components of the tank, is of little worth if the
transconductor stage shows such a losses; at high oscillation amplitudes, for instance.
Fig. 2-24 shows the variation of the QTRANS factor of the active cell with the bias current.
It should be remarked that as ITAIL is increased to attain larger A0 values, high injection effects
like b and Early resistance degradation reduce the total impedance seen into the base (see Fig. 219) and the rise in Cp further degrades the fT. Similar considerations also apply to single-ended
stages, as well as to CMOS transconductors. To give a rough idea of the technology we will be
using, the fT of a C2 bipolar reaches 20 GHz at 0.4 mA collector current, to descend towards 10
when the current is reduced to 0.11 mA, or risen to 3.5 mA.
Q du e to cell parasitic R in
34
32
30
28
26
24
0
Fig. 2-24
2
4
6
10 12
8
T ail current Ip [m A ]
14
16
The simulated quality factor degradation (Q-loading) at high biasing currents of the cell.
Fast inspection of this effect can be obtained by resorting to harmonic balance simulation methods.
46
Chapter 2
Measurements vs. predictions and Q-loading
In conclusion, the influence of the loading effects on the Q cannot quantitatively account
for the unsatisfactory SSCR obtained on the STARMAN-CUT 1. More in-depth analysis is needed
for example on AM-to-PM conversion issues, which will be studied next.
2.11 Q extraction from ITAIL ® A0 measurements
The tail tuning capability allows for the investigation of the real Q of the VCO. The most
immediate way to link electrical variables to the quality factor is by exploiting the equation
(2.13) given above. From simple collection of A0 vs. ITAIL data, the slope of the dependence is
derived, that is proportional to the Q. The measurement sweep on ITAIL was done, and parallel
Eldo simulations were performed, as reported in Fig. 2-25.
1 .2
AMPLITUDE
S IM U LAZIO N I
amEstimated
piezza stim ata
Oscillation
A 0n[V]
A m p ie zzaamplitude
d i o scilla zio
e [V ]
1 .0
Real
am piezza
effettiva
Q»7
0 .8
0 .6
Q » 10
0 .4
0 .2
0 .0
0
2
4
6
8
10
Tail
C o rre
n tebias
d i pcurrent
o la rizzaITAIL
zio[mA]
n e [m A ]
Fig. 2-25 A0 vs. ITAIL curves measured on the Cut 1.1 . From a starting slope that is signature of Q =
10, once at 6 mA the plot bends, indicating the gradual reduction of the Q down to about 7. The
experimental data were faithfully reproduced by simulation, hence the equivalent parasitic parameters
have been precisely extracted.
The correct slope of the experimental curve was reproduced by setting Q = 10 for the
inductor in the circuit schematic. At high amplitudes the curve tends to bend, thus Q is degraded
and becomes about 7; according to the transconductor loading analysis presented in Paragraph
2.10 this effect is no longer a surprise. The corrections for the VBE variability of the peak
detector, which impacts directly on the accuracy of the oscillation amplitude reading, were
performed by a further specific run of simulations.
47
Chapter 3
Investigation on AM-to-PM conversion effects
Chapter 3
Investigation on
AM-to-PM conversion effects
Other potential phase noise contributors are investigated here. The low frequency noise
coming from the AAC and the noise due to an internal BGR voltage reference, that both inject
into the tail of the VCO, are first quantified. Since these noise sources could in principle
contribute to AM noise only, the AM-to-PM conversion due to static varactor non-linearities is
inspected by means of behavioral and schematic simulation. Dynamic effects of the varactor
working are achieved through device-level simulation (Dessis). The amplitude → phase
conversion leads in effect the SSCR to increase with A0,, even if not to the quantitative extent
suitable to explain the experimental data.
3.1 Contributors to the tail current noise
3.1.1 AAC noise injection
T
he unexplained experimental data on STARMAN VCOs triggered the analysis of
the noise transfers in the AAC, which finally led to the redesign of the servocircuit. The VCO cell alone cannot benefit from a 2.4 → 1.9 V swing decrease at
A0 of 600-700 mV; but the noise that the AAC injects in it is different in the two conditions:
• at 1.9 V, the simulations tell that AAC is always turned off. The base of the follower
driving the tail is stuck at 1.9 V, pulled-up by the 30 kΩ resistor of the inactive differential
stage. The noise injected in the tail by this final part of the circuitry is constant, and the
current noise probed at the tail output is about 1.5 nA/√Hz
• at 2.4 V the AAC is working, and its state varies with time. When the oscillation on one
collector is at peak, the detector’s rectifier is on and charges the capacitance. The
differential stage is a little more closed and the peak detector less noisy: the Eldo
simulation gives
S iT − AAC = 6.3 nA/√Hz
(3.1)
The noise contributed by the last stages was then < 25% of the total noise of the
regulation system. The main noise source of the discharge current generator in the rectifier is the
48
Chapter 3
Investigation on AM-to-PM conversion effects
one of the 3 kΩ degeneration resistor, seeing a 9 kΩ shift resistor in shunt with the differential
stage (see Fig. 3-2 for a simplified sketch of the original peak detector):
4kT
4 KT
2
⋅ R SHIFT
=
⋅ 9kΩ = 20 nV/√Hz
R DEG
3kΩ
(3.2)
Once reported to the tail current via the transfer evaluated by AC simulations, it accounts for 4.1
nA/√Hz. For comparison, the upper 9 kΩ voltage shift resistor gives a noise term of about 2.3
nA/√Hz: this completes the investigation of the noise source partition.
Tail noise IDEAL BIAS
Tail noise REAL BIAS
Frequency
Fig. 3-1 Spectral density of the current noise on the STARMAN-CUT 1 VCO tail, when the peak detector
is kept “on” by the input waveform. Also the noise of the bias network is assessed, by substituting for it
with a noiseless voltage source.
The noise rolls off after the dominant pole of the loop, set to 1/(2π⋅30kΩ⋅10pF) ≈ 530
kHz. The lower red curve is the output noise when the bias network is supposed to be clean: the
noise becomes 4.5 nA/√Hz, or 28% less. Then it seems that the common mode noise rejection of
the AAC can be improved, provided the design of the differential stage is re-balanced.
The problem occurs when the oscillation is near the zero-crossing. The current source of
the peak detector finds the rectifier open, then injects all of its noise towards the pursuing
differential, that amplifies it a lot. By using schematic “tricks” also this condition can be
simulated. The rectifier must be turned off, but the differential ought to be balanced in the steady
condition. The .IC or .NODESET options of Eldo cannot be exploited, as they converge to a
stable status of the network but with the current generator off! A huge choker (1 TH,
necessitating convergence parameter tailoring) was instead used to bias the differential stage,
while leaving the noise transfers in the network unperturbed (Fig. 3-2a).
49
Chapter 3
Investigation on AM-to-PM conversion effects
b)
a)
Tail noise IDEAL BIAS
Tail noise REAL BIAS
S1
5 pF
S2
9 KΩ
Peak
CHOKE
V
static
Bias
3 KΩ
Frequency
Fig. 3-2 Current noise assessment on the VCO tail, b), when the input waveform drives the rectifier
“off”. The correct biasing of the ensuing differential stage is assured by the choker placed as in a).
The noise is now as high as 117 nA/√Hz (Fig. 3-2b). The pole has diminished to C⋅2rπ ≈
290 kHz (C = 5 pF, and rπ = 109 kΩ if the differential is balanced). The VCO designer cannot be
unaware of this noise switching mechanism, for both SSCR estimation and circuit improvement.
Chapter 5 will be entirely devoted to the theoretical, simulative and experimental analysis of this
time-varying AAC noise topic.
Up to now, we need only to know the effect that such a low-frequency noise affecting the
tail can cause on the tank.
3.1.2 BGR noise injection
The test board STARMAN-CUT 1.1 permits the direct measurement of the electrical
characteristics of the tail on one of the three VCOs integrated on the chip. The schematic of the
tail configuration available on the test specimen is depicted in Fig. 3-3.
VCO
50.9 Ω
BGR
0.1 Ω
VN
Fig. 3-3 External resistors connection on the tail of one of the test VCOs.
50
Chapter 3
Investigation on AM-to-PM conversion effects
The external SMD resistor acts as “hardware switch”, capable of joining or keeping
separate the two emitter paths of the VCO. The 50.9 Ω resistor, in turn, can be fed by the main
ground connection of the system (labeled VN), or by the internal-generated reference voltage
coming from the BGR (VREF2 on the corresponding board, see Chapter 8). The BandGap
Reference is a voltage reference synthesizer particularly stable with respect to temperature and
supply voltage variations; it was included in the circuit in order to stabilize the voltage swing
with respect to these environmental variations, commonly met during the operation of a cellular
terminal. Measurements and simulations performed on the voltage regulator give an output of
0.62 V. When the phase noise assessment with BGR connected will be executed in Chapter 4, we
will remember that the dynamic swing of the transconductor is reduced of 0.62 V (from 3 V
down to ≈2.4 V) and, consequently, that the A0 versus ITAIL relation results more compressed.
This implies modifications on the slope of the SSCR plotted against the bias current itself.
One may wonder if, being the AAC still connected to BGR voltage while the tail gets
attached to ground in the tests, it can continue to inject noise in the current generator. A
simulation was made to be sure that this does not happen: a sinusoidal tone was injected over the
VRpll (lower rail), but keeping the 51 Ω resistor connected to ground. The current response of
the tail, in Fig. 3-4, clearly indicates that the AAC does not hinder the quality of the noise
analysis.
VRpll
V_bias
I_tail
Time
Fig. 3-4 Results of the simulated injection of a probing tone on the ground rail.
The upper waveform is the 10 mV, 100 kHz voltage tone superposed over the 0.62 V of
the BGR. In the middle is represented the voltage probed at the biasing network, which issues
the driving voltage across the emitter-degenerated current sources of the AAC: there is virtually
no rejection of the tone there. The currents in the legs of the AAC are set by the difference of
these two voltages, that almost precisely track each other; the final follower with the transistor
B12 is then fueled by a clean current, and the BGR noise is rejected on the tail of the differential
stage of the feedback circuit. The output driving voltage is affected by only 100 µV of sinusoidal
51
Chapter 3
Investigation on AM-to-PM conversion effects
perturbation, that finally impose only 2 µA of ripple on the tail current. The rejection factor (a
sort of PSRR) rail voltage → tail current is therefore about 5000, or 74 dB!
3.1.2.1 Output driving capability of the BGR
Modeling the BGR and its driving stage as done in [41], i.e. studying the network of Fig.
3-5, an eyeball estimation of the output impedance of the bandgap can be made.
VP
7.2 kΩ
R2
CINT
7.2 kΩ
R1
VR
BIAS
PWR
CEST
Fig. 3-5 Simplified scheme of the output stage of the BandGap voltage Reference available inside the
STARMAN test chip.
To lower the impedance, the output is taken onto a node of the loop. We can take into
account the action of the feedback on the “cool” resistance of the circuit, by dividing it for the
loop gain. With closed loop it is:
ROUT o.l . = 7.2 kΩ ⋅ 2 = 14.4 kΩ
(3.3)
(the opamp shows high impedance on the + electrode; and the r0 of the compound output bipolar
can be neglected, since it has high current driving capacity and does not suffer saturation). The
open-loop resistance is therefore quite high, but the loop gain can be evaluated by opening the
feedback on the + input of the opamp (it is really a differential couple with single-stage trailing
amplifier, typical configuration for the embedded service circuitry). From simulations we obtain:
− G loop = 7586 ≈ 77.6 dB
(3.4)
and eventually the closed-loop output impedance is figured out:
ROUT c.l . =
Rout o.l .
1 − G loop
≈
14.4 kΩ
= 1.8 Ω
7586
(3.5)
This first check of the circuit can be supported by a simple AC run: the voltage regulator
output has been excited with AC current stimulus, leaving in this way the feedback fully
operating, and the corresponding voltage response has been saved. The result of the subsequent
division gives Fig. 3-6, where the impedance on the vertical axis is to be read directly in ohms
and not in decibels.
52
Chapter 3
Investigation on AM-to-PM conversion effects
Frequency
Fig. 3-6 Frequency behavior of the magnitude of the output impedance featured by the BGR.
The negative feedback keeps the ROUT c.l. at 1.7 Ω up to the loop bandwidth limit, beyond 100
kHz.
3.1.2.2 Output voltage noise of the reference
The noise of the BGR is now to be determined. Although it is a voltage reference and
features then very low output impedance, the stage has been filtered by an external 100 nF SMD
capacitor on the board: of course, this lowpass pole will not assure an effective filtering.
The noise simulation is particularly easy for this autonomous circuit; only the output
voltage noise shall be investigated, and the result is depicted in Fig. 3-7:
Frequency
Fig. 3-7 Lowpass-shaped noise spectral power diagram as simulated at the output of the BGR.
The noise pole is to be sought at 1/√2 times the maximum in the linear plot proposed: on
the vertical axis the square root of the noise spectral density is quoted (i.e., the rms value in 1 Hz
bandwidth). The pole lies around 700 kHz. The noise at DC reaches 124 nV/√Hz, and - despite
the internal 10 pF capacitance - at 100 kHz it is still unabated. The external 100 nF ceramic
capacitor creates a pole at 1/(2πROUT c.l.Cext) ≈ 880 kHz, that again is not effective for our 100
kHz interference reduction purposes. Notice that the external capacitor could also be considered
part of the loop, reducing the loop bandwidth and causing a premature rise in the output
53
Chapter 3
Investigation on AM-to-PM conversion effects
impedance (after only 100 Hz); but, also its value will be divided by the effect of the loop, and
the pole will be substantially kept unchanged.
Eventually, beyond the R-C filter the rms noise density accounts for 122 nV/√Hz. This is
a very large amount of interference that can potentially spoil both the amplitude and phase noise
performance of the oscillator. By a suitable low-noise, high-input impedance instrumentation
amplifier (whose realization steps are documented in Appendix A) we are now capable to
experimentally confirm these expectations. Thanks to the discrete-components amplifier,
fabricated basing on biomedical instrumentation techniques, we can easily determine the noise
between the VN and VREF2 electrodes of the board. The AC coupling of the two probes of the
circuit prevent the saturation of the input stage (even if its two internal feedback loops would
react against the steady component, canceling it out). The noise anyway passes unchanged, since
the single-ended input impedance is 50 MΩ and the capacitance adopted is 67 nF-coaxial, to
give about 47 mHz for the first high-pass pole. At the spectrum analyzer, the noise appears as
illustrated in Fig. 3-8:
Fig. 3-8 Snapshot of the voltage noise coming from by the BGR, as seen on the spectrum analyzer. The
needed buffering was provided by the low-noise amplifier whose realization is described in Appendix A.
The value confirms the simulation results. The analyzer, already set in noise
measurement mode, senses -90.9 dBm/Hz @ 100 kHz, or 0.82 pW/Hz; when referred to a 50 Ω
reference load this accounts for 6.39 µV/√Hz. The pre-amplifier gain is about 50 (refer to
Appendix A, at Fig. A-6) thus the noise level is eventually measured to be 127 nV/√Hz.
The slight descent in the spectrum is in agreement with the simulations. The series of
peaks - equally spaced at 16 kHz - that come out of the noise floor in the snapshot is due to the
switching power supply used. When the BGR is detached and the noise affecting ground line
(with respect to the supply rail, VP) is characterized, in fact, the peaks steadily emerge above the
noise baseline and reach the same level as in Fig. 3-8. In the next Chapter 4 this noise will be fed
to the conversion coefficient KTAIL, evaluated in a consistent technique, in order to predict the
experimental phase noise data available on the board STARMAN-CUT 1.1 .
3.2 Behavioral static estimation of AM-to-PM conversion
From the previous measurements the importance of AAC noise has emerged. Amazingly
enough, the theory outlined in Chapter 1 rules out the low frequency noise contributions from the
jeopardy list of the phase noise performance: the noise, once upconverted around ω0 by the
switching transconductor, should be only AM in nature. The only phenomenon left, actually
54
Chapter 3
Investigation on AM-to-PM conversion effects
capable to explain the tail influence on the SSCR, seems to be the AM-to-PM conversion on the
tank; it is here thoroughly addressed.
As sketched in Chapter 1, the amplitude perturbation on the tank is capable of inducing
frequency perturbations, owing to the rectifying effects inherent to the non-linear C-V link of the
varactors - and of the collector-substrate parasitic capacitances[26]. The entity of this conversion
process can be quantified by means of the adimensional coefficient KAM-PM; it was defined as the
sensitivity of the effective capacitance Ceff to the amplitude A0, amplified by the closed loop
transfer of the tank (acting like a frequency → output phase parameter, in the proximity of the
LC resonance). The (1.33) is rewritten below for our convenience:
K AM − PM =
ω0 ∂ Ceff A0
⋅
⋅
2α Q ∂ A0 Ceff
(3.6)
Unlike the original ω0(A0) dependence, the function Ceff(A0) can be estimated by issuing a
behavioral simulation that entails only the varactor characteristic; or more precisely, only the
capacitive part of the tank. From the HSB2 technology specification [42] the Spice-like varactor
model, DV, gives:
m = 0.41
φbi = 0.9 V
respectively for root parameter of the junction and the built-in voltage; whereas the collectrosubstrate parasitics found in the transistor C6 model feature:
m = 0.33
φbi = 0.82 V
The parasitic junction is therefore gradual (whose theoretical coefficient is a cubic root,
or m = 0.33) whereas the varactors tend more to the abrupt junction (i.e., m = 0.5). Given the
tank topology, the forward+reverse characteristic of the half-tank capacitive arrangement is
plotted in Fig. 3-9. The amount of parasitics has been derived knowing that:
ω0 =
1
=
LCeff
1
L ( ( CV // CS ) + C parasitics )
VC C
(3.7)
VC C
Half-tank
TU N E
680 pH
6 pF
6 pF
6 pF
4.5 1 pF
5kΩ
Capacitance [F]
680 pH
6 pF
4.5 1 pF
5 kΩ
Vtune [V]
a)
b)
Fig. 3-9 The C-V static characteristic, b), of the whole semi-tank, a), as obtained by Matlab.
55
Chapter 3
Investigation on AM-to-PM conversion effects
The varactors preserve their reverse biasing thanks to the 5 kΩ pull-down resistors; the
collector-substrate elements experience instead the rail-to-rail swing since they are tied to the
inductor on the cathode. The 12 pF CS in series to the varactors cause a linearization of the tank
characteristic, at the cost of reduced tunability of the central frequency.
In Matlab environment, we have defined the C-V characteristic of the variable
capacitance by adopting the classical formula:
CV (t ) =
CJ 0
CS
A
ö
æ
⋅ 0 cos(ω 0 t ) ÷
ç VTUNE −
C S + CV (t ) 2
ç1 +
÷
ç
÷
φ built in
ç
÷
è
ø
m
(3.8)
Instantaneous capacitance [F]
Then the composition of capacitances was made. The voltage term senses the
instantaneous oscillation across the junction, and therefore does not take into account dynamical
effects, that will be addressed by means of device-level simulations later in this Chapter.
Moreover, the varactor capacitance is a function of the voltage across it... that in turn depends on
the partition of the oscillation between the MIM capacitor CS and the varactor itself! The circular
reference leads to an implicit equation, which was solved by iterating the numerical estimation of
the formula (3.8) until a self-consistent value was found. The convergence condition was fixed
by requiring that the varactor capacitance values from two successive iterations differ less than
0.1%. The first guess was the varactor value estimated one step before. The problem is a wellbehaved one, and the convergence is nearly immediate. The synoptic time plots of the half-tank
capacitances are reported in Fig. 3-10:
Time [s]
Fig. 3-10 The sequence C(t) of capacitance values taken on by the semi-tank of the VCO vs. time, when
stimulated by sinusoids of increasing amplitudes (+50 mV voltage step).
The oscillation amplitude voltage increase is 50 mV between every step. The remarkable
peaking of the diagrams indicate that the average values, adopted to find the Ceff establishing the
oscillation frequency, will be ever rising. The strong capacitive increase registered when
approaching the temporary forward bias makes the rise more than linear. Employing the simple
56
Chapter 3
Investigation on AM-to-PM conversion effects
average of the instantaneous C(t) to get Ceff is a rather naive estimation method, but indeed it
rapidly provides a first order idea of the AM-to-PM conversion behavior. The collection of
behaviorally simulated data is presented in Fig. 3-11, where the capacitance differentiation
directly gives KAM-PM. The logarithmic version of the right plot in Fig. 3-11 permits to recognize
a quadratic ramp of the coefficient:
(3.9)
KAM-PM @ 100 kHz
Oscillation Frequency f0 [GHz]
KAM-PM ∝ A02
Oscillation Amplitude A0 [V]
Oscillation Amplitude A0 [V]
Fig. 3-11 Matlab extraction of the average frequency f0 vs. amplitude A0, and related values of the
KAM-PM conversion coefficient.
3.3 Corrections due to PLL feedback
The presence of the PLL, which was kept locked during the measurements in order to
avoid frequency instabilities, shifts a bit the viewpoint of the previous analysis but does not
affect the final result. Instead of differentiating the Ceff locus with constant VTUNE, we ought to
keep ω0 constant (and hence the Ceff) varying VTUNE. The change imparted to VTUNE to counter the
variation of Ceff can be anyway seen as a counter-variation of the same Ceff, thus the terms of the
argument do not vary. As a further proof, we tried to:
1. numerically derive the comprehensive 2-variable function:
Ceff = Ceff(VTUNE , A0)
after the non-linear formulas (3.8) written above. The surface was figured out by a run of
Matlab on the matrix of the variables
2. intersect the surface with the constant Ceff plane. This operation reproduces the PLL action,
giving a univocal A0 ↔ VTUNE curve onto which the phase lock forces the VCO to stay.
Operating on this curve is like writing
VTUNE = VTUNE (A0)
57
Chapter 3
Investigation on AM-to-PM conversion effects
3. For each set of three (VTUNE(A0),A0,Ceff), that is now function of A0 only, we can determine
the corresponding KAM-PM according to the usual expression (3.6).
In the present case, with f0 = 2.67 GHz we find for the half tank Ceff = 5.23 pF. The
results of the crosscheck estimation are illustrated in Fig. 3-12; the implicit locus given by the
intersection of the surfaces in Fig. 3-12a has been processed to give the conversion coefficient in
Fig. 3-12b.
30
0.72
K A M-P M @ 10 0 k Hz
C eff capacitance A 0 [V]
25
0.60
20
0.48
15
0.36
10
0.24
5
0.12
Tuning V tune [V]
00
00
Amplitude A0 [V]
0.5
0.5
1.0
1
Oscillation Amplitude A 0 [V]
a)
b)
Fig. 3-12 3-D locus of the Ceff set by different oscillation amplitudes and tuning voltages, with the PLL
constraint plane, a). KAM-PM inferred from the Ceff vs. A0 link, b).
The KAM-PM with the PLL constraint is very close to the previous one. The order of
magnitude of the discrepancies lies largely within the numerical errors.
3.4 Estimation by electrical tank simulation
The results obtained by the static behavior procedure can be corroborated by a more
complete circuit schematic analysis. Once the angular frequency ω0 is extracted by Eldo when
the amplitude A0 is changed (e.g. by driving the tail), from the definition (Chapter 1)
ω0 =
1
L ⋅ C eff
=
1
L ⋅ CVAR
(3.10)
the Ceff can be backtracked. Remind that, when the non-linear reactance is periodically driven by
the carrier V0(t)=A0cos(ω0t) and a CVAR(t) curve is generated, the time average of the reactance
<CVAR(t)> = Ceff is only a heuristic estimate of the true capacitance in one period. The method
gives anyway a first idea of the impact of the phenomenon on the phase noise. Clearly, if other
effects exist that lead to a frequency modulation when the amplitude is changed, they will be
58
Chapter 3
Investigation on AM-to-PM conversion effects
altogether confused in the method. Hence the simulations were performed on the tank alone,
made lossless through purpose model modifications (the RVAR parameter modeling the varactor
series loss [41] was forced to zero) and stimulated by the initial condition on the inductor. Fig. 313a illustrates the schematic issued for simulation (tuning voltage VTUNE = 1 V), after which the
Ceff and finally the KAM-PM were extracted:
60
IL(0)
50
CS
CV
KKAM-PM
@100kHz
100 kHz
V0 @
L
CP
V
a)
40
30
20
10
Fig. 3-13 a) Schematic of the semi-tank issued for
circuit simulation, and b) the KAM-PM, curve, in
substantial agreement with the plots of the
parameter previously obtained.
0
0.0
b)
0.2
0.4
0.6
0.8
1.0
1.2
1.4
Oscillation Amplitude [V]
The eventual coefficient can be interpolated again by a power law with exponent very
close to 2. Such a slope can be compatible with the rise in SSCR that triggered all this analysis;
unfortunately, as will be seen in the next Chapter, the final amount of noise due to AM-to-PM
conversion lies about 40 dB lower than the experimental level.
Up to now, we have reported the first attempts to justify the experimental results by
means of a mere extension of the theory discussed in Chapter 1. The KAM-PM coefficient can be
instead seen as one particular case of a more general sensitivity approach, based on the direct
and indirect stability concepts [37]. The proof of this was given already during the derivation of
Eq. (1.33) in Chapter 1, when the KAM-PM was derived by an intuitive amplitude → frequency
sensitivity approach. A more systematic treatment will be proposed in Chapter 4.
3.5 Varactor dynamics implications on AM-to-PM conversion
The KAM-PM derivation is indeed qualitatively well based, and confirmed by the Eldo
simulations. The missing link is the quantitative agreement between the KAM-PM predictions due
to the varactor non-linearity, and the coefficient as derived by starting from the phase noise
curve. The former in fact shows values increasing with A0, but is still much inferior with respect
to the experimental evidence.
One of the possible reasons that can lead to the discrepant values found for the KAM-PM
coefficient is the non-linearity evaluation method. In particular, the analysis carried out in
Paragraphs 3.2 to 3.4 makes use of the static modeling of the junction; here instead we try to
understand if the dynamic effects that the high oscillation frequency entails, can be responsible
for unexpectedly strong conversion of the noise. Some carrier transport mechanisms could in fact
have been neglected in the conventional lumped model, while they are surely encompassed by
59
Chapter 3
Investigation on AM-to-PM conversion effects
device-level simulations. By this analysis, we look for an effective varactor capacitance Ceff with
distorted dynamic behavior. In such a case, after the definition of Eq. (3.6) the resulting
conversion coefficient would maybe result superior, and explain the measurements; or, it can
remain at the values estimated up to now, or even inferior, and be definitely ruled out. The
interest for this kind of investigations is testified by the recent publication of similar analyses on
integrated active devices, especially for microwave circuits ([43], and [44], for GaAs varactors in
the specific case).
3.6 Planar structure of the junction
The starting point for the device-level analysis of the varactor is naturally the knowledge
of its planar structure. Our information is not complete from this viewpoint. We must start from:
1. the varactor layout, as obtained in the technology library of the design kit DK_HSB2P30
2. the knowledge of the characteristics of the collector-base junction of the bipolar transistors
made with the aforementioned technology. A qualitative idea of the vertical section of the
junction has been derived from [45]; the real dimensions will be reconstructed after some
probe simulations.
The layout of the varactor is constituted as represented in Fig. 3-14:
Section
Sezione
Section
Sezione
Fig. 3-14 Layout of the varactor in HSB2 technology. The external crown of electrodes connects the
cathode, whereas the vertical crossing lines are anode electrodes.
The internal series of contacts, held within the dark red areas, is the anode terminal; the
vertical metals connect to the shallow diffusion of the n base, through the yellow apertures in the
oxyde. The internal square diffusion of boron defines the active area of the device; in fact, the
cathode is realized with a larger diffusion of phosphorous underneath, which surrounds the
anode and allows contacting the external crown of electrodes. The dashed lateral areas of the
60
Chapter 3
Investigation on AM-to-PM conversion effects
structure indicate the physical perimeter of the sinker implant, that is the outlet of the cathode.
The contacts share the same color because the superficial layer is polysilicon in both cases. The
horizontal Metal2 lines in blue are the cathode connections; the anode is indicated in red Metal1,
vertically routed on the component.
Once the surface topology is known, it is relatively easy to recover the planar structure of
the junction. Moreover, the device in Fig. 3-14 is symmetrical: hence we will simulate only one
half (or, one quarter) of the whole varactor in order to determine its behavior.
3.7 “Reverse engineering” of the planar varactor
The device-level simulator adopted for this study is Dessis [46] by ISE-TCAD AG. The
algorithm employed for the carrier density solution is of drift-diffusion kind, in fact:
1. it breaks up the volume of the device according to the Delaunay triangulation algorithm;
where the contour and the underlying doped zones are not critical it switches to a
rectangles representation, to save simulation time and memory. We actually did not exploit
the 3-D capabilities of the software, but resorted to the planar, 2-D simulation which is
computationally more efficient
2. it addresses the conduction problem by solving Poisson equations and continuity equations,
expressed in sampled terms within the polygons defined during the previous step. The
unknowns are the quasi-Fermi potential, the intrinsic potential, and the current densities; a
system is then issued, and the simulator seeks the solution for the various φ potentials. The
first trial is “decoupled”, i.e. the problems are solved iteratively in separate fashion (plugin cut). Only when an acceptable approximation for the solution has been found, one
unique non-linear system is issued (coupled cut) and solved via Newton-type techniques.
The problem complexity raises steeply with the increasing density of polygons within the
area to be simulated; the symmetry exploitation is greatly beneficial from the computational
efficiency standpoint.
3.7.1 Materials and geometry of the varactor
The first tool of the Dessis suite that is to be used is MDraw, to draw the profile of the
integrated device. Both the geometry and the technological processes can be defined by means of
this program. From the layout, the physical dimensions - in microns - have been inferred, and are
now reproduced on the vertical map in Fig. 3-15 (view VARACTOR.BND, describing the
boundaries of the object).
61
Chapter 3
Investigation on AM-to-PM conversion effects
Top
half
N_1
P_1
Right
half
Substrate
Fig. 3-15
The geometric arrangement and material composition of the varactor planar structure, as
issued in MDraw of the TCAD Dessis suite.
This half-right varactor comprises three anode electrodes, the external cathode and the
lateral trench isolation. There are totally 14 regions of different materials:
1. 4 of silicon di-oxyde, dark brown in the image; the trench and the separation of the anode
from the cathode sinker are among these ones
2. 4 aluminum metals, in light brown; the inferior width of the contact is as measured on the
layout, whereas the upper enlargement only mimics the real one
3. 1 generic silicon bulk (pink zone), into which the doping will be performed
4. 2 p+-doped polysilicon areas, that indicate the purple areas shown in Fig. 3-14; after
having experienced convergence problems, and since they represent simply ohmic contacts
metal and silicon, they have been finally neglected
5. 3 electrodes of the element (in bright red): P_1, or the anode, common to the three central
contacts; N_1, the outer cathode, outside the first SiO2 isolation; and the Substrate contact,
that covers the whole bottom of the silicon to permit the reverse biasing of the bulk.
3.7.2 Static DC-AC tests
The doping location is readily available from both reference [45] and a general
knowledge of bipolar processes. The densities of the dopant and the depth reached by donors and
acceptors have been instead tailored via a lengthy trimming phase; the correct behavior of the
varactor had to be mimicked at least “as it appears outside”. After [42] in fact we have:
1. reverse current, to define the breakdown voltage
IBV/Area = 10 µA (BV = -22.5 V)
2. forward current, when a conventional forward bias is imposed to the diode:
IS|Vj=0.9V /Area = 35 aA · exp(+0.9V/25mV)
3. single-varactor capacitance with 0 V biasing applied:
CJ0 = 1.08 pF
In all of the following the substrate has been tied to ground, as it happens in the real wafer.
For “reverse-engineering” purposes, the curves of the current obtained from Eldo can be
directly compared with their Dessis-simulated counterparts. Defining a series of operating points
62
Chapter 3
Investigation on AM-to-PM conversion effects
the reverse voltage sweep can be performed, for each of which the device equations will be
solved. Dessis also allows embedding the device in a simple lumped-element circuit; then the 2.5
Ω contact resistance can be promptly inserted in the simulated setup, with the only attention to
not including its terminals among the nodes to be solved. The lumped components are defined
exactly in Spice-like style.
After a lot of trials, highlighting the capital importance of the surface boron doping from
both peak and diffusion depth standpoints, the matching between the results derived from
schematic- and device-level modeling became acceptable. In effect:
Forward current in the anode [A]
Forward current in the anode [A]
1. in forward biasing, reaching VD as high as 0.9 V we get current curves such as the ones in
Fig. 3-16 (left a)- Eldo results, right b)- Dessis output):
a)
Forward Bias VD [V]
b)
Forward Bias VD [V]
Fig. 3-16 I-V static forward characteristic of the varactor diode, as retrieved by a) the circuit simulator
and b) the device-level solver.
2. in reverse biasing we had to impose VD = -23 V. It is worth reminding that the devicesolving routines must take into account much more physical effects in the reverse zone
than in the direct one. In particular, the dominant contribution to the current is given by the
avalanche effect (since VINV > 5 V); in the setup of the simulation, VARACTORDC.IN, the
following commands have been issued:
…
EffectiveIntrinsicDensity (NoFermi NoBandgapNarrowing)
Mobility
(
DopingDependence
HighFieldSaturation
CarrierCarrierScattering
)
First the carrier mobility has been made dependent on the local doping (impurity
scattering effects). The carrier speed saturation (near 107 cm/s) at high electric fields has
been specified; and even the inter-carrier interactions have been “turned on”, since the high
doping levels could enable effects otherwise quite unlikely, such as Auger recombination.
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Chapter 3
Investigation on AM-to-PM conversion effects
These three model options are used to better describe the behavior of the particles that
ignite the avalanches. Moreover:
…
Recombination
(
SRH (DopingDependence)
Auger
Band2Band(E1_5)
eAvalanche (vanOverstraeten Eparallel)
hAvalanche (vanOverstraeten Eparallel)
)
Reverse current from the anode [A]
Reverse current from the anode [A]
where the SHR (Shockley-Hall-Read) and the mentioned Auger recombination are set
dependent on the doping. The intensity factor of the band-to-band tunneling takes into
account the Zener-effect term of the reverse current. The avalanche effect for electrons and
holes is modeled following the Van Overstraeten theory1. The reverse breakdown plots are
illustrated in Fig. 3-17, from which we observe that the real current increase occurs at 22.5 V, also found with the Eldo model:
Reverse Bias VREV [V]
a)
Reverse Bias VREV [V]
b)
Fig. 3-17 I-V static reverse characteristic of the varactor diode, as retrieved by a) the circuit simulator
and b) the device-level solver.
3. A sequence of AC simulations at 1 kHz probe frequency allowed tailoring the doping;
eventually, at zero bias, the capacitance of the varactor was 1.0825 pF, i.e. the value of Cj0
as reported in the official reference [42]. Of course an area factor, given by the ratio
between the total area of the electrodes on the real layout and the contact area as specified
by MDraw must be defined; this factor is to be applied to all the electrical variables
depending on the surface extension (e.g. current, capacitance). In our case, the final set
was:
1
The author wishes to acknowledge Dr. A. S. Spinelli for having acted as consultant for numerous issues, pertaining
to the physics of devices. Many simulation parameters have been set appropriately thanks to his precious hints.
64
Chapter 3
Investigation on AM-to-PM conversion effects
…
Electrode
{
{ name="P_1" voltage=0.0 AreaFactor=78}
{ name="N_1" voltage=0.0 AreaFactor=142}
{ name="Substrate" voltage=0.0 AreaFactor=123}
}
3.7.3 Doping profiles after reconstruction
In the file VARACTOR.CMD of the commands given to the program to issue the doping
profiles, we imposed:
• a constant doping profile for substrate_P (boron - 1e16 cm-3) to define the initial condition
of the bare silicon wafer
• a Gaussian doping for n-, the phosphorous region of the N-collector that defines the
junction with P-base region; the concentration reaches 1.6e17 cm-3 at the peak while the
substrate neutralization, at 1e16 cm-3 density, occurs at about 9 µm (the structure is very
deep)
• the P-zone of the base, said boron-p+, is realized with an erf-function (i.e. with surface
deposition) of 1e19 cm-3, rapidly crumbling at 1e17 cm-3 at 1 µm of depth
• for what concerns the anode contacts, a Gaussian profile of n+ buried is adopted; the peak
is at 7.4 µm depth and 1e20 cm-3 height, quite strong, to enhance the conductivity as much
as possible
• the n+ sinker is Gaussian again, with a peak of 1e20 cm-3 and diffusion length of 3.4 µm, to
safely join the buried layer
• erf profile for EndTrench_P, the small boron zone (1e18 cm-3) that prevents false
triggering at the bottom of the lateral trench.
The implementation of the process sequence above leads to create a final doping such as
the one in Fig. 3-18a:
a)
65
Chapter 3
Investigation on AM-to-PM conversion effects
b)
Fig. 3-18 a) Map of the dopant concentration regions issued in the vertical varactor, and b) zoom on
the metallurgical boron-phosphorus junction.
The map has been obtained during the simulations by means of Picasso, the graphical
visualization tool of the Dessis suite. From the blue p-doped zones of the anode we pass to the
light red of the intrinsic cathode, to join the bright red of the phosphorous n-diffusions in the
buried layer and the sinker. The wafer substrate is cyan again, hence p-doped. The arrows in the
figure mark the points at which some technological steps have been executed; the meshes given
by triangulation are also depicted. A zoom on the mesh, greatly encroached at the anode
junction, is offered by Fig. 3-18b.
In Fig. 3-19 the doping concentrations are instead described with Cartesian plots, for
verification purposes. In Fig. 3-19a the net dopant concentration, in atoms per cm3, is drawn. For
the reader’s convenience, Fig. 3-19b reports the absolute doping concentrations: near the anode
we notice the prevalence of the shallow boron diffusion, in black, and the typical Gaussian red
profile of collector phosphorous (moderate doping) before the typical profile of the heavily
doped buried layer. After the buried layer, the black substrate with constant doping is visible.
a)
b)
Net concentration [at/cm 3]
Dopant concentration [at/cm 3 ]
Silicon depth [µ
µ m]
Silicon depth [µ
µ m]
Fig. 3-19
Logarithmic plots of a) the net dopant concentration and b) the separate p and n
concentrations encountered along a significant vertical section of the diode.
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Chapter 3
Investigation on AM-to-PM conversion effects
3.8 Oscillation-driven carrier motion within the junction
Once the static simulations have been performed, and the behavior of the planar varactor
matches the original model, it can be determined if - and to what extent - dynamical effects of its
working can increase the conversion coefficient AM→PM. The main difficulty that threatens our
analysis is the consistence of the bandwidth of the device as modeled before. After [42] a transit
time of the carriers of about 60 ps is found; from charge storage considerations (i.e. the formula
τtr = Cdiff⋅gm-1) we derive that our structure is much slower than the real junction, which probably
features smaller depletion layer. The following tests will provide the ultimate response about the
dynamic corrections to be applied to the analysis so far carried out.
3.8.1 Low frequency: f0 = 1 Hz
The first test exercised on the varactor consists of a forcing sinusoidal waveform between
the electrodes, of amplitude 0.66 V and 1 Hz of frequency; we still are in the quasi-static
domain. The varactor is operated in reverse DC biasing, -0.55 V; in effect, we are now interested
in the evaluation of the capacitive link between voltage and current (leading the voltage of 90°).
Every sinusoid period was checked in 4 instants, namely:
•
•
•
•
the rising zero crossing
the positive peak
the falling zero crossing
the negative peak
With the input stimulus varying so slowly, the varactor capacitance will reproduce the
static characteristics met during the Eldo investigation. The interesting internal displacement of
the charge carriers is available from the simulator, and the main charge configurations
recognized in this case will be identified in more critical, because faster, conditions.
The principal parameters suitable for describing the concentration of carriers within the
device are the quasi-Fermi potentials, for electrons and holes. Once said φi the intrinsic potential
level, it can be written [47]:
q (φ p −φ i )
ì
ï p = ni ⋅ e kT
í
q (φ n −φ i )
−
ï
kT
n
=
n
⋅
e
i
î
(3.11)
The drift and diffusion current densities are readily determined from the quasi-Fermi φn
and φp potential profiles; moreover, the map of potentials is clearer than the corresponding
charged particles distribution, then the first representation will be preferred in the next 2-D
graphs. The potential φquasi-Fermi at the electrodes is forced by the outside input signal, then its
evolution can be neatly tracked within the waveform period: in the figures representing voltages,
the sequence +0.66 → 0 → -0.66 → 0 is generated onto the anode terminal. The simulator
permits to save the physical configuration of the junction at the desired instants of its evolution,
thus obtaining a sort of “movie” of the carrier in 4 photograms successively presented:
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Chapter 3
Investigation on AM-to-PM conversion effects
1. positive-slope zero crossing:
Fig. 3-20 Quasi-Fermi potential for the electrons, φn, at half the rising front of the driving wave.
Fig. 3-20 shows the φn electrons potential profile, that after the legend is understood to
vary between 0 and -0.59 V. The sections of the potentials, relative to both holes and
electrons, can be found from Fig. 3-22b on. The vertical logarithmic scale allows recognizing
the exponential decays of the carrier concentrations, taken on a section of silicon starting at
the second metal contact of the anode in the figure above.
The line of the quasi-Fermi potentials must be paid attention. From the chromatic map of
Fig. 3-20 we observe a blue color at the surface of the device, hence a negative value for the
voltage (about -0.5 V); after the metallurgical junction the colors vary in the red spectrum,
from +0.052 V towards 0 V - in fact, the cathode is tied to ground. For the electrons, the
function must change its sign; the same happens for the holes, as can be deduced from Fig. 321.
To complete the scenario of the first simulated status, in Fig. 3-21 we report the φp
mapping equivalent to the φn one represented in Fig. 3-20.
Fig. 3-21 Quasi-Fermi potential for the holes, φp, at half the rising front of the driving wave.
The potential profile is again definitely separated between the anode zone (low values,
hence holes accumulation) and the cathode one, into which a remarkable extension of the
gradient into the “collector-like” area occurs. Once the buried+sinker regions have been
reached, the doping concentration is so high that negligible bending of the bands suffices to
ensure the current flow: the color tends therefore to become uniform there (blue zones).
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Chapter 3
Investigation on AM-to-PM conversion effects
2. sinusoid positive peak:
The plots are quite different from the previous ones; they have been collected in Fig. 3-22.
a)
c)
b)
Quasi-Fermi potentials [V]
Silicon depth [µ
µ m]
Carrier density [cm -3]
Silicon depth [µ
µ m]
d)
Fig. 3-22 Complete description of the carrier status into the varactor at the positive peak of the driving
waveform: a) φn, b) imrefs n and p into an inner section, c) electrons and holes concentrations, and d) φp.
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Chapter 3
Investigation on AM-to-PM conversion effects
The electron current flow is stronger than before; in fact, this time the sign inversion on
the φn is almost unappreciable, and the left border of Fig. 3-22b shows the typical steep
profile of the short-junction diodes (the equilibrium is reached only at the metal contact). Fig.
3-22c depicts a carrier density of “forward bias” type for the diode, which features an
exponential tapering between the carrier level in the various zones. The abrupt irregularities
after the buried layer can be probably ascribed to the mesh widening instanced there, in order
to speed up the simulations. The steep ramp of the function φn at the electrodes leads to a
uniform graph for Fig. 3-22a, by concentrating the variations only at the surface; Fig. 3-22d
depicts instead a holes potential φp still tapering towards to internal zones of the varactor.
3. negative-slope zero-crossing:
This bias condition of the device mimics the first one proposed, at Point 1, given the zero
potentials at the electrodes; it is the carrier “inertia” that makes the difference. In the first case
the diode came out of a strong inversion condition, whereas now the carriers are to be
removed from the regions into which they spread, as minority particles. The situation is
summarized in Fig. 3-23:
a)
b)
c)
Quasi-Fermi potentials [V]
Carrier density [cm -3]
Silicon depth [µ
µ m]
Silicon depth [µ
µ m]
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Chapter 3
Investigation on AM-to-PM conversion effects
d)
Fig. 3-23 Complete description of the carrier status into the varactor at half the falling front of the
driving waveform: a) φn, b) imrefs n and p into an inner section, c) electrons and holes concentrations,
and d) φp.
The electrons are no longer swept away from the terminals (compare Fig. 3-23c with the
analogous Fig. 3-22c), and the holes are still far from completing their removal from the
cathode (even if their potential, Fig. 3-23b, has already changed in the p++ surface diffusion).
We cannot see yet any indication of incipient inversion in the junction, but the flat descent of
the hole density usually precedes the slope change of the density peak, towards the junction
depletion and the current inversion. These phenomena will take place near the p-n domain
interface, at 1 µm depth from the surface.
4. sinusoid negative peak:
The plots referred to this particular condition of the varactor diode have been collected
together in Fig. 3-24:
a)
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Chapter 3
Investigation on AM-to-PM conversion effects
c)
b)
Quasi-Fermi potentials [V]
Silicon depth [µ
µ m]
Carrier density [cm -3]
Silicon depth [µ
µ m]
d)
Fig. 3-24 Complete description of the carrier status into the varactor at the negative peak of the driving
waveform: a) φn, b) imrefs n and p into an inner section, c) electrons and holes concentrations, and d) φp.
The definite abatement of the electrons in the p++ zone follows the strong decrease in φn,
indicated by the intense blue tonality of Fig. 3-24a, and by the relative curves in Fig. 3-24b/c.
The holes are being pulled at the surface shallow junction: the slope of φn has been markedly
reverted (the cyan circles in Figs. 3-24b/c highlight this circumstance). Finally, in Fig. 3-24d we
can observe that the peak of φp, in bright red, tends again to displace towards the inner regions of
the semiconductor; the sequence of the maps of Figs. 3-21, 3-22d, 3-23d and 3-24d recompose
the wavy behavior of the hole concentration inside the varactor.
A snapshot of another paramount parameter of the device concludes the “movie” of the
varactor evolution: the electric field. In Fig. 3-25 the electric field configuration at 0 V biasing is
reported, near the diode junction. The only other electric field peak is located near the n++ buried
layer - π substrate; given the quite high doping levels adopted to achieve high capacitance values
per unity area, the depleted regions into which the field becomes strong (i.e., the potential
undergoes steeper slopes) are very narrow. In the other zones, the current density is transported
without necessitating high electric field, relying only on the great number of carriers.
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Chapter 3
Investigation on AM-to-PM conversion effects
Fig. 3-25 Zoom on the electric field peaking at the metallurgical junction, and field fading within the
nearest oxyde.
As seen in figure, the simulator is capable also of reconstructing the field-vanishing
effect that is created within the insulating oxyde.
3.8.2 Intermediate frequency: f0 = 1 MHz
Previous analysis allows the prompt identification what is actually going on in the
varactor even when the forcing voltage oscillation is displaced to higher frequencies. This time
the amplitude of the waveform was set to 0.5 V and to an intermediate frequency of 1 MHz; the
behavior of the diode can be summarized as cumulatively reported in Fig. 3-26:
a)
e)
f)
b)
c)
73
g)
Chapter 3
d)
Investigation on AM-to-PM conversion effects
h)
Fig. 3-26 Electrons (left column) and holes (right column) quasi-Fermi potentials (imrefs) in the
varactor during the entire period of the sinusoidal sweep at 1 MHz.
In this simulation run the DC bias of the element was kept to 0 V, so as to appreciate the
effects of the temporary forward bias of the junction, even if only in the signal domain. Some
artifacts useful for the AM→PM conversion assessment can be noticed already.
The diagrams pertaining to holes give the main information. The potential profile is no
longer uniform over the three anode contacts, but it is modulated by the signal, extending back
and forth from the lateral sinker area. The sequence is clearly visible in Fig. 3-26e; the holes then
propagate into the n-zone during the positive part of the sinusoid, bringing the diode in the
forward state of Fig. 3-26f. The cathode is not completely emptied from holes, even at the
negative extreme of the driving: in Fig. 3-26g a residual of holes is still present besides the
depletion layer. The φp will relax from +0.46 V down to +0.18 V, but the positive charged
carriers remain oddly distributed until a new injection of majority particles (Fig. 3-26e) coming
from the p++ zone brings the equilibrium back. The generation and recombination times are set
internally to the routines, and vary according to the dependencies issued by the instructions given
in Paragraph 3.7.2; they are anyway expected to be around 1 microsecond (as can be derived
from Shockley-Hall-Read theory, [47]), hence comparable with the driving signal period.
The maps relative to the φn for the electrons are less rich in details; they can be compared
with the 1 Hz case. Figs. 3-26a and 3-26e are similar to each other, and to the corresponding
images of the previous simulation; the electrons are indeed less sensitive to the gradient in the
cathode zone. Although the current ought to change for the positive biasing of the junction, a
frequency of 1 MHz is evidently too fast to be followed synchronously by the carriers. Fig. 326b and 3-26d resemble the 1 Hz case, but are even more uniform (the cyan zone in Fig. 3-22a
was small already, but has now completely disappeared).
The charge flows relative to every domain can be aggregated in order to achieve the
current behavior of the junction, which we expect to be of capacitive kind. In effect, the curves
represented in Fig. 3-27 are almost completely in quadrature, with the current that leads the
voltage:
74
Chapter 3
Investigation on AM-to-PM conversion effects
Voltage across varactor [V]
Forward current in the varactor [A]
1-MHz sinusoidal transient
Time [s]
Fig. 3-27 1-MHz driving voltage, and current induced in the varactor. The lead and lag of the current
peaks relative to the voltage zero-crossings indicate the non-ideality of the carrier behavior (“inertia” of
the charge distribution).
The analysis is executed by Dessis in 400 steps, with maximum interval of 2.5 ns. From
the equation:
I MAX = jω 0 CVAR ⋅ VMAX
(3.12)
given VMAX = 0.5 V and IMAX = 3.6 µA, the value CVAR = 1.14 pF is derived, very close to 1.08 pF
at 0 V found in the Eldo model. Then the slight doping profile variations observed in the former
simulations are sufficient to generate the displacement currents needed to accomplish the wanted
capacitive behavior. The quadrature is imperfect however: the current tends to anticipate the
minimum and delay its maximum, with respect to the zero-crossing of the voltage. The capacitor
easily tracks the voltage when in reverse bias, whereas the forward region slows down the carrier
profiles and the capacitive response (ultimately, this is the electrical view of the device
bandwidth concept). When in reverse bias, the modulating voltage drives the borders of the
depleted region, moving the carriers within the zones into which they are in majority: the
response is regulated by the relaxation time of the material (τrel = ρ⋅εSi), which is usually less
than picoseconds. In forward bias the carriers are in minority, and their mobility is dominated by
the diffusion times (or: the capacitance, setting the pole of the varactor bandwidth together with
the diode transconductance gm-1, is exponentially risen). The equation (3.12) should be replaced
by the more precise (3.13):
⋅
⋅
(3.13)
I = CV + CV
to justify the non-harmonic current with respect to sinusoidal voltage. The rise in A0 issued to
pursue SSCR enhancement, bears this side effect that can be avoided with the linearization of the
tank (as it really happens in STARMAN, see Paragraph 3.2) at the price of a shrink in tuning range.
3.8.3 RF frequency: f0 = 2.6 GHz
Finally, the simulations in the operating conditions of our tank have been reproduced
with Dessis. The amplitude is again 0.5 V, and the corresponding period is around 380 ps. It is
75
Chapter 3
Investigation on AM-to-PM conversion effects
useful to recall here that this varactor is slower than the real one: if, even with this device, the
KAM-PM coefficient turns out to be smaller than expected from phase noise simulations carried out
in Paragraphs 3.2 and 3.4, then every dynamic effect can be surely ruled out.
Fig. 3-28 concentrates together the four states of the junction, with the driving sinusoid:
a)
e)
b)
f)
c)
g)
d)
h)
Fig. 3-28 Electrons (left column) and holes (right column) quasi-Fermi potentials (imrefs) in the
varactor, during the entire period of the sinusoidal sweep at 2.6 GHz.
The DC bias of the varactor has been left to 0 V again, to facilitate the comparison with
Fig. 3-26. The holes potential repeat the sequence of the 1 MHz case, but the gradients have
changed. From Fig. 3-28e to 3-28h we find the same conditions encountered before, but now the
potential is not varying even deep inside the junction (striking effect in Fig. 14h), and it keeps a
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Chapter 3
Investigation on AM-to-PM conversion effects
steady red component near the center of the diode. This means, the fronts of carriers are less and
less prompt to respond to the voltage stimulus. In Fig. 3-28e the hole accumulation under the
oxyde is more compact then before, since they have not begun scattering away. Analogously, the
electron configurations in Fig. 3-28a to 3-28d strictly match the one found for the 1-MHz case,
except for the restricted cyan area near the n zone of Fig. 3-28a, and the limited extension of the
blue strip in Fig. 3-28c.
3.9 The dynamic characteristic of the capacitance
A better idea of the dynamics of working of the diode can be derived again by the I-V
sinusoidal behavior, always at 2.6 GHz. The features already seen when the forcing signal was 1
MHz become exacerbated, but are qualitatively the same. The results can be compared also with
the schematic-level Eldo solution of the same circuit, which immediately appears to be in
excellent agreement with the device-level simulator response (Fig. 3-29).
2.64-GHz sinusoidal transient
Voltage across varactor [V]
V(Varactor)
I(Varactor)
Time
Time [s]
Fig. 3-29 a) Eldo and b) Dessis simulation of one period of the forcing sinusoid at RF (2.6 GHz). The
lead-lag fashion of the current wave is consistent, and reproduces the one observed in the 1 MHz case.
By applying equation (3.12) with VMAX = 0.66 V and IMAX = 12.2 mA, we reach again an
estimation of CVAR = 1.12 pF very close to the characterized parameters.
This time, two oscillation periods have been simulated (in about 1h 15’ on a WS Sun
Ultra-1) and we had the capacitance value extracted directly by Dessis. The software package
can in fact compound the transient and the AC simulations, by executing an AC analysis - with
annex CVAR extraction - for every point of the transient run. In practice, the carrier distribution
imposed by the transient evolution can be frozen, and employed for the traditional reactance
analysis. In every 380 ps period, the 8 carrier configurations are saved over the 1900 transient
points picked, and at every point an AC simulation is issued. During the two periods, the variable
capacitor takes the values illustrated in Fig. 3-30:
77
Forward current in the varactor [A]
b)
a)
Chapter 3
Investigation on AM-to-PM conversion effects
Varactor capacitance [F]
Instantaneous capacitance
of the varactor - 2 cycles
Oscillation voltage [V]
Fig. 3-30
Dynamic C-V characteristic of the varactor, taken over a 2-periods simulation. The
hysteresis in the capacitance plot derives from the delay in the carrier motion within the structure.
Capacitance [pF]
The inner piece of the curve is due to the initial transient, and is not trustworthy; it begins
exactly at 1.08 pF (the value set by tailoring the area factor of the varactor), but with too a flat
slope. The stable solution shows a hysteretical characteristic, i.e. it is a closed trajectory. This
plot was easy to predict, after the carrier motion studied and visualized so far; the explanation
why in forward bias (the right half of the diagram) the hysteresis is so marked comes
straightforward from the inertial attitude previously noticed on the carriers.
Therefore, it can be stated that the dynamic effects exist. However, the hysteresis could
lead to distortion in the oscillation and to reciprocal mixing of the noise, but it does not hold any
impact on the AM→PM conversion. The capacitance is periodic, and its periodical variations
could induce multiple spurious tones in the output spectrum; but the phase noise spectra will
result by an average of the instantaneous spectra, without undergoing any phase noise buildup. It
is instead the non-linearity of the dashed green average characteristic to determine the efficacy of
the unwanted conversion. The dynamic curve of Fig. 3-30 resembles closely the varactor nonlinear static characteristics that were used to issue Matlab simulations in Paragraph 3.2 .
Before going on with the dynamic investigation, the static capacitance curve has been
derived by steady-state simulation (operating point) in Dessis. The voltage DC sweep has been
instanced, from -2 V up to +1 V, and the capacitance has been extracted in every condition. The
resulting plot is depicted in Fig. 3-31, which is to be compared with the corresponding graph
obtained from Matlab in the cited Paragraph 3.2:
Voltage across the varactor [V]
Fig. 3-31 C-V curve relative to the varactor, obtained from Dessis after AC analysis.
78
Chapter 3
Investigation on AM-to-PM conversion effects
Two AC probing signals were defined, at 1 Hz (blue circles) and 1 MHz (red stars). In
effect, the curve is a little steeper than the original one simulated within Matlab environment; but
the derivative of the characteristic is increased by a factor < 2 only, that will not be enough to
explain the 40 dB discrepancy in the SSCR fitting attempted in the next Chapter. The plot can fit
with acceptable approximation the average of the close trajectory proposed in Fig. 3-30, and then
it is fully representative of the dynamic working of the varactor.
The graphs show a burst in the capacitance data around 0.8 V, where a value of 3.1 nF is
reached, before the successive collapse; anyway, the losses of the tank in strong forward bias
impair the use of such a working region. The red plot in Fig. 3-31 stays always under the blue
one; that is, the effective capacitance is progressively lower with increasing frequencies, and its
variations get smoother and smoother. Not only the high frequency driving does not worsen the
non linearity of the varactor, but it reduces the curvature of the C-V characteristic instead, since
the carrier within the diode lose their capability of tracking the incoming signal variations. The
slowness of varactor model with respect to the real one turns out to be beneficial, because this
dynamic effect could be seen at slower frequencies.
3.10 AM-to-PM variation with frequency
Capacitance [pF]
As a final proof, a range of 4 decades has been covered with 20 simulations, from 1 MHz
to 10 GHz. For each frequency, 12 AC simulations spanned the bias range from -2 V up to +1 V.
The results can be usefully visualized in at least two ways, namely:
• the 20 curves classified for different frequencies, in Fig. 3-32a:
Voltage across the varactor [V]
Capacitance [nF]
a)
b)
Voltage across the varactor [V]
Fig. 3-32 a) Results of the AC capacitive inspection extended over a 1 MHz–20 GHz range logarithmic
79
Chapter 3
Investigation on AM-to-PM conversion effects
space. In b) the view is pointed only at the strong forward bias of the junction, where the reduction in the
diffusion capacitance at higher frequencies can be better remarked.
Major variations occur in the upper range of the forward bias, hence the curves have been
zoomed in Fig. 3-32b (one point every 50 mV)
Capacitance [nF]
• a column diagram of the capacitance values at the various voltages applied, separated for
frequency; the sweep range of variability stands out particularly clearly from the histogram
representation of Fig. 3-33:
Frequency of the varactor stimulus [V]
Fig. 3-33
Bar plot of the capacitive variation swing, that highlights the progressive flattening of the
range as the frequency is raised.
The trend is indeed apparent: larger stretches of capacitance values, and consequently
major non-linearities, are generated for frequencies < 10 MHz. From the 80 MHz on, the
trend becomes nearly indistinguishable; anyway, the compression in the CVAR range is
monotonic.
The conclusion is that the Matlab simulations performed adopting the static characteristic
were even conservative, in principle: the high oscillation frequency of the VCO “sees” in reality
a flattened curve, since it swings at 2.5 GHz and above. The conventional formula for the
junction capacitance calculation gives a more linear behavior than the one given by this devicelevel simulation method, and the conversion coefficient KAM-PM may be increased by a factor of
about 2 according to the results of Figs. 3-30 and 3-31. The analysis may suffer from a modeling
inaccuracy regarding the transit time, and the adjustment factor is possibly not correct; but the
evaluation of the role of the KAM-PM is fully valid, and alternative mechanisms of phase noise
transfers other than AM→PM must surely be sought.
80
Chapter 4
Importance of Indirect Stability
Chapter 4
Importance of Indirect Stability
The increase in SSCR at high A0 is qualitatively and quantitatively explained in this Chapter.
After outlining some other non-linear effects hindering phase noise performance, the analysis of
the so-called Indirect Stability of the VCO is carried out. The stability with respect to different
electrical variables z is indicated by suitable sensitivity coefficients Kz, constructively defined here.
In particular, the sensitivity to the tail current noise, KTAIL, proves capable of converting into PM
the strong amounts of noise found in the previous Chapter, and eventually permits the fitting of the
SSCR data. The mechanism is ascribed to the displacement of the high-frequency singularities of
the transconductor, which is caused by the modulation of the bias tail current due to the noise. The
effect is verified through purposely issued circuit simulations. Two fast techniques suitable for the
simulation of the low- and high-frequency noise within the VCO are also reported.
4.1 Phase noise degradation at high oscillation amplitudes
A
s a reminder, Fig. 4-1 shows a schematic representation of the STARMAN-CUT
1.1 circuit. The tank has metal spiral inductors and reverse biased p-n junction
varactors, in series with metal-to-metal capacitors Cs, as described in Chapter 2;
the quality factor is close to 10, mainly limited by the inductors. The oscillation frequency (with
the usual tuning voltage Vtune = 1 V) comes about 2.6 GHz. The AC coupling between base and
collector of each transistor has made it possible to achieve oscillation amplitudes as high as A0 =
1.1 V with ITAIL = 11 mA (differential, zero-to-peak amplitude). The VCO was also provided the
amplitude control system.
V
Vtune
Vref
V0
2
V0
2
VB
Vext
Ipol
AMP
RE
Fig. 4-1 Schematic structure of the STARMAN-CUT 1.1 complete with the AAC system.
81
Chapter 4
Importance of Indirect Stability
As stated in Chapter 1, for large oscillation amplitudes almost only phase noise is found
at the output, due to the transconductor limiting action; anyway, the differential hard-limiting
and frequency dividing (¸2) stage following the VCO cuts off any residual amplitude
contribution from the output spectrum. The circuits were embedded within a complete digital
PLL structure, needed for the transceiver’s aims.
In Chapter 2, the original chip and test board were modified in order to change the VCO
oscillation amplitude: some inlets - usually engaged for the receiver section - were instead
devoted to route out the peak detector node and the tail driving node, together with the tuning.
By means of these external signals it was possible to open both the PLL and the AAC loops.
Adjusting the external voltage level Vext the tail current, ITAIL, of the transconductor was changed;
the actual ITAIL value was also checked by reading the voltage drop across the resistance RE = 50
W, external to the chip. The A0 value was read from the auxiliary output of the AAC peak
detector.
-70
S S C@
R @100
1 00kHz
kH z [dBc/Hz]
[d B c/H z]
SSCR
-75
-80
-85
-90
-95
-100
0.1
2
3
4
5
6
7
8
9 1.0
A
m pie zza dAmplitude
i osc illazionAe0 [V
]
Oscillation
[V]
Fig. 4-2 Dependence of the SSCR vs. the oscillation amplitude as measured on the CUT 1.1 test VCO
(triangles with solid line). The dashed line represents the estimate of the VCO phase noise based on the
theory presented in Chapter 1.
Fig. 4-2 shows again the dependence of the SSCR versus the oscillation amplitude
already presented in Chapter 2 (triangles with solid line), when the tail is connected directly to
ground and not to the BGR. The dashed line represents the largely unsatisfactory estimation of
the VCO phase noise based on the theory in Chapter 1. The first point, at A0 » 200 mV,
corresponds to the performance of the VCO just on the edge of oscillation - when the carrier was
not well settled. For 260 mV < A0 < 550 mV the measurements are in good agreement with the
estimate of the phase noise obtained according to the theory.
At larger oscillation amplitudes the discrepancy becomes apparent, and could be
explained by accounting neither the Q-loading effect nor the AM-to-PM conversion.
4.2 What do previous theories say?
Let us briefly examine the main approaches to the estimation of phase noise. As a first
attempt, theories exist (like [48],[49] for ring VCOs) which propose a fully linear derivation, that
82
Chapter 4
Importance of Indirect Stability
proves very intuitive but oversimplified in our case. The [12] theory supports the SSCR estimate
represented by the dashed line in Fig. 4-2; it accurately takes into account the non-linear transfer
mechanisms operating into the oscillator, but as shown it fails in predicting the final SSCR rise.
Both theories explain the birth of either AM and PM noise on the output waveform due to the
noise sources in the circuit. It is to be remarked, however, that none of them considers the
modulation of the phase loop delay (indirect instability, as is labeled in [37]), i.e. of the central
frequency, caused by the noise.
[3] is a more comprehensive treatise. Besides considering the multiplicative up- and
down-converted contributions to the phase noise, it also focuses on the phase instability that a
flicker on the tuning variable generates, through the VCO gain KVCO; as will be seen in
Paragraph 4.7 this further contribution, alone, does not explain the SSCR ramping either.
The more recently published theory in [20] – extended in [50] - accounts for the direct
and indirect frequency instabilities due to changes of the state variables, since it considers the
step-like DfOUT variation (i.e., impulsive Dw0 variation) induced by injecting a noise impulse into
a node. The model develops a time-dependent periodic sensitivity function, ISF, and accumulates
the elementary phase displacement due to every impulse (according to Campbell’s theorem); the
single impulse phase contribution is weighed by its own sensitivity, evaluated at the time
occurrence of the impulse relative to the carrier. The calculation is performed relying onto the
assumption of an unperturbed carrier; but the various pulses do influence each other exactly via
the displacement of the carrier. In the author’s belief, this subtle shortcoming can be theoretically
identified with the approximation that was inherent to the local linearization technique proposed
by [19]. It is probably this pitfall that impairs the correct prediction of SSCR behavior with the
non-linear theory [12] in our case. While the usual noise calculations assume that the poles of the
oscillator (or, the carrier displacement) are not affected by the slight change of the bias due to the
noise, we will find in the following that such an assumption is too narrow; the increase of the
SSCR at large A0 is precisely due to these effects. A systematical, critical approach to the general
phase noise theories based on the orthogonal decomposition of the perturbations in AM and PM
parts, can also be found in [51].
The following analysis wants to avoid the involvement in the complicated Floquet theory
(treated in [52]), in order to preserve an intuitive, designer-oriented and practical approach,
wherever possible. It can be instead classified among the “black-box” approaches, because it
exploits the simple sensitivity concept to recognize the effects causing the generation of phase
noise, it is no longer subject to this defect. We are not giving a generalized approach to the phase
noise theory; but instead, trying to furnish a fast and operative tool for phase-noise-generating
source identification and cancellation.
4.3 Additional phase noise generation mechanisms to be inspected
Concentrate on the theory in Chapter 1. It accounts for the non-linear transfer
mechanisms of the noise sources in the circuit, such as the shot noise of the tail current, the
thermal noise of the transistor spreading resistance, and so forth. For each noise source, the
contribution to the output amplitude (AM) and phase (PM) noise was computed, accounting for
the folding effects arising from the switching operation of the transconductor stage. However,
the analysis neglects:
i) the non-linear C(V) characteristic of the varactors
ii) the presence of higher harmonics of the fundamental frequency circulating into the VCO
loop, due to the low Q of the band-pass filter
83
Chapter 4
Importance of Indirect Stability
iii) the presence of the additional poles of the transconductor stage, and in general of the highfrequency singularities different from those set by the LC tank.
2 .6
2 .4
FOscillation
re q u e n za dfrequency
i o s cila zio n e[GHz]
[G H z ]
a)
Consider the effect i). In [12] it is shown that, due to the noise folding given by the
switching operation of the transconductor stage, the white noise spectrum SiT on the tail
contributes to both AM and PM output noise. The contribution to the phase noise can be
conservatively estimated by adding SiT/8 to the current noise of the lossy conductance of the
tank. In addition to this, any low frequency component (e.g. 1/f noise) should cause only AM
noise at the output, since the transconductor acts as a mixer for the low-frequency disturbances
entering from the tail (this standpoint is proposed also in [14]). Due to the non-linear C(V)
characteristic of the varactors, this is not strictly true: any amplitude modulation of the output
voltage at a low-frequency a, modulates the varactor capacitance (becoming a direct instability
issue, [37]) and therefore the oscillation frequency. The low-frequency noise of the tail current
can thus contribute to the SSCR worsening via the non-linear characteristic of the varactors. This
is the kernel of the AM-to-PM analysis of Chapter 3.
Effect ii). In low-Q oscillators the higher order harmonics are not effectively cut off by
the loop filter, and can recirculate. In this case, even if the tank has no varactors, and if the active
element does not introduce any further pole within the loop, the w0 is not necessarily equal to the
resonance frequency of the loop filter. The former is instead the one at which the self-sustaining
conditions are satisfied, not only for the fundamental harmonic but also for its higher-frequency
components [53]. Their presence modifies the congruence relationships for the carrier, whose
frequency gets related again to the noisy oscillation amplitude. This condition makes w0
dependent on the non-linear characteristics of the active elements, and ultimately on the circuit
bias point [13]. Fig. 4-3 shows the Matlab-Simulink system employed in order to quantify the
phenomenon, along with a resume of the series of simulations obtained. The influence of the
limited Q of the loop filter on the oscillation frequency stands out strikingly after the Q has
lowered under about 3.
b)
After
SIMULINK
2 .2
2 .0
1 .8
1 .6
1 .4
1 .2
0
2
4
6
8
10
F a tto re dfactor
i q u a lità
Quality
QQ
Fig. 4-3 a) Simulink 2nd-order tank+saturated transconductor system, issued to verify the effect of the Q
degradation on the carrier frequency. b) The collapse of
balance of higher harmonics.
w0
for Q < 3, required by the self-consistent
This mechanism is however more suitable for ring oscillator analysis, featuring Q lower
than integrated LC tanks, and its discussion will not be protracted here.
84
Chapter 4
Importance of Indirect Stability
Last but foremost, the effect iii). The presence of high frequency singularities provided
by the transconductor can lead to additional sensitivity of the output frequency, to the
modulation of the circuit bias point. For instance, by changing the tail current we may expect a
displacement of the high-frequency poles of the transconductor (i.e. an indirect instability
mechanism, see again [37]). The loop phase changes accordingly, and for sake of the
Barkhausen’s criterion the oscillation frequency varies.
In summary, as long as these effects can be neglected, phase and amplitude modulations
are well decoupled in the circuit operation, and their orthogonal decomposition is a correct
practice. In those cases, any variation of the transconductor bias point (e.g. the value of tail
current) affects only the oscillation magnitude while the oscillation frequency remains set by the
loop filter resonance. The output phase noise is therefore related only to the power spectrum of
the noise sources; difficulties arise solely from the switching operation of the active element. On
the contrary, as the effects listed above begin to play a role, any low-frequency modulation of the
electrical variables of the circuit may affect w0 at the output, thus causing a deviation Dw0cos(at)
of the instantaneous frequency. From this standpoint, the dashed line in Fig. 4-2 represents the
phase noise of the VCO circuit in absence of the effects now devised.
In the following we will show that these phenomena can be quantitatively accounted for
without incurring in lengthy numerical treatments. In Paragraph 4.10 we will also introduce fast
simulation procedures that make it possible to quickly estimate their effect on the output phase
noise.
4.4 Ranking the stability: the Kz coefficients
Let us assume that a low-frequency change of an electrical variable, say z, affects the
oscillator regime hence causing a deviation Dw0cos(at) of the instantaneous frequency.
Integrating Dw0cos(at) the resulting phase modulation is derived:
(
)
Dw 0
é
ù
V0 (t ) = A0 cos ò [w 0 + Dw 0 × cos(at )]dt = A0 cosêw 0 t +
sin(at )ú
a
ë
û
(4.1)
We define DfOUT(t)=(Dw0/a)×sin(at). Provided that the frequency peak deviation Dw 0 is small,
after straightforward application of trigonometric formulas the output waveform V0(t) is written:
Dw
Dw
é
ù
V0 t @ A0 cosêw0t + 0 sinat ú @ A0 cosw0t - A0 0 sinat sinw0t a
a
ë
û
(4.2)
The phasor representation of the above equation looks like in Fig. 4-4:
85
Chapter 4
Importance of Indirect Stability
2
A0 /2
A 0.Dw 0
a
DfOUT
( )
2
A0.Df
/2
2
( )
2
A0.Df
/2
2
A0
w0-a w0 w0+ a
a)
b)
Fig. 4-4 a) Phasor representation of the phase modulation leading to Eq. (4.4), and b) the two spectral
lines generated by the injection of the small tone of frequency, Eq. (4.5).
The phase modulation of the carrier is given by the peak of DfOUT(t), or:
Df OUT =
Dw 0
a
(4.3)
Eventually, using Werner’s formulas it is found:
V0 (t ) @ A0 cos(w 0 t ) - A0
Df OUT
(cos(w 0 - a )t - cos(w 0 + a )t )
2
(4.4)
Fig. 4-4 also illustrated the three tones featured by the phase modulation. The spectrum
of the signal in (4.2) features two lines, at w0±a, with amplitude A0DfOUT/2. Since the SSCR(a)
depends only on the noise power in a single side-band Df = 1 Hz of the spectrum, it is computed
by:
( A0 × Df OUT 2 )2
2
æ Df OUT ö
2
(4.5)
SSCR =
=ç
÷
2
A0 2
è 2 ø
Let us now denote by DfOUT=Dw0/a the maximum amplitude of the phase modulation. In
general, it may be written:
Dz
Df OUT = K z ×
(4.6)
z
where Kz coefficient represents the sensitivity of the output phase to a disturbance on the
electrical variable z. This may be regarded as a generalization of the KVCO concept also found in
[3]. A Kz coefficient can be associated to every noise source in the VCO circuit, and at every
offset a from the carrier. Owing to their dimensionless definition, these coefficients can be
readily compared in order to rank the importance of the effects due to different noise sources.
4.5 The KTAIL – Definition and direct measurement
Concentrating for instance on the tail current, we find that a modulation tone of DI TAIL
amplitude can be used to probe the conversion effect. In such a case, the general definition
proposed in (4.6) involves the ratio of the phase vs. current modulation indexes:
86
Chapter 4
Importance of Indirect Stability
KTAIL =
DfOUT
DI TAIL I TAIL
(4.7)
Eqs. (4.5) and (4.7) lead to the following SSCR addendum:
SSCRa × Df =
DfOUT 2
4
=
KTAIL a × DI TAIL
K 2 a DI 2 2
= TAIL × TAIL
2
ITAIL
2
I TAIL 2
4
=
(4.8)
By reversing (4.8) we eventually derive:
K TAIL a = 2 × SSCRa × Df
I TAIL
rms
DI TAIL
(4.9)
This last equation suggests a direct method to assess the coefficient: force a modulation
of the noisy variable under test (ITAIL in Eq. (4.9)) and measure the resulting phase noise tone on
the output oscillation.
By replacing the rms value of the modulation DI2TAIL/2 with the more general expression
for the noise power spectrum, in the last step to obtain (4.8), it is written:
SSCR a × Df =
2
a S iT a × Df
K TAIL
×
2
2
I TAIL
(4.10)
which is an extension of the formula in (4.8), allowing wider applicability.
R
VBias
RE
C
Vn
Fig. 4-5
Experimental setup for tone and white noise injection from the tail current generator. VBias
schematically represents the external biasing capability of the test chip (see Fig. 4-1).
In order to probe the sensitivity of the output frequency to the low frequency fluctuations
of the tail current, in STARMAN-CUT 1.1 the uncomplicated experimental setup in Fig. 4-5 has
been employed. By means of a HP ESG-D4000 signal synthesizer we have superimposed to
the DC level ITAIL = 5 mA (externally controlled; VBias schematically represents the external
87
Chapter 4
Importance of Indirect Stability
biasing capability, see also Fig. 4-1) a sinusoidal current tone DITAIL » 2 µA-peak at a = 2p×100
kHz, via the R-C external network depicted in the figure. The resulting modulation index of the
current was therefore as low as 0.4‰.
To monitor their power, the current tones inserted in the VCO were indirectly measured
by reading the sinusoidal signal (< 100 mV peak) induced on RE. By using HP8593E spectrum
analyzer the needed resolution is achieved (down to –125 dBW, or 4 mV rms on 50 W). Our
high-impedance amplifier (not shown in Fig. 4-5; it is discussed in the Appendix A) buffers RE
from the 50 W input impedance of the spectrum analyzer. All of the measurements presented in
the remainder have been obtained with a tuning voltage of 1 V across the tank.
In absence of any additional effects, the current tone should give rise to AM components
on the output signal at w0±a, which should be cut out by the following hard limiter stage (see
Chapter 1). In the snapshot of Fig. 4-6a we can observe instead two phase noise tones emerge
from the spectrum floor, 100 kHz away from the carrier. By measuring their relative intensity
(the injected tone was 1.7 mA this time) the KTAIL coefficient can be derived, based on (4.9). This
coefficient depends on the bias conditions, of course; repeating the measurements at different tail
currents (therefore, A0 values) we obtained the results marked with solid triangles in Fig. 4-6b.
a)
O scillatio n am p litud e [V ]
b)
0 .2
0 .4
0.6
0 .8
1.0
1 .2
1 .4
4
6
8
10
12
20 00
100kHz
KTAILK I pol
@@
100
kHz
16 00
12 00
8 00
4 00
0
0
2
T a il curren t [m A ]
Fig. 4-6 a) Spectrum analyzer snapshot of the oscillator output, showing the main phase tones excited
100 kHz away from the carrier by the insertion of the tail current tone, and the multiple spurious mixing
effects. b) KTAIL coefficient measured by inserting current tones into the tail of the transconductor.
88
Chapter 4
Importance of Indirect Stability
4.6 Fast evaluation technique for KTAIL
Despite the above experimental procedure has the worth of coming directly from the
definition of Kz, it is rather critical and cumbersome. A much easier characterization method can
be derived just writing (4.7) in differential form, and taking into account that DfOUT = Dw0/a:
K TAIL =
¶f OUT
¶w 0 I TAIL
=
×
¶I TAIL
¶I TAIL I TAIL
a
(4.11)
According to this formula KTAIL can be simply obtained by measuring the sensitivity of
the central frequency to the fluctuations of any electrical parameter z; the coefficient is
expressed - to a first order - by the derivative of the w0(z) functional dependence. Since it is
KTAIL squared that enters in (4.10), Eq. (4.11) and also Figs. 4-6b and 4-7 use its absolute value.
The rhombic dots in Fig. 4-7 represent the results of the w0 measurements, taken with the
spectrum analyzer, as a function of the bias current. The curve reaches a maximum of 2.64 GHz
when ITAIL is close to 3 mA; this entails that the KTAIL after differentiation (crosses) drops down
to zero in that range, consistently with the behavior already found by injecting current tones.
After the minimum, the KTAIL increases with a power law larger than the A02 that was found by
the static analysis of KAM-PM in Chapter 3. These results match very well those reported in Fig. 46b (triangles), thus confirming that the adoption of (4.11) can substitute the direct tone injection
technique.
More important: note that KTAIL features a V-shape compatible with the increasing SSCR
reported in Fig. 4-2.
2 00 0
1 60 0
@ 100kH
z
KKTAIL
100 kHz
I pol @
2 .6 5
1 20 0
2 .6 0
80 0
2 .5 5
40 0
0
0
2
4
6
8
10
O scillation frequency [G H z]
2 .7 0
2 .5 0
12
T ail current [m A ]
Fig. 4-7 Rhombic dots show the f0 vs. ITAIL curve measured on the test VCO (right axis). Following the
alternative technique leading to (4.11) the KTAIL dotted line fitting the crosses is derived, that closely
matches the triangles of the KTAIL obtained before with the classical tone injection (left axis).
89
Chapter 4
Importance of Indirect Stability
4.7 The key effect: impact of tail current sensitivity on SSCR
VCC
L
Osc. Ampl.
Vtune
C
Vref
Vext
VB
IT
AMP
VEE
RE
Fig. 4-8 Microphotograph of the test chip with the complete front-end of the DAB transceiver. The 3
VCOs are surrounded by the PLL blocks, the mixers and the power amplifier at the oscillation output.
Fig. 4-8 shows the microphotograph of the complete STARMAN-CUT 1.1 transceiver. The
three VCOs are tuned to different central frequencies in order to cover a broader Tx-Rx range.
Assuming a lowpass-shaped tail current noise as high as 0.2 nA/ÖHz, the contribution given
by the tail disturbances of the VCOs on the chip, transferred with KTAIL, eventually fits the
experimental results. This can be seen from the red dashed curve in Fig. 4-9, representing the new SSCR
prediction after sensitivity considerations have been taken into account. The current noise level is
higher than predicted, however we are going to show in the following that the ramping SSCR
dependence is a clear signature of KTAIL presence. No other effects can reproduce such a SSCR
dependence on A0.
Tail current ITAIL [mA]
SSCR @ 100kHz [dBc/Hz]
-70
1.0
1.7
2.5
4.0
6.0
8.5
0.6
0.8
1.0
-75
-80
-85
-90
-95
-100
0.2
0.3
0.4
0.5
Oscillation amplitude A0 [V]
Fig. 4-9 Blue line denotes the theoretical expectation, whereas the dashed red curve indicates the SSCR
prediction after that the sensitivity considerations have been taken into account: it accurately fits the
experimental curve (circles and solid line), provided 0.2 nA/ÖHz of rms tail noise are assumed.
The noise level of 0.2 nA/ÖHz needed to fit the experimental SSCR values in Fig. 4-2 or 4-9, is
well above the noise density estimated by taking into account the lone stages feeding the base of the tail
90
Chapter 4
Importance of Indirect Stability
transistor. From Fig. 4-10, the tail contributions due to the noise sources within the cell and the remainder
of the AAC left “on” can account for 0.05 nA/ÖHz @ 100 kHz The low pole that can be observed in the
figure pertains to the external filtering of the gain stage of the AAC, with 220 nF ceramic capacitor.
However, the shape of the SSCR dependence, univocally indicates that the noise contribution impairing it
at large A0 enters from the tail. As seen from Fig. 4-8, our VCO is operating within a complete RF front
end: the disturbances coming from the surrounding digital blocks (PLL prescaler, FPD, etc.), from the
RF-to-IF downconversion path, and especially from the oscillation amplifier (PPA) likely add to the
actual noise injected into the VCO tail. In complete transceivers such as [55] and [56], careful choices
were declaredly taken in frequency planning and circuit floorplan, in order to minimize the risk of
injection locking-pulling phenomena, and instabilities onset. The performance comparison between the
VCO in [57] and the corresponding complete PLL in [58] shows in effect a SSCR worsening, even if
very reduced (3 dB) with respect to the one here observed. To the same effects [59] refers, when
comparing stand-alone VCOs versus whole PLLs. In summary, the effect is not unknown in literature,
and the isolation of the substrate allocating the tail devices then must be fortified; in Chapter 7, special
care will be devoted to this aspect of the VCO layout.
The AC simulation of the current noise coming from the tail is shown in Fig. 4-10, and shows
only minor variations over the entire range of the bias current.
Tail noise – FILTERED AAC amplifier (Cext 220 nF)
Frequency
Fig. 4-10 Simulation of the current noise (in A/ÖHz) associated to the tail, when it is driven through the
LC external filter. At 100 kHz the noise value is about 0.05 nA/ÖHz, too low to explain the poor SSCR
observed.
To elude this quantitative inconvenience, and check further if the SSCR scales correctly with the
current tail noise, we injected a known level of white noise in parallel to the RE, and then measured the
SSCR as a function of A0. This technique was first adopted in [60]. The experimental values were then
compared to those derived by summing the phase noise predicted by the theory, and the additional term
of KTAIL sensitivity.
Operatively, our “white” voltage noise was synthesized by an R&S SMT06 Signal Generator,
internally low-pass filtered at 800 kHz, and fed to RE via an R-C (1 kW-66 nF) highpass network with the
apparatus of Fig. 4-5. Both the noise spectrum at the signal generator output and across RE were verified
with the spectrum analyzer.
Fig. 4-11 sketches the addition of the different phase noise terms. The dashed curve is the SSCR
derived from the sum of the theoretical and the KTAIL–induced contributions. The amount of noise coming
from the tail is known this time, since 1.6 mV/ÖHz were injected from outside; and the prediction is in
close agreement with the corresponding experimental data. The theoretical phase noise sets a baseline
onto which the higher KTAIL-converted noise builds upon, thus giving the total dashed graph that
fits the experimental data (solid line with triangles). Note the marked dip of the dotted graph, that
appears in proximity of the zero in KTAIL (A0 = 500 mV corresponds to about 3 mA of ITAIL).
91
Chapter 4
Importance of Indirect Stability
-70
S S C R @ 100kH z [dB c/H z]
-75
T otal
-80
-85
-90
A fter [12]
[9]
-95
KKTAIL
I pol
-100
0 .2
0.4
0.6
0.8
1.0
O scillation am plitude [V ]
Fig. 4-11
Details of the noise contributions to SSCR when 1.6 mV/ÖHz are injected in the tail. The
theoretical phase noise sets a baseline onto which the much higher KTAIL-transformed noise builds upon,
thus giving the total dashed graph that fits the experimental data (solid curve with triangles).
Another simple analysis, aimed to assure that the observed phase noise performance is uniquely
determined by the KTAIL conversion, relies on incremental noise injection. By doubling the level of the
white noise fed into the VCO, if the SSCR is really KTAIL-driven we can expect a uniform 6-dB rise in the
SSCR plot. Fig. 4-12 shows the spectra of the VCO output when the generated and injected voltage noise
was 1.6 mV/ÖHz rms and 3.2 mV/ÖHz rms, respectively: the expected 6 dB increase indeed happens.
Fig. 4-12 Phase noise spectra resulting from the injection of doubled lowpass-filtered noise levels from
the tail of the VCO cell. The 6-dB gap between the SSCR measurements proves the dependence of phase
noise on the low frequency noise affecting the bias current.
Fig. 4-13 demonstrates that the noise doubling is almost uniform on the whole A0 sweep. The two
measured curves – indicated in figure with solid circles and triangles – are spaced exactly 6 dB apart, for
the whole range except the dip zone. Near the dip, in fact, the predominance of the other PM
contributions over the KTAIL demotes the significance of the experiment. Also remark how the two curves
remain split well above 1 V of oscillation amplitude, where the measurements become more difficult
owing to saturation phenomena.
92
Chapter 4
Importance of Indirect Stability
-60
M easured 12m V
M easured 6m V
S S C R @ 10 0K h z (d B c/H z)
T heore tical fro m K am /pm
-70
-80
-90
-100
0 .2
0 .4
0 .6
O scillation a m p litu de (V olt)
0 .8
1.00
Fig. 4-13
The 6-dB gap is kept over the entire range of A0, except the zone immediately near the
minimum where the dominant contribution does not originate from the KTAIL term. The theoretical
predictions in dashed line fairly reproduce the measured SSCR.
4.8 BGR insertion countercheck
Last, we exploited the internal injection of noise provided by the BGR to probe the
consistency of the conversion hypothesis. When the tail resistor is tied to the BGR, the upper
graph in Fig. 4-14b is obtained that denotes a striking degradation of the SSCR.
Tail current ITAIL [mA]
VCC
VTune
VEE
I
T
SSCR @ 100 kHz [dBc/Hz]
VTail
-60
1.0
1.7
2.5
4.0
6.0
8.5
0.6
0.8
1.0
-65
-70
-75
-80
-85
-90
-95
-100
0.2
0.3
0.4
0.5
Oscillation amplitude A0 [V]
b)
GND
BGR
a)
Fig. 4-14 a) The lower rail switching capability of the VCO under test; b) Accordance between SSCR
estimate (upper red dashed line) and experimental data (triangles, solid line) with the tail connected to
BGR.
The theoretical red dashed plot fairly matches these results also. Thus we can state that
the phenomenon bedeviling the VCO under test has been definitely identified.
93
Chapter 4
Importance of Indirect Stability
4.9 Other sensitivities: to amplitude, tuning, and supply noise
The same sensitivity analysis has been performed on other electrical variables. First the
sensitivity of w0 to the changes of the oscillation amplitude A0 (effect i) in Paragraph 4.3) has
been determined, much like as done for CUT 1: in fact, this parameter represents the PM
conversion factor of the residual AM modulation on the tank, i.e. the traditional AM-to-PM
conversion.
This task cannot be accomplished by measurements: we have no direct access to the
standalone tank. Moreover, in order to change A0 we would be forced to vary other electrical
variables, such as the tail current, ending up in the evaluation of a combined effect. We would
thus fail in isolating the single phenomenon due to non-linear characteristic of the varactors. The
only alternative is to resort to simulations, as done in Chapter 3: they are performed both using a
behavioral static model within a Matlab environment (solid line in Fig. 4-15a) and the chargecontrol representation featured by Anacad Eldo (dashed line, same figure). This time, the
sensitivity referred to the oscillation amplitude disturbances was computed according to the
general definition:
KV0 =
¶w0 V0
×
¶V0 a
(4.12)
The resulting KVo coefficient in Fig. 4-15a is almost identical in shape to the STARMANCUT 1, as expected. The definition of KVo, formerly named KAM-PM, is based on sensitivity only
and appears more compact; but it can be proven to be identical to Eq. (1.33) presented before.
Notice that the coefficient is not only monotonic, but also more than one order of magnitude
lower than the KTAIL coefficient in Fig. 4-7.
Tail current ITAIL [mA]
60
1.0
-60
50
-70
SSCR @ 100kHz [dBc/Hz]
K V @ 1 0 0 kH z
0
70
40
30
20
10
a)
0.2
0.4
0 .6
0.8
O scilla tio n A m p litu d e [V ]
1 .0
1.2
b)
2.5
0.3
0.4
4.0
6.0
8.5
0.6
0.8
1.0
-80
-90
-100
-110
-120
0
0.0
1.7
0.2
0.5
Oscillation amplitude A0 [V]
a) The simulated KVo behavior. The solid line comes from behavioral Matlab analysis,
whereas the dashed line from Eldo schematic simulation; the lack of the minimum and the limited
magnitudes make KVo markedly differ from KTAIL. b) KVo (AM-to-PM) contribution with BGR inserted
(green line with rhombic dots).
Fig. 4-15
The SSCR plot illustrated in Fig. 4-15b has been measured on STARMAN-CUT 1.1 with
the lower rail connected to the BandGap Reference (triangles). The up-conversion of the strong
band-gap noise discussed in Chapter 3 causes an AM noise of 183 nV/ÖHz across the tank [12].
Even taking the maximum KV0 value of 60, the limit to the SSCR is still –97 dBc/Hz at 1.1 V,
94
Chapter 4
Importance of Indirect Stability
and lies well below the experimental results (Fig. 4-15b), uniformly 40 dB lower. Hence it turns
out that, even if AM-to-PM conversions are present, their impact on the SSCR degradation is
negligible. The dynamic correction of the coefficient proposed in Chapter 3 led only to minor
adjustments of the KVo magnitude: as a consequence, this parameter can be definitely ruled out
from the present analysis. At any rate, the simulation procedure outlined in the section can be
useful to estimate the impact of the effect during the design of alternative oscillator topologies.
Let us now consider the effect on the SSCR of the noisy tuning voltage Vtune. Following
the general formula (4.7), the sensitivity of w0 to Vtune is given by:
KVtune =
V
¶w 0 Vtune
×
= KVCO × tune
¶Vtune a
a
(4.13)
This coefficient is proportional to the more popular KVCO expression [3], and depends on
the circuit bias point (e.g. Vtune, ITAIL etc). Therefore, in order to check its contribution to the
SSCR, we have to derive the KVtune in the same bias conditions at which SSCR was recorded. To
this purpose, Vtune was kept equal to 1 V and A0 was changed via the tail current ITAIL, as done in
former measurements. The local KVtune value was obtained from the incremental ratio Dw0/DVtune
with DVtune = 100 mV. Fig. 4-16a summarizes the results.
a)
b)
1 300
Tail current ITAIL [mA]
1.7
1.0
-60
2.5
4.0
6.0
8.5
0.6
0.8
1.0
SSCR@100kHz [dBc/Hz]
1 200
1 150
KV
tune
@ 100kH z
1 250
1 100
-70
-80
A
-90
-100
B
-110
C
-120
1 050
0 .0
0 .2
0 .4
0 .6
0 .8
1 .0
1 .2
0.2
0.3
0.4
0.5
Oscillation Amplitude V0 [V]
O scillation am plitude [V]
Fig. 4-16 a) The measured KVtune sequence; each point is obtained by a first-order sensitivity estimate
at a fixed tail current. The high sensitivity associated to the tuning node justifies the spread affecting the
data scatter; note the expanded vertical scale. b) The KVtune contribution to the SSCR is not the limiting
one (dark red line with squares).
Note that the magnitudes of the KVtune are not far from those of KTAIL. Once converted in
SSCR figure, a voltage noise spectral density of 11 nV/ÖHz perturbing the tuning node can in
principle keep phase noise performance above –100 dBc/Hz, when KVtune approaches its
maximum (see curve B in Fig. 4-16b). However, the negative slope of the KVtune vs. A0 profile –
put into evidence by the expanded scale of Fig. 4-16a - does not match at all the ramping
dependence of the SSCR, hence its impact on our circuit performance can be ruled out. It was
this “strange” mismatch that actually triggered us to extend the sensitivity concept found in
[3,16].
95
Chapter 4
Importance of Indirect Stability
Note that other electrical variables could be inspected via this technique. For example, some
analyses amenable to this same principle were recently performed in [61] and [62] on the supply
noise of a ring oscillator, but even there they lead to nearly monotonic sensitivity behavior.
4.10 Fast simulation techniques for phase noise assessment
Since the oscillator phase noise is still the tightest bottleneck for the integrated receiver
solutions [13], there is strong interest especially towards the availability of phase noise
prediction tools, usable right from the starting steps of the design flow. The experimental
procedures presented above can be used to quantify the sensitivities during the earlier design
phases. To evaluate the best viable ways to accomplish this task, we performed a brief
comparison of different simulation techniques suitable for the aim, from time consumption and
processing complexity standpoints.
The simplest (and most widely adopted) technique for the general noise prevision is the
AC noise simulation: the bias point is first achieved, thereafter an equivalent linear lumped
circuit, which locally approximates its behavior, replaces each non-linear element. However,
oscillators belong to a class of circuits that, more than any other, is characterized by inherently
non-linear behavior. In fact the oscillation amplitude is usually to be limited by the non-linearity
of an active element. As a consequence, AC simulation is no longer suitable for the evaluation of
the phase noise, especially if operating at high oscillation amplitudes.
Software packages like Anacad Eldo allow transient noise simulations. Despite it takes
into account the non-linear behavior of the system, this technique also suffers some
disadvantages: for example, it does not give the possibility of focusing the most critical noise
source by issuing one noisy component at a time, and thus making it difficult to optimize the
cell. Moreover, since working in the time domain, it usually necessitates rather lengthy
simulation runs.
On the other hand, simulators in the frequency domain such as Libra or EldoRF are much
faster [63], and inherently based on concepts such as correlation matrices [64]. But in Chapter 2
SpectreRF was found to lose the SSCR rise with the amplitude; near the carrier in fact these
algorithms suffer sometimes convergence problems [65], and maybe the phase noise
contributions due to the modulation of the loop delay can be missed. In addition, the Harmonic
Balance solving is not available in low-end simulation tools such as PSpice.
4.10.1 The traditional tone-insertion approach
For all of these reasons, up to now one of the most common methods to analyze noise in
non-linear circuits has consisted of injecting harmonic tones in place of the noise source [3],[34].
In order to evaluate the Kz factors one may resort to an Eldo replica of the experimental current
tone insertion technique. The rationale supporting this technique is again the well-known
Campbell’s theorem [21]: superposing a series of Dirac-deltas, either in the frequency or in the
time domain [20] can represent white Gaussian noise. This widespread technique is however
very slow; in particular, in the frequency domain a high spectrum resolution is needed in order to
evaluate correctly the noise components close to the carrier. Moreover, aliasing effects must be
avoided. These issues lead to lengthen the CPU time, therefore the simulations cannot be
96
Chapter 4
Importance of Indirect Stability
efficiently iterated for different values of the oscillation amplitude and of the other electrical
parameters under investigation.
The LC-tuned differential oscillator completed with the tail noise source. SnI
Fig. 4-17
represents injected noise, either white or in tones.
Let us apply this procedure to the oscillator in Fig. 4-17, and in particular to the analysis
of the tail noise source SnI. The free running frequency of about 2.5 GHz has been reproduced. A
slow (1 MHz) current sinusoid DItail×cos(at) is injected in parallel to the tail generator, and the
output oscillation waveform obtained from the Eldo transient analysis is saved; then suitable
Matlab post-processing (hard-limiting, FFT and power normalization) is made, and finally we
can determine the power of the emerging PM tones. Despite the non-linearity of the system, the
phase response of the oscillator to an injected tone keeps almost linear if a low modulation
(DItail/Itail < 0.1%) is applied; under this assumption, a series of single-tone analyses can be
considered representative of the overall white noise.
First the current tone was 5 mA-peaked, superposed to a bias value of 10 mA (0.05%);
the oscillation amplitude A0 is 1 V (0 dBV). The final output spectrum is reported in Fig. 4-18a
and shows two phase tones at 1 MHz offset from the carrier. The eventual SSCR given by the
tones is –27.5 dBc (it is not noise density, but noise concentrated in a tone – then, dBc and not
dBc/Hz).
a)
b)
Fig. 4-18 a) Spectrum of the output voltage of the oscillation, after the injection of a 5 mA-peak current
tone at 1 MHz. b) Power spectrum of the phase noise tones when the tone is raised to 30 mA. The side
replicas are due to the non-linear working regime of the transconductor.
97
Chapter 4
Importance of Indirect Stability
Next (Fig. 4-18b) the current modulation adopted was increased to 0.6% (30 mA-peaked
current tone over 5 mA), with the oscillation amplitude reduced to A0 = 670 mV (giving a carrier
power of +6.6 dBm when referred to 50 W impedance). The non-linearity of the circuit causes
the birth of a number of side replicas, which were partially sunk in the noise floor during the
actual measurement (see Fig. 4-6a). According to (4.9) a value of about 1100 can be calculated
for KTAIL at 100 kHz.
This method is very time-consuming. Even adopting tones at 1 MHz, then quite far away
from the carrier (f0 = 2.5604 GHz), each SSCR computation requires about 10 hours of
simulation time on a Sun Ultra-1 workstation. In fact, a spectral resolution of at least 100
kHz is needed, in order to determine the SSCR at 1 MHz offset from the carrier in a reliable
way: this means that the oscillator is to be simulated for > 10 ms, considering an initial transient
of about 100 ns. Moreover, the Fourier transform operates on a signal sampled at frequency fs,
then the spectrum is replicated at frequencies kfs; in order to avoid aliasing phenomena, that can
easily hide the weak phase noise tones, a sampling frequency of at least 10×f0 has appropriately
been chosen. This requires a time step of 40 ps with an oscillation frequency of 2.5 GHz.
Therefore the total number of points of the FFT is given by N = 10ms/40ps = 2.5×105 points, to be
processed for each tone injection.
Furthermore, the time step of the transient simulation cannot be chosen as wide as 40 ps,
because this would imply a failure in convergence to the actual behavior of the circuit. The
simulated oscillation waveform tends in fact to decrease in amplitude and increase in period,
when the accuracy of the solution is relaxed by raising the minimal allowed time step. The
maximum time step still guaranteeing convergence was found to be 3 ps when the oscillation
period is 400 ps, which gives more than 3×106 simulation points in order to cover the whole 10
ms.
To proceed to the optimization of the cell, these long simulations should be repeated
several times. For example, phase noise should be analyzed at different oscillation amplitudes
and by injecting the harmonic tone from different nodes, and at different frequencies (low
frequency, in-band and at frequencies multiple of the carrier).
4.10.2 Optimization for sensitivity method
Eq. (4.11) suggests a very effective procedure to figure out the phase noise of an
oscillator from simulations. Much like in measurements, by changing step-by-step the biasing
current ITAIL of the VCO with Eldo, the oscillation frequency w0 can be derived as the reciprocal
of the oscillation period. Once extracted, the w0 vs. ITAIL dependence leads to the SSCR
estimation through the relation given.
The total range of the tail current can be swept with only one simulation, by adopting a
piece-wise linear source for the voltage Vtail (see Fig. 4-17). One different frequency value will
be induced by each Vtail step, which should last long enough as to allow the settling of w0; in our
case, the oscillation settled within 1000 cycles. Simulated results come out as illustrated by the
solid curve (triangles) of Fig. 4-19: the entire 14-points sequence has been obtained in about one
hour. In order to validate the presented method, it was successfully compared with the results of
the classical tone injection: each validation point required more than 10 hours of simulation. It
would have been very impractical to draw the entire curve by following the traditional approach.
The tuning voltage was fixed to 1 V in all the simulations.
98
Chapter 4
Importance of Indirect Stability
Fig. 4-19 The frequency vs. bias current Eldo simulated curve (solid line) compared with the frequency
measurements taken on three different specimens of the test chip (dashed lines). The prediction lies very
close to the experimental data, and the fit is further improved after the temperature correction proposed
in Appendix B.
The figure also reports the experimental data collected over three different specimens of
the test chip (dashed lines). By comparing simulated and measured curves, one can appreciate
how the simulated behavior lies well within the experimental spread. In particular the frequency
offsets, so apparent in Fig. 4-19, are in reality as low as 3.4% and can be explained by the
random dispersion in the parasitics on the die: a junction capacitance tolerance in excess of
±10% is still deemed acceptable in bipolar technologies.
This simulation approach, here employed for the analysis of the tail noise, can be easily
generalized to other nodes of the circuit. For example, voltage variations can be superimposed
onto the power supply, obtaining a KV+ vs. A0 curve. V+ can be automatically varied of only one
step, while contemporarily ITAIL is stepped to reproduce the growing A0 sequence. This exactly
replicates what pursued in Paragraph 4.9 for the analysis of the KVtune impact on the SSCR.
al
ion
dit
a
r
T
ELDO
ity
itiv
ns
Se
ion
lat
du
o
m
De
Postprocessing
0
2
4
6
8
10
12
Simulation Time [hours]
Fig. 4-20 Comparison of the three simulation techniques for the estimation of phase noise at different
frequencies in oscillators. The CPU time required is indicated on the horizontal axis, and accounts for
both actual circuit simulation and post-processing time
99
Chapter 4
Importance of Indirect Stability
Fig. 4-20 shows the CPU time duration of a single simulation, when either the traditional
method or the sensitivity method is employed. It accounts for both the net Eldo simulation and
the post-processing time (FFT for the traditional, differentiation for the sensitivity, and
frequency extraction for the demodulation method). The sensitivity technique proves therefore
very fast and reliable, and the designer can use it to concentrate on the low-frequency-induced
PM analysis, during the Spice-aided a priori evaluation of phase noise during the oscillation
draft. For instance, the effects due to the flicker noise of the devices can be effectively addressed
in this way.
4.10.3 Frequency demodulation method
The sensitivity method is a quasi-static approach. Only quasi-static variations of the
oscillation frequency are considered, as a result of step variations of the tail current. The
sensitivity obtained in such a way is then extended to the low frequency modulations of the tail
current. The method is no longer suitable, anyway, if the effects of high-frequency noise
components have to be investigated.
Let us consider the injection of a current tone from the tail at a frequency double than the
carrier. At high oscillation amplitudes, the differential transconductor acts as a hard-limiter
giving a square wave current at the output. If a tone at (2w0+a) frequency is injected, it mixes
with the carrier at w0 giving rise to two tones at (w0±a), that represent either an amplitude or a
phase modulation (Chapter 1) as seen in Fig. 4-21.
Amplitude modulation on Vout
Instantaneous frequency [Hz]
Time
Fig. 4-21
Evolution of the envelope and the frequency of the synthesized oscillation when a 5 mApeaked current tone at (2w0-a) is injected in the tail. The FM peak is Df0 » 350 kHz. The frequency
demodulation in the lower graph is performed by means of a Xelga user-defined function.
Even in this case, the traditional approach of simulating the circuit and then performing
the FFT at the output can be considered; but a faster method can be devised in order to avoid the
use of FFT and save simulation time. If a harmonic tone inserted in the circuit produces two PM
tones near the carrier, a modulation Dw0cos(at) has been induced on the oscillation. In fact the
100
Chapter 4
Importance of Indirect Stability
frequency is the time derivative of the phase of the output oscillation, therefore Dw0=a×DfOUT in
the sinusoidal stimulus case. The SSCR is thus given by:
æ Dw ö
æ Dfout ö
÷ = ç 0÷
è 2a ø
è 2 ø
2
SSCR a = ç
2
(4.14)
The expression suggests that the SSCR can also be computed by injecting a harmonic tone in the
circuit, and frequency-demodulating the output waveform. The frequency evolution caused by
the insertion of a current tone in the tail of the oscillator, at angular frequency (2w0+a) where a
= 2p × 1 Mrad/s, is shown in Fig. 4-21. The estimated FM peak due to the 5 mA current tone is
Df0 » 350 kHz, which leads to SSCR about -15 dBc on that tone.
In order to derive the FM peak Dw0 only one period of the inserted modulation is
sufficient. Therefore, when injecting a tone 1 MHz away from the 2w0 frequency, we need to
simulate only 1 ms instead of the 10 ms required before; in addition, there is no longer necessity
of the FFT itself. The comparison between the CPU time spent to exploit this method against the
traditional one can be seen in Fig. 4-20; the saving of time is quite evident. Notice how the
demodulation method may also be employed for low frequency tones, but the sensitivity method
is computationally more convenient in such a case.
The only potential difficulty of this procedure is represented by the execution of the
frequency demodulation. Anacad Xelga software, often associated to Eldo for waveform
visualization and processing, implements the function intersect(wave1,wave2) which seeks for
the time instants at which the two waves cross, by means of linear interpolation between the
points truly simulated [31]. Hence a user-defined function can be created that automatically
computes the instantaneous oscillation frequency of the output voltage waveform. The function
first builds a constant vector C that contains the mean value of the voltage oscillation vector W.
By means of intersect() the time sequence tz(n), i.e. the time occurrences of the crossings
between the waves W and C, can be achieved. The oscillation period of the cycle n is trivially
given by the vector difference between the zero-crossings: T(n) = tz(n + 2) – tz(n). All the w0
simulations throughout the dissertation are obtained by means of this automatic algorithm.
Applying the procedure to an oscillation vector composed by 2.5×104 points (covering 1 ms) takes
about 20 minutes.
-1 0
S S C R @ 1 M H z [d B c ]
(A 0 )
-2
-1 5
-2 0
-2 5
-3 0
0.1
2
3
4
5
6
7 8 91 .0
O scillatio n A m p litud e [V ]
Fig. 4-22 SSCR vs. A0 resulting by the injection of a harmonic tone (5 mA-peak) at (2w0+a) in the tail,
at 1 MHz. The circles are derived by the frequency demodulation method, whereas triangles are obtained
from the standard FFT technique, and lie on the same curve.
101
Chapter 4
Importance of Indirect Stability
The procedure has been repeated at different oscillation amplitudes, always injecting a
5 mA tone at (2w0+a). Again in this case, the method is successfully compared with the
traditional one. The results are illustrated in Fig. 4-22; circles are derived by the frequency
demodulation method, whereas triangles are obtained from the standard FFT technique. As
expected from the noise folding theory, at high oscillation amplitudes the noise factor settles and
the SSCR features the standard A0-2 dependence [12],[13].
In conclusion, the new techniques are at least one order of magnitude faster (in worst
case!) than the traditional one, and can be implemented with any commercial, low-cost circuit
analysis software.
4.11 Circuit interpretation of indirect instability
Fig. 4-2 showed as a reference the phase-noise performance of the cell computed
according to Eq. (1.30). This estimate accounts for the folding of the noise spectra when the
transconductor departs from the small-signal operation and enters the more realistic switching
regime. This phase noise is computed under the general assumption that the central oscillation
frequency w0 remains fixed, set by the tank resonance, and that other interference phasors add to
the carrier. Nevertheless, further phase noise can arise from other phenomena that cause w0 to
jitter. As stated before, attention has been recently focused on the random fluctuations of the
tuning voltage or of the positive supply; however, as seen in Fig. 4-16b these contributions were
not sufficient to explain the experimental SSCR. We hypothesized that w0 jitter can come from
the poor indirect stability of the oscillator.
In a real oscillator, the resonance frequency w0 is not simply set by the LC parameters of
the tank. The presence of the additional poles of the transconductor stage, and in general of high
frequency singularities, adds a contribution Dqloop to the loop phase, and the Barkhausen’s
criterion mandates for a frequency:
_
_
w
× Dq loop
w0 = w (4.15)
2Q
_
w
where w = 1 LC , and
is the slope of the characteristic in the proximity of the abscissa
2Q
crossing. It follows that w0 may change not only due to variations of Vtune but also of the other
electrical variables affecting Dqloop (e.g., the transconductor bias current). A visual representation
of this concept can be given as in Fig. 4-23:
q loop
Dw 0
_
+90°
0°
w0
w
Dq
Fig. 4-23 Modulation of the carrier oscillation frequency w0 (intersection of the curve with the 0° axis)
caused by the variations on the phase of the loop. These latters can be given by the noise-induced
displacement of higher frequency poles.
102
Chapter 4
Importance of Indirect Stability
4.12 The role of the transconductor poles
Let us consider now the mechanism that can lead to dependence of the output phase from
the tail current. Fig. 4-24 schematically shows an equivalent single-ended circuit of our LCtuned oscillator, highlighting the load due to the transconductor and its delay. The transconductor
input impedance, in parallel to the tank, is essentially due to the base spreading resistance rbb' and
to the diffusion capacitance Cp. In fact at w0 the base resistance rp is much larger than the
impedance of Cp. As the transistors switch, all of these terms are time-dependent. Even if Fig. 424 has to be regarded only as a qualitative model, it highlights how the low frequency noise from
the tail current can affect the output frequency.
L
C
R
r
bb'
Cp
vp
g e wtvp
-j
m
Fig. 4-24
Schematic representation of the LC-tuned oscillator, highlighting the load due to the
transconductor and its internal delays (spreading resistance-diffusion capacitance pole, and base transit
time).
In fact, the input impedance of the transconductor and the transistor transit time are both
depending on ITAIL and add a phase delay Dqloop to the feedback loop. According to Barkhausen’s
criterion, the oscillation frequency is therefore shifted from the resonance frequency of the tank,
1/ LC , to [37]:
é Dq ù
w 0 @ 1 ê1 - loop ú
(4.16)
2Q û
LC ë
Dqloop is obviously expected to depend on ITAIL.
Taking the appropriate values of SiT @ 100 kHz with and without BandGap Reference,
Eq. (4.10) correctly gives the dashed lines depicted in Fig. 4-14b that fairly match the
experimental values. However, it is still to be verified whether this effect is actually due to the
dependence on IT of the phase delay Dqloop, as proposed in Paragraph 4.3 . Circuit simulations have
been therefore performed in order to validate this framework.
4.13 Simulative validation of the instability concept
The curve (I) in Fig. 4-27 was first derived, as a reference. It represents the simulated
w0(ITAIL) function obtained following the same experimental procedure leading to Fig. 4-19. The
differences with respect to the experimental w0(ITAIL) curve in that former figure could be ascribed to
inaccuracy of the parameters adopted in the circuit models. If the w0 sensitivity to ITAIL is caused by a
103
Chapter 4
Importance of Indirect Stability
modulation of Dqloop, the values obtained after Eq. (4.16) using the Dqloop data derived from circuit
simulations must be close to curve (I). The sequence of the Dqloop can be estimated by opening the
feedback (as schematically shown in Fig. 4-25a) and injecting into the loop a sinusoidal current
signal at the tank resonance frequency. Dqloop is the phase shift between the first harmonic of the
transconductor output current and the voltage driving tone (Fig. 4-25b gives a circuit view of the
technique).
a)
b)
V
I
V
L
C
r
R
vp
bb'
Cp
I
gmvp
I
VEE
T
Dq
RE
Fig. 4-25 a) Open-loop scheme of the circuit used for the evaluation of the phase loop delay due to the
transconductor. b) Extraction of the variable loop delay as voltage-current lag. The oscillation frequency
shift is then obtained after Eq. (4.16).
In practice, in the circuit simulations the tank was removed, and the differential pair was
driven by a voltage source having a series resistance equal to the tank resistance Rtank (Fig. 4-26).
Of course the voltage amplitude was set to the A0 value consistent with the corresponding ITAIL.
Since at the resonance frequency the LC parallel is an open circuit, the adoption of a voltage
source corresponds to a Thévenin equivalent of the current generator in Fig. 4-25a, and has the
advantage of directly setting the A0 value.
VCC
I
Rtank
2
+
Rtank
2
V0
cos(w0t)
2
IT
VT
V0
cos(w0t)
2
RE
VEE
Fig. 4-26 The circuit detail of the loop delay evaluation technique illustrated in Fig. 4-25b.
104
Chapter 4
Importance of Indirect Stability
Curve (II) in Fig. 4-27 shows the results obtained by substituting in Eq. (4.16) the Dqloop
values derived in this way. The profile obtained closely matches curve (I), thus confirming that
the key instability effect is related to the modulation of the transconductor delay.
Oscillation Frequency [GHz]
2.64
2.62
2.60
2.58
2.56
I
2.54
II
2.52
2.50
0
1
2
3
4
5
6
7
8
9
10 11
Tail current ITAIL [mA]
Fig. 4-27 Simulated dependence of the oscillation frequency on the bias current, curve (I). Curve (II) is
the dependence of the oscillation frequency as derived from Eq. (4.16), when applied to the phase delay
Dqloop obtained after the simulation of the open loop circuit.
The investigation of the mechanisms acting into the circuits to give the loop delay, and
ultimately the oscillation frequency behavior observed in Fig. 4-27 is complete only for the
descending fraction of the curve. The increase in current is compatible with the progressive
downshift of the RtankCp pole, and the saturation of the devices in the transconductor will lead to
the final crumble of the frequency. We will now try to explain the rising initial part of the curve.
To split the phase sensitivity effects within the transconductor, two kinds of simulations
have been performed:
· with Rtank: the generator was a real one, and drove the cell through the tank series
resistance
· without Rtank: the transconductor cell was driven by an ideal voltage generator.
The loop delay in the first case is depicted with the red upper curve, B) in Fig. 4-28. The vertical
axis expresses the delay in percentage of one complete period, quoted in degrees: e.g. +90°
means a lag in the loop equal to ¼ period, -180° a half-period lead in the phase. As shown, the
delay provided by Rtank is the most remarkable one, and its rise with ITAIL can be ascribed to Cp
growth.
In the second case a further branch can be studied:
· modified models for the transistors, in which both geometrical and diffusion
capacitances have been brought to zero - while still adopting a real tail source, and
keeping the CE capacitor between the emitters: even a phase lead is observed, slightly
growing with ITAIL. This is the lower orange curve in Fig. 4-28, labeled A)
· bipolar standard modeling, but ideal tail current sources and CE capacitor removal: the
characteristic features again a slow rise in the delay of the oscillator loop.
105
Chapter 4
Importance of Indirect Stability
Transconductor delay composition [°]
40
30
B) Ideal Tail - Real transc. (rbb')
20
10
0
without
Rtank
Delay
composition (A+B)
-10
-20
A) Real tail (C E) - Ideal transc.
-30
0
2
4
6
8
10
12
Bias tail current ITAIL [mA]
Fig. 4-28 The detailed splitting up of the effects contributing to the transconductor delay: the transistor
slowdown with increasing current (curve on top, lag) and the interaction with the tail singularities (curve
on bottom, lead), once composed give the overall phase delay previously obtained in closed-loop
simulations.
By composing A) + B) plots, the dark-green dashed graph is obtained that approaches the
blue solid line. The latter curve indicates the loop delay as was achieved by simulating the
complete VCO. These data were substituted in the formula (4.16) to give the frequency
displacement finally displayed in Fig. 4-27. For, the two main terms that constitute the loop
phase delay have been tracked and identified; the initial “strange” lead in the loop phase is due to
the effect of the oscillator tail, that after a certain current is overwhelmed by the other term.
Given that the delays were caused by the presence of poles, the circuit explanation of the lead
has been sought in zeros.
VP
VP
IOUT
CE
VIN
IPOL/2
RE
2CE
IPOL
Fig. 4-29 The phase lead effect can be explained through the combined pole-zero displacement, with
the increase in current, into an emitter follower structure set equivalent to the half-transconductor. CE
plays a major role in this phenomenon.
Having a capacitor CE = 1.5 pF and Early resistors of the half-tail generator on the order
of r0×(1+gmRE) » 125 kW at ITAIL = 7 mA, the zero lies about 420 kHz. A pole is also provided by
the tail structure depicted in Fig. 4-29, but with currents of milliamps the gm-1 assures a pole over
106
Chapter 4
Importance of Indirect Stability
10 GHz. The two singularities partially compensate each other in the loop phase, but the zero is
split enough from the pole and gives heavier contribution to the phase at w0, speeding up the
loop. With increasing currents, the output resistance of the tail tends to degrade, while the pole is
progressively rising: the net effect is a uniform lead phase contribution near the w0 frequency, as
suggested by the curve A).
Last, it is interesting to note that in [66] a coefficient G1/f is devised to rank the impact on
SSCR of the upconverted 1/f noise, coming from the tail, in a differential cross-coupled CMOS
oscillator of the type proposed in [8] and topologically very similar to STARMAN. The coefficient
represents a simple figure of merit to assess the symmetry of the commutations in the LC
oscillator, and is based on the Hajimiri’s G phase sensitivity theory explained in [20], and applied
to CMOS LC VCOs in [67]. Through a simple analysis of the slopes at the rising and falling zero
crossings, the G1/f relative to the tail is obtained as a function of oscillation amplitude:
surprisingly enough, it features a V-shaped behavior similar to our KTAIL proposed above. Such a
behavior was ascribed completely to the asymmetry of the oscillation. The scientific debate is
still alive on the topic [68], since device-level phenomena have not been considered in the
derivation; for example, the noise reduction due to the rapid inversion and accumulation of the
MOS transistors, that leads to the phase noise lowering technique recently reported in [69].
Anyway, in the author’s opinion the additional V-shaped effect reported seems to be very
peculiar of the CMOS implementation, and not of the cross-coupled topology. Unfortunately, in
[66] a quantitative conversion of tail noise into SSCR is not provided, and thus the verification of
the correctness of the hypothesis that relies on symmetry is virtually impossible.
4.14 The last unknown
In all of the preceding parts of the Chapter we have concentrated on the fitting of the
SSCR curve obtained for the modified STARMAN-CUT 1 VCO (and the structurally identical CUT
1.1). The curve was obtained with the AAC turned off, since in the first case the VCO driving is
accomplished by controlling the final follower of the regulator, and in the second one (Fig. 4-5)
the tail has been completely detached by the amplitude loop.
The two experimental points that described the CUT 1 behavior before the FIB
modification, with the AAC inserted, can be now fitted. The point at 1.9 V is indeed matched by
the theoretical prevision, by PM-converting the 1.5 nA/ÖHz rms noise for the KTAIL measured at
405 mV amplitude; the tail noise is higher than the one of Fig. 4.10 of course, because no
external filtering was available for the gain stage of the AAC. When applied to the point at 2.4
V, the same technique grossly fails to match the measured data. This time, the AAC is on. Then,
as discussed in Chapter 3, depending on the peak detector working condition the noise on the tail
can undertake two values: 6.3 nA/ÖHz with rectifier on, and 117 nA/ÖHz with rectifier off. At
the simulated 660 mV of oscillation amplitude, when the optimistic first prediction is applied we
obtain about -87 dBc/Hz against the measured -76 dBc/Hz. On the other hand, the pessimistic
calculation gives about -61 dBc/Hz. A suitable pondering between the two spectral densities is to
be done. But how can we accomplish this?
Obviously, the .AC - and consequently the .NOISE - analysis cannot be performed during
the Eldo transient solving. The first attempt of obtaining the real noise at the tail is therefore the
linear weighing of the two noises, related to the respective duration of the rectifier on and off
intervals. To assess the time spans, the current flowing in the filtering capacitor (and also in the
rectifier junction) was simulated (Fig. 4-30):
107
Chapter 4
Importance of Indirect Stability
Osc-
53% 47%
Osc+
Peak
Fig. 4-30 Current waveforms flowing in the rectifier junctions and in the capacitor of the peak detector.
The duty cycle of the stage is about 47%.
Estimating with a 47% the time during which the capacitor is charged (rectifier on), while during
the remainder of the period the charge flows out of it (rectifier off, steady current discharge), the
final computation is:
117.0 nA / Hz
2
× 53% + 6.3 nA / Hz
× 47% = 85.3 nV /
2
Hz
(4.17)
Due to the duty cycle, the power average is only 3 dB under the pessimistic case. If this
noise amount is phase-converted by means of the KTAIL coefficient at 660 mV, a prediction of -64
dBc/Hz comes out. This largely overestimates the real phase noise. In the next Chapter 5 we will
show the in-depth study of the time-varying AAC noise, showing how it is dominated by the
peak detector design, and finding a couple of handy rules to estimate the spectral density of the
noise after the rectifier. From there to the tail, the rms noise transfer is linear and effortless. The
final prediction will be quite different from the oversimplified one attempted here; and, also in
this last case, the SSCR experimental data will be fully understood.
108
Chapter 5
Time-varying analysis of noise in the AAC servo-loop
Chapter 5
Time-varying analysis of noise
in the AAC servo-loop
The Automatic Amplitude Control (AAC) system is a popular servo-circuit for integrated VCOs.
Nevertheless, the noise contributed by the AAC can degrade the phase noise performance of the
oscillator. In this Chapter, the time-varying noise transfer of the peak detector is analyzed,
recognizing it as the critical noise source in the simple AAC loop taken as reference. The
investigation is carried out first theoretically, exploiting the properties of autocorrelations, then by
Matlab simulations. The fundamental property of conservation of GBWP for the peak detector is
found, and fast rules to predict the noise spectral density at the rectifier output are given.
Experimental validation is also presented at the end, performed by means of a discrete components
test board. The corrections applied by the new formulas to the first-order estimate of the SSCR,
when the AAC is inserted, prove instrumental to adjust the prediction and match the measured
phase noise.
5.1 Usefulness of the AAC loop
A
s discussed in the Introduction, the field of mobile communications is
experiencing the progressive success of cellular standards that are characterized
by more and more stringent requirements concerning the whole system: from the
input low-noise amplifier (for what pertains dynamic range) to the final power amplifier (battery
consumption issues). In particular, the toughest problems that threaten the compliance of fullyintegrated RF transceivers with these protocols are the strict co-channel and adjacent channel
interferers specifications (blockers), the fulfillment of which relies substantially onto the
oscillator performance [70].
In the following we will consider the complete STARMAN VCO structure, equipped with the
AAC (Automatic Amplitude Control) system. The presence of such a servo-circuit brings many
advantages to the oscillator:
1. it proves extremely useful to ensure a fast and reliable oscillation startup [39]. For instance,
in [71] some techniques to control the rise time of the oscillation envelope via the adoption
of AAC are proposed. Such a chance will be especially important in 3-G wireless FHSS
applications (third-generation Frequency Hopping Spread Spectrum), where the active
109
Chapter 5
Time-varying analysis of noise in the AAC servo-loop
VCO is to be periodically selected and turned on from an array of oscillators, each tuned to
a different carrier frequency [72],[73]
2. in any case of sudden change in supply voltage, or temperature variation, the AAC keeps
the oscillation amplitude stable - thus minimizing the switch delays (whose tolerances are
directly set forth by transmission standards, see [2]).
Nevertheless, every AAC circuitry features one potentially fatal drawback that may
impair its usefulness: it injects additive noise in the VCO, which can ultimately degrade the
phase stability up to an unacceptable extent.
VCC
Osc+
RL
CL
VTUNE
Osc-
VREF
CP
RP
Ampl
Ctrl
IBIAS
Fig. 5-1 Detailed schematic of the LC-tank VCO equipped with the AAC servo-circuit. Note the RPCP
pole of the peak detector and the RLCL dominant pole of the loop.
Fig. 5-1 presents one of the simplest schematic structures for an oscillation amplitude
regulator (other similar topologies can be found in [39],[74],[75]); the configuration will be
addressed for reference throughout the following. The peak detector circuit (rectifier and RPCP
filter) senses the oscillation amplitude A0, and drives the error amplifier stage. The signal is then
lowpass filtered by the RLCL loop pole, for both stability concerns and ripple cutoff purposes,
before controlling the current generator that biases the transconductor of the VCO.
This control system is particularly critical from the stability standpoint; in effect, high
loop gain is required for effectively rejecting the amplitude oscillation variations, but, on the
other hand, wide bandwidth is needed to extend the AM-controlling action of the loop
sufficiently far away from the carrier. Unless special structures are used, these AAC schemes can
be demonstrated to lead to non-robust control [76], because the link between ITAIL and the
oscillation envelope is rather indirect. Necessary conditions for achieving a safe system behavior
are studied for example in [77]. To keep the circuit reasonably simple, dominant pole
compensation is often adopted (RLCL pole in Fig. 5-1) hence the loop will feature a lowpass
profile with the first pole standing well below the other singularities. In current feedback
oscillators, AAC topologies with less critical stability requirements could be realized [78].
We analyze now the main noise transfer mechanisms into the AAC, pointing out the
crucial sources of disturbance and proposing some design rules to minimize them.
110
Chapter 5
Time-varying analysis of noise in the AAC servo-loop
5.2 Potential jeopardy of the AAC on SSCR performance
The theory developed in the previous Chapters 3 and 4 explains how the noise injected in
the VCO from the AAC can degrade the phase noise performance. At this point of the phase
noise analysis, we already know that the bias current noise contributed by the AAC does not
produce only amplitude modulation on the synthesizer: it also affects the oscillation frequency
through the AM-to-PM conversion (Chapter 3) and the indirect instability effects (Chapter 4).
The AAC can therefore worsen the figures commonly used to rate the phase stability of a
synthesizer, first of all the SSCR performance.
Fig. 5-2 shows a simplified scheme with the essentials of the whole system. Since the
controller tunes the VCO tail current, the noise coming from the AAC blocks (peak detector and
differential gain stage) gives rise to random fluctuations of the bias current. The RLCL dominant
pole filters the AAC noise sources, thus the noise injected on the oscillator current is lowpass
shaped. This noise is upconverted in AM by the mixing action of the switching transconductor,
then in PM via the KAM-PM.
Diff. stage
+
VREF
Ampl
Ctrl
VCO
-
A0
Peak
Detector
Fig. 5-2 Block diagram representation of the control system. A0 indicates the oscillation envelope. The
output noise of the peak detector is not compensated for by the loop, as it is embedded in the feedback
path.
The noise transfers that are taking place into the regulator loop and the main sources of
disturbance have been pointed out, the worst being the peak detector embedded in the feedback.
The inspection of the AAC block diagram in Fig. 5-2 is sufficient to assert that the most critical
nodes of the control loop (with respect to noise) are those which lay in the feedback path. This
happens since their contribution is not rejected by the loop gain.
As the AAC controls the oscillation amplitude, it also compensates for the noise sources
in its direct path; for instance, the ones in the VCO, that follows the differential stage. However,
the loop is totally ineffective against the output noise of the peak detector, because the block is
embedded in the feedback path drawn in the scheme; i.e., the fluctuations of the peak detector
and of VREF have the same transfer function towards the oscillator output. Therefore it becomes
important to characterize the noise behavior of the peak detector. This is highly non-trivial task,
given the time-varying nature of the noisy process involved. In the following, we will pursue a
theoretical analysis of the noise leading to a final prediction of the resulting spectrum of the
process.
111
Chapter 5
Time-varying analysis of noise in the AAC servo-loop
5.3 Peak detector as chief noise contributor
As previously outlined, the output noise of the peak detector is the only source in the
AAC that can significantly affect the SSCR performance of the VCO. The noise of the voltage
reference (VREF in Fig. 5-2) is equally important, but - as it lies out of the signal loop - it is much
easier to reduce.
The voltage noise of the peak detector at the input of the differential stage in Fig. 5-1 is
then to be evaluated. Fig. 5-3a represents an excerpt of the real peak detector found in the
regulator.
b)
a)
c)
1/gm
VCC
CP
CP
RP
RP
CP
En2
En2
RP
RP 1/gm
VEE
CP
En2
RP2
CP
RP
Fig. 5-3 Simplified passive circuit for peak detection, a). b) “on” state (rectifier active) and c) “off”
state (rectifier cut off) and respective Norton equivalents. The GBWP keeps constant in the two cases, at
the value 1/CP.
One single transistor has replaced the two bipolars making up the rectifier; the period of
the rectified wave is to be doubled. The discharge network was kept simple, adopting the
traditional R-C shunt.
Let us start by taking into account the thermal noise of the resistor RP. The input
resistance of the differential stage is considered much higher than RP, and neglected; it can be
anyway added in parallel to RP. The input current generator 4kT/RP forces a periodically varying
impedance, due to the switching behavior of the rectifier:
• at the oscillation peak one of the two transistors is on, Fig. 5-3a; it supplies current in both
the resistor and the capacitor, to replenish the latter with the charge spent during the “off”
state. The noise generator forces the parallel of CP, RP and gm-1: then the noise current finds
a path to escape the successive differential amplification. By Thévenin transformation of
the circuit it is apparent how the original noise is heavily attenuated, and passes on
practically unfiltered
• when the driving signal is lower both the transistors turn off, Fig. 5-3b, and the noise
current is injected in CP and RP. As the bipolar transistors get interdicted, the RPCP parallel
current noise sees only the path leading to the subsequent differential stage. This time the
112
En2
RP2
Chapter 5
Time-varying analysis of noise in the AAC servo-loop
noise is not attenuated, but it undergoes the lowpass filtering action of the RC time
constant (see Fig. 5-3c).
In the first case, the DC value of the impedance is RP||gm-1 with a pole (RP||gm-1 ⋅CP)-1; in
the second, the DC impedance raises to RP and the pole lowers to (RPCP)-1. Note that the
impedance gain times the bandwidth product, GBWP, always keeps constant to the value 1/CP in
the two cases.
Another source that affects the driving voltage of the differential amplifier is the shot
noise 2qICP of the rectifier. When one of the transistors is on, Fig. 5-3a, this noise is higher than
4kT/RP; whereas it vanishes when both transistors are off. The effect of this term is expected to
be negligible for low values of the input duty cycle (that is usually < 10%), but it could play a
role if this figure increases. Finally, the equivalent input noise of the differential stage is
negligible with respect to the two sources considered.
The time-varying nature of the transfer function for the considered noise sources makes it
quite difficult to evaluate their effects: the transfer depends on duty cycle and transconductance
gm of the rectifier, frequency of the input signal, etc. . However, for the AAC to work properly,
only one suitable sequence of the time constants involved in the transfer exist:
• the time constant of the rectifier in “on” state (τON) must be smaller than the period T of the
wave to detect, in order to track the envelope
• the time constant in “off” state (τOFF) must be instead longer than the period, to hold the
input peak
• an effective ripple-filtering lowpass stage must feature a time constant τLPF much longer
than the period, and possibly than the τOFF (for stability concerns also).
In the following, we will pursue a theoretical analysis of noise leading to a final
prediction of the switching process spectrum. The time constants of the AAC will be arranged as
indicated above, and depicted in Fig. 5-4.
τO N
T
τO F F
τL P F
Fig. 5-4 The usual arrangement of the time constants for a peak detector.
From the noise point of view the system can be considered linear and time-varying, according to
the argument reported in [14],[18].
5.4 Switched noise as time-varying stochastic process – The theory
The noise of the two sources identified above can be conveniently considered as white
noise, periodically amplitude modulated, followed by a lowpass filter that changes its pole
synchronously to the input waveform. In fact, the steady noise coming from RP enters a transfer
function having both varying gain and pole. ICP shot noise is even more complicated to handle
113
Chapter 5
Time-varying analysis of noise in the AAC servo-loop
since it switches between zero and the case represented in Fig. 5-5a, before filtering occurs; its
effect will be briefly outlined in the following Paragraph 5.8 .
2qICP
CP RP
4kT
RP
CP RP
4kT
RP
b)
a)
Fig. 5-5
Peak detector operation detail: a) when one of the transistors is on, the two main noise
sources are shunted by gm-1; b) when both transistors are off, the ICP shot noise vanishes and the noise
reaching the differential stage is 4kT/RP.
5.4.1 The background: weighing function and autocorrelation
The classical spectral theory approach to the noise relies substantially on autocorrelation
concept. The role of autocorrelation function in transferring non-deterministic signals through
linear networks can be considered as important as the role that impulse response plays for
deterministic signals. Thus, the gap from time-invariant to time-varying behavior of a system fed
with noise, is bridged with less effort if we can refer to the expression of its autocorrelation
function.
Given a stochastic process y(t), two definitions can be given for its autocorrelation:
• ensemble autocorrelation, calculated over a representative set of different samples:
Ryy ( t0 , t1 ) = y( t0 ) ⋅ y( t1 ) =
+∞+∞
ò òy
y ⋅ py A y B ( t0 , t1 ) ⋅ dy A dyB
A B
(5.1)
−∞−∞
• time autocorrelation, calculated over one single sample of the process:
+T
1
⋅ yT ( t ) yT ( t1 − t0 + t ) ⋅ dt
Kyy ( t1 − t0 ) = lim
T → +∞ 2 T ò
−T
(5.2)
It is well known that the ensemble average of (5.2), K yy (t1 − t 0 ) , is equal to the time
average of Eq. (5.1), R yy (t 0 , t1 ) , when the process y(t) is ergodic (Birkhoff’s theorem, [79]).
The process y(t) exiting a linear block whose impulse response is h(t) can be determined from
the entering stationary process, indicated by x(t), through the relation:
114
Chapter 5
Time-varying analysis of noise in the AAC servo-loop
Ryy ( t1 − t0 ) = Rxx ( t1 − t0 ) * Khh ( t1 − t0 )
(5.3)
To obtain the output y(t) from the input noise x(t) we must consider that the system is
switching. Let us customize the analysis for the process described in Fig. 5-3. The impulse
response h(t1-t0) used in time-invariant systems is to be replaced by its time varying counterpart,
the weighing function w(t1,t0). The former depends only on the difference between the occurring
time t0 of an impulse and the time t1 to which the output is observed, whereas the latter depends
on both times, and could be completely different for the time couples (t1,t0) and (t1’,t0’) even if
t1-t0 = t1’-t0’ . The output dependence on the input via the weighing function becomes:
y (t1 ) =
∞
ò w(t , α ) x(α ) dα
(5.4)
1
−∞
In the present case, if one considers the noise due to the resistor as composed by random
pulses (as stated by Campbell’s theorem) then:
• a current impulse can arise when the peak detector is “on”, being strongly attenuated and
promptly forgotten (i.e. conveyed into the emitter);
• or, it can arise when peak detector is in “off” state, and be kept a long time without
attenuation.
Some profiles of the weighing functions relative to peak detector, for different couples of
times (t1,t0), are shown in Fig. 5-6:
a)
c)
w(t0,t1 )
w(t0,t1 )
t0
t1
t0 t1
b)
d)
w(t0,t1 )
w(t0,t1 )
t0
t1
t0
t1
Fig. 5-6 Time-varying nature of the weighing function: the time occurrence of the impulse determines
the exponential slope it is assigned. a-d) cover all the possible cases.
The transfer of the original noise x(t) through the linear time-varying system described by
w(t1,t0) functions can be now translated in terms of autocorrelation. We can write:
115
Chapter 5
Time-varying analysis of noise in the AAC servo-loop
Ryy ( t0 , t1 ) = y( t0 ) ⋅ y( t1 ) =
+∞+∞
ò ò x(α )w( t ,α ) ⋅ x(β )w( t ,β ) ⋅ dαdβ =
0
1
−∞−∞
=
+∞+∞
ò ò x(α )x( β ) ⋅ w( t ,α )w( t ,β ) ⋅ dαdβ
0
(5.5)
1
−∞−∞
but, since we are dealing with stationary white thermal noise in input:
x(α ) x( β ) = x(α ) x(α + γ ) = Rxx (γ )
where γ = β − α
(5.6)
Let us take now a stationary, white input noise with spectral density Sxx. The input
autocorrelation is:
R xx (γ ) = S xx ⋅ δ (γ )
(5.7)
From the equations (5.5)-(5.7) it is finally obtained [21]:
+∞
R yy (t 0 , t1 ) = S xx ⋅ ò w(t 0 , α )w(t1 , α ) ⋅ dα = S xx ⋅ K w0 w1 (0)
(5.8)
−∞
As expected, Eq. (5.8) highlights that the sought autocorrelation function depends on
both t0 and t1. Instead of manipulating 2-dimensional autocorrelations and spectra, the analysis
can be simplified by exploiting the properties of lowpass filtering. In fact, by definition a timevarying process cannot be ergodic; but a tightly lowpass filtered time-varying process recovers
the ergodicity [79]. In fact, by performing a long time average of Ryy(t1,t0 ) it can be derived that:
+∞
yT ( t ) yT ( t 1 − t 0 + t )
yT ( t ) yT (t1 − t0 + t )
dt =
dt
=
lim
ò
ò
T →+∞
T → +∞
2T
2T
−∞
−∞
K yy (t1 − t0 ) = lim
+∞
= lim
T →+∞
+∞
ò
−∞
Ry T y T ( t ,t1 − t0 + t )
2T
(5.9)
dt = Ryy ( t1 ,t0 )
In other words, provided the time constant of the filter encompasses some periods of the
switching noise, we have again Kyy(t1 −t0 ) = Ryy(t1,t0 ) ; i.e., the couple (t0,t1) reduces to the time
difference t1-t0. The 1-D autocorrelation is now suitable for Fourier transformation, and the
computed noise power spectrum can be accounted for in the phase noise evaluation of the VCO.
In the actual AAC, the narrow loop filter RLCL after the peak detector performs this time
averaging of the switching noise [80]. The RLCL filter action is equivalent to the cascade of two
distinct effects: besides performing time-domain average, it obviously introduces a pole in the
spectrum profile. However, in order to expunge unessential effects from the analysis, the sole
time average will be considered in the next Paragraphs. The spectra corrected by introducing the
cutoff of the additional pole will be presented later, in Paragraph 5.7 .
116
Chapter 5
Time-varying analysis of noise in the AAC servo-loop
5.4.2 Application of the concepts in the case of peak detector
To better clarify the steps that lead to figure out the spectrum of the noise, let us try to
predict the 2-dimensional shape of the ensemble autocorrelation function Ryy(t0,t1) for the thermal
noise of RP. Despite the case considered in the following is an oversimplified one, other
simulated situations will be easily understood by extending the results drawn.
First of all, the process y(t) is recognized to be cyclostationary. The simplest case occurs
when the “on” time constant of the peak detector approaches zero: this implies an almost
complete loss of the RPCP filter memory, thus w(α,t0) becomes a short exponential decay with
negligible area. In such a case, one can concentrate onto what happens within a single period, i.e.
for (t0,t1) ∈ (0,T)×(0,T). Given a duty cycle of the detector of 50% (the most convenient for
representation reasons), the weighing functions can be represented as in Figs. 5-7a..f. The
corresponding 2-D autocorrelation is computed as follows:
1) when |t1-t0| > TON = 50%⋅T, the product of w(α,t) under the (5) integral is zero (Fig. 5-7a,
dashed area in Fig. 5-7g)
2) moving along the main diagonal of the graph means t0 = t1, i.e. the autocorrelation in (5) is
proportional to the integral of w(α,t0)2:
• in “off” state, from 0 to 50%⋅T, Ryy(t0,t0) rises as the area of a truncated exponential:
T
R yy (t 0 , t 0 ) ∝ S xx ⋅ ò e
2
α − t0
τ OFF
u (t 0 − α )d α = S xx
0
2 t0
−
æ
τ OFF
ç
⋅ 1− e
ç
è
ö
÷
÷
ø
(5.10)
then the rise shows negative concavity (Fig. 5-7b, and the diagonal locus of maxima in
Fig. 5-7g)
• in “on” state, from 50%⋅T to T, Ryy(t0,t0) is constant and equal to the variance of the
incoming white current noise, attenuated by the effect of gm-1 (Fig. 5-7c, and the low
diagonal relief in Fig. 5-7g)
3) fixing one of the time variables, say t0 = T/4:
• Ryy (t0 ,t1 ) rises until t1 < t0 , since the two weighing functions tend to overlap completely
(Fig. 5-7d)
• it falls exponentially for t1 > t0 , because the functions progressively disoverlap (Fig. 57e).
In both intervals the concavities are directed upwards (as represented by the dotted line
embedded in Fig. 5-7g)
4) outside the square (t0,t1) ∈ (0,50%⋅T)×(0,50%⋅T) the autocorrelation is zero, since one of
the weighing functions is surely the short exponential decay (Fig. 5-7f, and gray plane
surface in Fig. 5-7g). If the rush decay is modeled with a Dirac delta, one of the functions
may be expressed in the form w(α,ti) = δ(t I-α); in such condition, the autocorrelation does
not vanish only when w(α,tj) = w(α,ti) = δ(tI-α):
+∞
R yy ( t 0 , t 1 ) = K yy ( t 1 − t 0 ) = S x ⋅ ò w(α , t 0 ) w(α , t 1 )dα =
−∞
+∞
= S x ⋅ ò δ (t 0 − α ) w(t 1 ,α )dα = 0
(5.11)
for t 0 ≠ t 1
−∞
117
Chapter 5
Time-varying analysis of noise in the AAC servo-loop
5) obviously the diagram is symmetrical with respect to the +45° diagonal of the horizontal
plane, because Ryy ( t0 ,t1 ) = Ryy ( t1 ,t0 ) .
t0= t1
b)
t0 t1
Ryy(t0 ,t1)
T/2
0
d)
T
t0
t1
t1
T/4
t1 t0
e)
T/2
T
t0
t1 -t0= const
g)
t0
f)
t1
t0= t1
c)
Fig. 5-7 Derivation of the 2-D autocorrelation. The plots a-f) depict the possible permutations in the
relative positions of the weighing functions; g) is the theoretical final profile of Ryy(t0,t1) in the ideal case.
The resulting 3-D graph of the ensemble autocorrelation is to be periodically reproduced
over the main diagonal of (t0,t1) plane, as cyclostationarity requires (Fig. 5-8).
To resume the 1-D information, time average must be applied; the smoothing must be
performed over the main diagonal of the Cartesian plane. There are at least three reasons that
support this consideration. First, the resulting function is dependent only from the time
difference t1-t0, then it will be located onto the -45° diagonal of (t0,t1) plane; the direction in
which the averaging must be carried out is perpendicular to this one, and consequently it ought
to be performed along the main diagonal of the same plane. Moreover, it seems to be intuitive
that the central value of autocorrelation, proportional to the power of the process, encompasses
both the power of filtered and white noise; and this latter one is found exclusively onto the
diagonal. Last, two separate 1-dimensional averages, performed along t0 and t1 axes, end up in
being equivalent to the proposed diagonal procedure. The illustration of the average procedure is
reported in Fig. 5-8.
118
a)
Chapter 5
Time-varying analysis of noise in the AAC servo-loop
Ryy(t0,t1 )
0
T
2T
t1
T
2T
t0
t1-t0= const
Ryy(t0 ,t1 )
0
Fig. 5-8 The suitable direction for the time averaging of Ryy(t0,t1) on the (t0,t1) plane.
Intuitively, the final spectrum is expected to be a mixture of a lowpass pole shape and a
lower white component.
5.4.3 Further refinements of the analysis
The presented scenario was an oversimplified one. In reality, the “on” interval implies a
fast but not instantaneous pole response, and the duty cycle of the switching wave is of the order
of less than 10% for typical peak detectors.
The first correction implies some modifications to the graph shown in Fig. 5-7. All the
vertical surfaces become exponential decays, implying for example an enlargement of the spiky
relief (the noise is not perfectly white), a smoother joint between the relief and the subsequent
exponential rise, and an invasion of the plane also out of the central stripe |t1-t0| < d.c.⋅T (there is
residual correlation for instants of time in and out of the “on” interval). The boundary zone of the
graph on the axes is not tapered to zero, but it tends instead to approach the height of the relief;
this effect is especially striking in Fig. 5-13.
The second correction presents a fundamental implication: if the “on” time is short
enough with respect to “on” time constant, the memory of the filter can persist well over one
period. Thus the surface reaches far greater breadth, and the locus of maxima on +45° diagonal
tends to become a straight line (just with wavelets at every period). For instance, in the case of
duty cycle tending to 0%, the “off” filtering characteristic is practically unperturbed and the
Ryy(t0,t1) autocorrelation will become equal to a 3-D double-sided exponential shape, Fig. 5-9b.
The autocorrelation does not vanish even for hundreds of periods, with the typical parameters of
real peak detectors; it goes without saying that the resulting power spectrum will reproduce in
toto the lowpass transfer function of the RC slow pole, in this particular case.
119
Chapter 5
Time-varying analysis of noise in the AAC servo-loop
Ryy(t0,t1 )
Ryy(t0,t1)
t1
0
T
t1
T
T
t0
T
0
2T
2T
t0
a)
b)
Fig. 5-9
The periodicity of the autocorrelation on the 45° diagonal, a); 2-D view of the classical
double-exponential decay profile of the autocorrelation of the single-pole lowpass filter, b).
The insight acquired thanks to these theoretical considerations will be instrumental to
understand more in depth the results of both simulations and measurements.
5.5 Behavioral simulations of noise in the peak detector
5.5.1 Switched-noise modeling technique
The first check of the noise characteristics discovered in the antecedent analysis of the
thermal noise from RP could be performed by behavioral simulation. In the present case, a very
simple setup may be arranged as follows (see also Fig. 5-10):
1) a white noise generator
2) a single pole LPF transfer function, into which both the time constant and the gain magnitude
can be changed in real-time.
Switch
synchronization
Scope
[time,WGN]
MATLAB
generated noise
1
2 πPole .s+1
[Filtered
WGN]
to MATLAB
environment
Fig. 5-10
A principle scheme for the Matlab-Simulink simulation of white noise filtered by the
switching peak detector.
The simulation environment was composed by Matlab and Simulink, the Matlab toolbox
suitable for step-by-step continuous- and sampled-system simulation. In particular, since the
main difficulty of the simulation analysis resides in its variability over time, we must control the
flow of the program execution - especially at switching instants. This was accomplished by
breaking up the Simulink run activity in as many sessions as the “on” and “off” intervals
comprised within the observation time are. Every run-&-stop session was organized in this way:
120
Chapter 5
Time-varying analysis of noise in the AAC servo-loop
1) from Matlab, a white noise sequence of length TON or TOFF is generated; the pseudo-random
seed of the noise generator is re-initialized at every occurrence, to assure that the incoming
sequences are scrambled as much as possible
2) the sequence is fed to Simulink. Before launching the run, the two global variables
Attenuation and Pole are set according to the next interval being “on” or “off”. For proper
simulation of the filter, its state at the end of a session must be recorded and restored at the
start of the next run, so as to generate a continuous, well-behaved output transition
3) the filtered noise is saved in Matlab environment each time, and appended to previous
outputs.
It is to be remarked that simpler solutions, such as switching the noise between two
distinct filtering paths (fast and attenuating for “on” intervals, slow and without attenuation in
the “off” state) are not trustworthy reproductions of the real working of peak detector. In fact the
slower filtering path keeps its memory between a cycle and the next one, even if the time
constant of the faster path is zero. On the contrary, from Fig. 5-6 we learn that the actual RC
filter will irretrievably lose its memory in this situation.
5.5.2 The numerical procedure
The choice of the simulation parameters has been made so as to minimize computation
run times, while allowing a clear identification of the different parts of the 2-D autocorrelation
shape. The set of values was tailored so as to comply with the realization of a discrete test-board.
Namely:
• period of the rectified wave: T = 1 µs (fIN = 1 MHz)
• RPCP “off” time constant: τOFF = 1.6 µs (or slow pole pOFF = 100 kHz; RP = 10 kΩ, CP =
160 pF)
• RPCP “on” time constant: τON = 100 ns (or fast pole pON = 1.6 MHz; gm-1 = 625 Ω).
Impedance gains RP = 10 kΩ and gm-1 = 625 Ω are needed to keep the gain-bandwidth product
GBWP equal to 100 kHz in both cases.
A snapshot of the noise as read at the output is reported in Fig. 5-11; for sake of clarity,
in input d.c. = 50% was chosen. The fast exponential crumble of the response and the different
coherence of “on” versus ”off” filtered noise can be immediately recognized.
Fig. 5-11 2-periods excerpt of the noise of RP, generated with Simulink (d.c. = 50%): bursts are the
slow noise without scaling, whereas white attenuated noise occupies the other timeslots. The high values
are due to the successive amplifications, already taken into account.
121
Chapter 5
Time-varying analysis of noise in the AAC servo-loop
We are now capable of generating a stochastic process y(t) of filtered noise, ready for the
application of the definition of ensemble autocorrelation written in (5.1). Each element of the
vector Y[i] obtained from Simulink contains just y(ti); the computation of the formula reduces
then to a column-by-row product of the output noise times itself:
y ( t 0 ) ⋅ y ( t 1 ) = Y [i ] ⋅ Y [ j ]
(5.12)
In Fig. 5-12 the 2-D surface relative to one single realization is reported. The time axes
and the vertical values of the autocorrelation are relative to the parameters listed above:
Fig. 5-12 Single-sample autocorrelation computed for d.c. = 50%.
The surface is rather different from the one foreseen in Fig. 5-7 by following the
theoretical approach; only the position of the relief and the lateral flat areas coincide with the
expected one. Anyway, Ryy(t0,t1) is the average of the 2-dimensional matrices of autocorrelation
obtained in independent samples. Each example illustrated in this Chapter comprises the average
on 1000 samples; the different random seed chosen for every run guarantees their statistical
independence.
Fig. 5-13 shows the ensemble average Ryy(t0,t1) taken over 1000 statistically independent
realizations of the process: this time, the simulated 3-D autocorrelation profile resembles very
closely the theoretical prediction.
Fig. 5-13 Autocorrelation averaged over 1000 statistically independent simulation trials (after 90°
rotation).
122
Chapter 5
Time-varying analysis of noise in the AAC servo-loop
Once Ryy(t0,t1) is computed, it must be averaged over time in order to generate a
statistically significant one-variable autocorrelation, or K yy ( t1 − t0 ) = Ryy (t0 ,t1 ) ; this ultimate
function is Fourier-transformed to estimate the power spectrum. The entire numerical procedure
is intuitively outlined in Fig. 5-14. The values on the axes no longer refer to the parameters
chosen before, and the flowchart shall be considered only as a procedure guideline.
×
+
+
+
…
N
Fig. 5-14 An overall review of the numerical procedure – from the generated noise stream to the final
spectra.
The choice of a right time step for the algorithm that solves the differential equations
describing our system is of chief importance, among other simulation issues. Capital attention
must be paid to the time-variance of the process; in fact, to gather information about the low
frequencies of the spectrum we ought to observe many periods of the process, since the observed
time Tobs gives:
f min =
1
1
=
Tobs n ⋅ Tperiod
(5.13)
123
Chapter 5
Time-varying analysis of noise in the AAC servo-loop
The practice of considering an integer number of periods is suggested directly by the
inherent circular nature of FFT. Let us say N the number of collected points per single
realization: the process in Fig. 5-14 involves large matrices of N×N size, hence memory and time
computation reasons limit N to 1024 points, at most. Thus, by enlarging the observation interval,
we risk undersampling the fast “on” transients, consequently incurring in “aliasing” effects.
The chosen pole pOFF = 100 kHz is not as low as the one implemented on the test board, but lets
us observe as few as 16 periods (16 µs, hence fmin = 62.5 kHz) and is still visible in the spectrum.
Spanning 1024 points in 16 periods means 64 points per period; even with a duty cycle around
10% or lower, at least 5 or 6 points surely fall into “on” intervals: this proved to be sufficient for
a correct spectral estimate.
In the following we consider the output spectra obtained with different values of the input
duty cycle d.c., and of the gm of the rectifier. Of course the behavior of the peak detector depends
on many circuit parameters, but for clarity only one of them is varied at a time. For example, as
different d.c. values imply variations in the ICP charging CP, gm should vary in turn; ICP has been
instead supposed to be constant. The designer can easily accomplish this by adopting a current
generator in place of RP, or suitably changing the voltage drop on RP through voltage translation
techniques.
5.6 Crosscheck of the theory through simulations
5.6.1 Duty cycle modulation
In these simulations the duty cycle was progressively risen from 1% to 99%. The rms
value of the white current noise injected in the RPCP filter was 200 nA/√Hz, in order to get -54
dBV2/Hz of noise power density when the detector is “off”; when in “on“ state, the attenuation
drops the level down to -78 dBV2/Hz. These levels are directly comparable with the ones
reported in Paragraph 5.10 that concern the peak detector test board.
Figs. 5-15a..c report three different Ryy(t0,t1) plots; they can be explained by reminding
the conclusions drawn in Paragraph 5.4 . The first graph is relative to d.c. = 1%: it provides the
numerical proof of what foreseen above, since it resembles very closely the linear time-invariant
autocorrelation function of a simple R-C filter. When viewed along +45° diagonal the surface
reveals the classical double-exponential shape. The second diagram shows d.c. = 50%: as
expected, it behaves like its theoretical counterpart that was considered in Fig. 5-8. The maxima
reached by the peaks at every period have decreased in magnitude, with respect to the first graph,
because the overlap of the weighing functions is now limited to half a period. The third 3-D plot
refers to d.c = 99%: the autocorrelation appears almost identical to the one typical of a fast
filtering pole, similar to a sort of “blade”.
124
Chapter 5
Time-varying analysis of noise in the AAC servo-loop
a)
b)
c)
Fig. 5-15 The filtered autocorrelation considered over 16 periods of the process. The views encompass
+45° and –45° angles of the plane, and are relative to a) d.c. = 99% b) d.c. = 50% and c) d.c. = 1%.
Fig. 5-16 shows the autocorrelations Ryy ( t0 ,t1 ) obtained. All the shapes are similar to
bilateral exponential decays, the classical autocorrelation of the single-pole lowpass filter.
Despite this seems to be obvious for the curves corresponding to very low or very high duty
cycles, it is a surprise for the intermediate cases. The peak detector analysis led to recognize that
GBWP holds constant in “on” and “off” states; but the time-varying characteristics of noise
seemed to prevent this property from trivially holding in the output noise spectra.
125
Chapter 5
Time-varying analysis of noise in the AAC servo-loop
1%
3%
10%
30%
99%
Fig. 5-16
The simulated autocorrelation shrinking at increasing duty cycles. Despite relative to
switched noise, they closely follow the classical double-exponential decay.
Ensemble and time averages have normalized almost every feature of the original
randomness of the processes from which the curves have been extracted. The statistical
confidence decreases as t1-t0 becomes bigger, because the averaged number of elements
diminishes linearly, moving towards the extreme diagonals of Ryy(t1,t0). To reduce these
uncertainties, averages were computed via the formula
N
K ( t1 − t0 ) = Ryy ( t0 , t1 ) =
å R (t , t )
yy
0
i =1
1 t − t =τ
1
0
(5.14)
N
The expression gives biased autocorrelation estimation, but improves the confidence of the
results - since the autocorrelation gets smoothed by triangular windowing, as is well known from
the periodogram spectral analysis.
Fig. 5-17 depicts the power spectra computed from the simulations for different duty
cycles. It shall be remarked that the spectra are obtained after the sole time averaging of
Ryy(t0,t1); hence, they could not be found at the output of a real lowpass filter, that would
introduce its pole. All of the spectra show indeed a constant gain-bandwidth product; this is one
of the core findings of this analysis. Given the impulse response of a lowpass filter with gain k⋅τ
and pole 1/τ, and its Fourier transform magnitude:
h (t ) = k ⋅ e
−
t
τ
F
→
H (ω ) =
k
1τ
2
+ω2
(5.15)
It is apparent that, by keeping k constant, the area of H(ω) also keeps, and a fixed GBWP
is maintained; so happens of course for |H(ω)|2. Fig. 5-17 indicates that GBWP keeps constant
when switching between two processes with equal GBWP. Although the autocorrelation profiles
in Fig. 5-16 derive from complicated filtering, it can be stated that their areas and decay time
constants inherit the building blocks’ original property, maintaining a fixed value for GBWP.
126
Chapter 5
Time-varying analysis of noise in the AAC servo-loop
1%
3%
10%
30%
70%
99%
Fig. 5-17 Simulated noise power density spectra for increasing duty cycles. The 0% d.c. level has been
set to –54 dBV2/Hz, for compliance with the test board discussed at the end of the Chapter.
5.6.2 Peak detector gm modulation
Other simulations investigated the behavior of the peak detector when the
transconductance gm of the bipolar rectifier is changed, e.g. via the adoption of a current
generator for CP discharge, or RP voltage drop tailoring with a suitable translator. The numeric
setup uses a realistic duty cycle of 10%; the effects due to the increase in gm are modeled by
means of gain shrinking and band widening. Fig. 5-18 shows the resulting power spectra.
0.05 mA/V
1 mA/V
10 mA/V
20 mA/V
Fig. 5-18 Simulated noise power density spectra for increasing gm. For gm-1 = 625 Ω (gm = 1.6 mA/V) a
level of –62 dBV2/Hz is expected, since d.c.= 10% (see Fig. 5-17).
A major limitation encountered in this new series of runs laid in some convergence
difficulties of the solving algorithm, especially when the frequency of the fast filtering pole was
increased. For the sake of comparability with preceding diagrams all the parameters have been
127
Chapter 5
Time-varying analysis of noise in the AAC servo-loop
anyway kept unchanged, and with the present setup the maximum pole frequency achievable was
20 MHz.
Since gm separately affects the attenuation factor (gm-1) and the position of the pole
(gm/CP), but still leaves GBWP unaffected, the resulting spectra are of the same type illustrated
in Fig. 5-17. As expected, noise power spectra feature a constant GBWP. For the upper curve
τON ≈ τOFF = 1.6 µs; an almost ideal lowpass filtering is thus performed, and the spectrum
features the usual -20 dB/dec downfall beyond 100 kHz. The two lowest curves refer to very fast
“on” filtering, with τON of 16 ns and 8 ns. By taking into account that TON is 100 ns, or 6.25 and
12.5 times τON respectively, it is easy to understand how the memory of the filter is completely
lost in the first case, and even overkilled in the second one. The two noise spectra are
consequently nearly identical.
5.7 Correction for real averaging filters – An additional pole
The previous results are easily adjusted to take into account the effect of the dominant
pole of the AAC loop: the spectra depicted so far must include the new singularity. This has been
verified by simulation: a time-invariant lowpass filter has been inserted in cascade to the
switching blocks that generate the time-varying noise. The pole must be slower than 1/τOFF =
100 kHz: 10 kHz was set for this crosscheck.
The plot in Fig. 5-19 illustrates the noise power spectra with duty cycle variations. It
confirms that the lowpass filter action can be decomposed into the cascade of two separate
effects: the time average of Ryy(t0,t1) and the 10 kHz spectrum cutoff.
1%
3%
10%
50%
70%
99%
Fig. 5-19 The noise spectra corrected with the addition of the lowpass filter pole at 10 kHz. A constant
GBW2P locus is invariably reached.
It is worth observing that the crossing between the two lines at -20 and -40 dB/dec
follows a constant GBW2P slope; the mathematical proof for this rule is effortless. For, once the
poles of the peak detector and of the successive filter are known, the curve locus is uniquely
determined: the duty cycle of the rectifier will finally set the low-frequency noise level.
128
Chapter 5
Time-varying analysis of noise in the AAC servo-loop
5.8 A simple rule for noise density vs. duty cycle prediction
The noise of the AAC eventually becomes bias noise for the VCO, that is upconverted
around the carrier. The low-frequency region of the previously analyzed spectra must be
lowered, since it contributes to limit the phase noise performance of the oscillator; in fact, phase
noise is usually rated at small frequency offsets from the carrier. Let us investigate the salient
characteristics of the spectra behavior, and try to find out a rationale that allows for a reasonably
simple prediction.
First and foremost, the transition from “off” to “on” state occurs in nearly exponential
manner. Slight reductions of duty cycle imply dramatic narrowing and lowering of Ryy (t0 ,t1 )
when d.c. goes from 1% to 10% (Fig. 5-16) - the peak drops from 0.78 V2 to 0.44 V2, or 43% thereafter the sensitivity to d.c. falls progressively: eventually, from 70% to 99% the peak drops
from 0.09 V2 to 0.05 V2, or only 44%. A semi-logarithmic plot of the transition can be found in
Fig. 5-20:
Fig. 5-20 The peaks of the autocorrelation in Fig. 5-16 [Kyy(0)] decay with the d.c., according to an
exponential rule with equivalent time constant τEQ ≈ 52 ns.
The straight line reflects the phenomenon of exponential memory loss during TON. The
initial sudden decay of maxima is explained by the reduction in overlapped area of w(α,t),
further worsened by another concurrent effect: the time average routine finds less and less nonzero data to sum, as d.c. increases, because Ryy(t1,t0) tends to become a blade everywhere. Fig. 520 lets us estimate the time constant τEQ of decay. In fact, taking for example the values at 1%
and 10% we get:
−
Peak10%
=e
Peak1%
T ⋅(10% −1% )
Teq
≈ 0.44 / 0.78 Þ τ EQ ≈ 52 ns
(5.16)
which is very close to the set τON = 100 ns.
These eyeball observations about the similarity of the curve with the exponential case
raise suspicion about regularity in the power spectra evolution, but do not provide information on
the spectra level. Moreover, from a more formal standpoint the sequence of autocorrelation
functions proposed in Fig. 5-16 does not seem to follow a manifest rule. The physical knowledge
of the peak detector circuit led us to recognize that GBWP keeps constant in both the “on” and
129
Chapter 5
Time-varying analysis of noise in the AAC servo-loop
“off” working phases; but the non-linear time-varying nature of switching process prevents this
property from being applied directly to output noise power spectra.
The question is whether conservation of constant GBWP holds when mixing together two
processes with equal GBW, with variable duty cycle: the analysis giving us Fig. 5-17 indicates
that this is effectively the case. Although the autocorrelation profiles in Fig. 5-16 derive from a
very complex filtering mechanism, we can conclude that their equivalent “decay time constants”
and their areas inherit their building blocks’ original property, keeping a fixed value for GBWP.
Finding a mathematical relation to link the peak detector parameters and the flat noise levels of
Figs. 5-17 and 5-18 is not straightforward. Note in fact that the flat zone of the spectrum with
50% duty cycle is about –69 dBV2/Hz; by simply compounding “on” and “off” noise powers,
weighted with their half-period spans, we get instead –54–3 = –57 dBV2/Hz ! A first order noise
estimation can be found by computing the average area of the impulse response. By squaring it,
and multiplying for the noise in input, the area of Kyy(τ) (i.e., Syy(0)) is obtained.
Regarding RP noise, the impulse response looks like a sequence of exponential decays, as
reported in the Appendix C. The spectrum magnitude computation eventually leads to:
S yy (0)
RP
=
1
2
2τ OFF
éτ OFF (1 − α )(1 + β ) + τ ON (1 − β )(1 + α ) ù
ê
ú
1 − αβ
ë
û
2
(5.17)
−T τ
where α = e −TOFF τ OFF and β = e ON ON ; the final result is to be multiplied by the equivalent
voltage noise injected in input.
The noise of ICP can be approximated by weighing the area of impulse responses
generated only during “on” intervals, with the span of TON:
S yy (0) I
CP
d .c. éτ (1 − α )β + τ ON (1 − β )ù
= 2 ê OFF
ú
τ OFF ë
1 − αβ
û
2
(5.18)
Multiplying by the equivalent voltage noise given by the rectifier (see below) the output is
found.
a)
130
Chapter 5
Time-varying analysis of noise in the AAC servo-loop
b)
Fig. 5-21 a) Comparison between the simulation results (triangles - RP noise, circles - ICP shot noise)
and the predictions given by the approximated formulas (solid line – RP, dashed line – ICP). As expected,
at high duty cycles ICP plays a major role. b) Comparison of the total peak detector noise simulated
(triangles) and estimated with the rule of thumb (solid line); a worst-case error as low as 1.5 dB is
achieved.
In Fig. 5-21a the RP noise levels at low frequency found with the previous simulations
(see Fig. 5-17) are compared with the estimation given by (5.17). The highest error is less than
2.5 dB and occurs for high values of the duty cycle, while the prediction is almost errorless for
duty cycles < 20%.
The analysis of ICP shot noise is more complex, because the input noise is also switched,
together with the RPCP filter. The shot noise contribution has been simulated starting from the
known case of 100% d.c. . Indicating by VRp the voltage drop across RP, ICP = VRp/RP in this
simple condition; the usual expression for the “on” noise at the output, 2qICP⋅gm-2, can be
rewritten as 2(kT/Vth)(VRp/RP)⋅gm-2, against the 4kT/RP⋅gm-2 thermal noise term. The ratio between
the two contributions is therefore VRp/(2Vth). By choosing gm-1 = 625 Ω as done in Paragraph
5.5.2, ICP is set to 40 µA, or VRp = 0.4 V; hence, when the peak detector is “on” the shot noise is
9 dB higher than its thermal counterpart (-69 dBV2/Hz at 100% d.c. in Fig. 5-21a). ICP was then
kept constant over the entire d.c. sweep. The ICP noise predictions of (5.18), dashed line,
compare less satisfactorily with the relative simulations. To keep our estimation simple, we
ought to neglect the effect of noise that is still decaying inside the filter during TOFF, when the
input noise goes to zero; especially at low duty cycles, such an effect is instead remarkable. The
simulated behavior is anyway approximated with acceptable accuracy.
The overall output noise and the sum of the estimations are compared in Fig. 5-21b: the
worst-case error is 1.5 dB. Thus the (5.17) and (5.18) provide simple while accurate formulas for
predicting the low frequency noise power density after the peak detector.
5.9 Setup of discrete-components test board
Experimental confirmation for the noise transfer has been achieved by designing a test
board, inclusive of a peak detector and a noise amplifier stage. The rectifier is implemented with
a simple R-C parallel connection, and one bipolar transistor; the schematic is represented in Fig.
5-22. The low testing frequency chosen (1 MHz, as in simulation) permits to neglect any
131
Chapter 5
Time-varying analysis of noise in the AAC servo-loop
impedance matching problem; the driving signal is fed directly to the base of the bipolar rectifier
Q1, while the output is available at one collector of the differential amplifier. Moreover,
crosstalk between the metal traces does not represent a critical concern, and all connectors and
cables do not have to be SMA kind, but BNC standard. Of course we cannot take advantage of
differential output, because these low frequencies do not allow resorting to baluns; but the direct
injection of noise has easily permitted to outweigh this difficulty.
VCC
2.2 kΩ
Q1
to FFT
1 MΩ
Osc. In
100 kΩ
Q2 Q3
Ext. noise
20 kΩ
47 nF
10 kΩ
47 µF
15 kΩ
VRC
Fig. 5-22 Circuit schematic of the discrete-components test board. The power supply was set to +12/-6
V. At every measurement, the differential stage was balanced by means of the trimmer on the left.
The final amplifier was originally intended to drive the NSC660A-FFT Spectrum
Analyzer (by Nicolet Scientific Corporation, 1980) presenting a 100 kΩ input impedance; hence
the driving collector needed no buffer stage after it. Because of the recognition of sensibility
limitations that made this first trial not successful, we resorted to Hewlett-Packard
HP4195A Network and Spectrum Analyzer, which can boast a -130 dB sensibility scale floor,
but features a standard 50 Ω input terminal. Tektronix 2467B oscilloscope postponed to the
differential amplifier acted as buffering stage. The oscilloscope loads the board with 1 MΩ input
(notice in fact the balancing resistor added to the other collector of differential stage) and drives
the spectrum analyzer through a 50 Ω output; it can also reinforce the input signals with an
amplification reaching a maximum gain of 14 dB. Unfortunately, it inserts a series of spurs near
1 kHz, i.e. in a frequency interval we are interested to.
Notice that, besides taking care not to saturate the oscilloscope channel, otherwise the
wanted signal will become clipped, we shall also AC-couple the output. In fact, the DC level
onto which the signal is superimposed is of the order of VCC, and will surely overload the
spectrum analyzer. The required isolation is accomplished by simply selecting the AC coupling
feature for the buffering oscilloscope, which introduces a high-pass pole lower than 10 Hz.
The transfer characteristic of the oscilloscope channel has been ascertained with the
network analyzer capability of HP4195A, resulting as in Fig. 5-23; from the phase diagram, the
DC decoupling pole is recognized to be quite low, whereas the magnitude proves sufficiently flat
for our purposes.
132
Chapter 5
Time-varying analysis of noise in the AAC servo-loop
OSCILLOSCOPE
Tek 2467B
80
7
Phase
6
Amplitude
60
5
4
40
3
2
Phase diagram [deg]
Magnitude diagram [ - ]
10
9
8
20
0
1
+1
1E
+2
1E
+3
1E
+4
1E
+5
1E
+6
1E
Frequency sweep [Hz]
Fig. 5-23
The oscilloscope stage of the amplification chain, tested with the HP4195A network
analyzer; the AC coupling does not interfere with the 5 (14 dB) flat gain.
The differential pair of the final amplifier stage should be sufficiently matched; a 2C444
discrete bipolar couple suffices (fT ≈ 200 MHz). The concern is about the equivalent input
referred noise of the transistors: to keep it negligible, we assure a rather high biasing current for
this stage (about 1 mA) obtained by adopting a tail resistor of 15 kΩ. This is not a high current
for discrete transistors, but choosing RCOLL = 2.2 kΩ it gives a gain in excess of 27 dB:
gm ⋅ RCOLL = 22
(5.19)
The dynamic range of the output will be just around
50 mV ⋅ 22 = 1.1 V
(5.20)
with 50 mV of peak input to stay still out of distortion. In effect the stage is not degenerated to
keep the noise low. The ripple of the driving signal fits anyway in this voltage range, as
illustrated in Fig. 5-24; as low as 48 mVpp derive from a 700 mV sinusoidal input:
Fig. 5-24 The forcing sinusoidal input and limited ripple at the output of the peak detector.
133
Chapter 5
Time-varying analysis of noise in the AAC servo-loop
The most critical design choices must be made for what concerns the input transistor and the
RPCP filter:
• the input bipolar should possess good switching characteristics; all measurements will not
exceed 5 MHz in frequency, but the peak of current needed to supply the resistor RP and
especially the capacitor CP must not overload the device. A BJT that satisfies this
requirement is the widely available N2219A, which endures current spikes in excess of 100
mA, reaches operating frequencies of 300 MHz and has a VBE breakdown voltage of 6 V
• for what pertains the thermal noise of the resistor, we can match RP to the impedance seen
into the base of the differential stage to assure the maximum noise transfer:
RIN diff = rπ + β⋅(Rtail//re) ≈ 2⋅rπ
(5.21)
or, RP = 10 kΩ. With RP = 10 kΩ, the bias current of Q1 is about 1 mA with VRC = -12 V;
this voltage reference is insulated from the common low rail, in order to vary the gm of the
transistor. The supply voltage values must cope with the necessity of keeping the DC input
voltage to 0 V; our sinusoidal generator (again the R&S SMT06, 50 Ω RF output) in fact
cannot add up a shifting DC level to the waveform. Readily available NIM-compliant
values of VCC = +6 V and VEE = -12 V proved convenient for performing the
measurements.
From the knowledge of tolerated ripple we get the criterion for choosing CP value. In the
simplified assumption of linear voltage drop (correctly applicable in the first 10% of
exponential decay), and by safely taking the entire rail-to-rail dynamics on the RPCP
parallel, it can be written:
t
1 µs
50 mV = ∆V > Vmax ⋅ > 18 V ⋅
(5.22)
10 k Ω ⋅ C
τ
where the falling time is approximated with the entire period T, at the standard test
frequency of 1 MHz. Then it follows CP > 36 nF; the used capacitance is CP = 47 nF, then
the rectifier pole is 370 Hz.
Let us consider other noise measurement issues. From a linear analysis of the noise
sources involved in the implemented circuit, during the “off” state the following spectral
densities come out (referred at the output):
•
•
•
•
shot noise from Q2: √ 2⋅4kT⋅re/2⋅1/4⋅G2diff = 13.9 nV/√Hz
single-ended noise from the tail of amplifier: √ 4kT/(2RT)⋅R2COLL = 1.1 nV/√Hz
thermal noise from load resistor: √ 4kT⋅RCOLL = 5.9 nV/√Hz
thermal noise from RP: √ 4kTR/4⋅G2diff = 139.1 nV/√Hz
The “on” state is a less noisy condition, though the input reference waveform generator
deserves care: its noise is in fact directly injected towards the differential amplifier, without
being filtered.
The thermal noise from RP, amplified by the cascade of differential stage and wideband
amplifier, results in –117 dBV2/Hz, or 1.39 µV/√Hz. This level is only slightly over the
sensibility of the spectrum analyzer when its input attenuation is set to 30 dB (to inhibit
overload), and must be risen. For this purpose, and also in order to overcome the spurious
electromagnetic emissions reaching the board from external environment - especially power
supplies and nearby CRTs - it proved very convenient to inject a known amount of white noise
into the filtered node of the circuit. The external noise was coupled to the circuit via a resistor
RCOUPLE = 100 kΩ >> RP, so that the chosen RPCP pole was not displaced. The 1:10 voltage
134
Chapter 5
Time-varying analysis of noise in the AAC servo-loop
partition scales the noise down to 20 µV/√Hz on the filter (-53 dBV2/Hz, or 2.2 mV/√Hz, after
the theoretical amplification).
The optional low-frequency signal source of Rohde&Schwarz SMT06 was employed
for this aim, synthesizing white gaussian noise with 200 µV/√Hz power density (measured on a
high impedance probe).
Fig. 5-25 Sample of the white noise generated by the Rohde&Schwarz SMT06 - LF feature.
Fig. 5-25 gives a snapshot of the white noise capability of the instrument.
The final realization of the two-sided board is depicted in Fig. 5-26; a) represents the top
side of the circuit and b) the bottom side, so that the two layers can be superposed by folding
them around the reference axis plotted horizontally in line-and-dot. The map of the bottom side
is also completed with text indicating the position and the type of components which will take
place between the dots drawn; these in turn outline the location of pinholes where the discrete
components will be fixed to the board. The two large circles accommodate BNC-female
connectors, and are surrounded by the 4 blocking screws pattern. Notice the breadth of power
supply lines, made as large as possible in order to reduce inductive bounce; their stability has
further been improved by large electrolytic capacitors (100 µF) put towards common ground.
Broad ground paths are designed on either sides of the board, and the connectivity between front
and back layers is assured by a series of 4 “vias” realized with thick screws (Fig. 5-27, right of
image).
a)
135
R2.2k
Time-varying analysis of noise in the AAC servo-loop
R1M eg
Chapter 5
Trim 20k
C47n
Diff
toFFT
PD
R2.2k
b)
PD
Diff
ToFFT
R10k
R15k
IN
→ Peak Detector NPN (TO-39 package)
→ Differential pair NPN
→ Output towards FFT Spectrum Analyzer (HP4195A)
Fig. 5-26 Layout of the discrete-components PCB designed for testing.
A photograph of the finished board is reported in Fig. 5-27.
from SIDE
from TOP
Fig. 5-27
Snapshots of the finished board, before the encapsulation in the metallic shield tank. The
three wires are for positive and negative NIM supply, and ground.
5.10 Switched noise measurements
The measurements reproduce the simulations described in the Paragraph 5.6: duty cycle
variation and tuning of the rectifier gm. In addition, a sweep of the input frequency concludes the
experimental results.
The noise fed to the analyzer has not been lowpass filtered on the board, because the
narrow sliding filter internal to the heterodyne analyzer performs exactly the time average
function simulated in Paragraph 5.5.2, without featuring the frequency cutoff inherent to fixedfrequency filters. We expect since then to observe the same behavior shown in Figs. 5-17 and 518.
136
Chapter 5
Time-varying analysis of noise in the AAC servo-loop
5.10.1 Duty cycle sweep
The first measurements are relative to duty cycle. VRC was kept to ground level to ensure
low values for gm. A duty cycle sweep ranging from 0.2% up to 99.8% was applied to the circuit
by adopting a square waveform input, generated by an Analogic Data Precision Mod.
2020 polynomial waveform synthesizer, which permits to define the duty cycle with the needed
precision. The curves in Fig. 5-28a are 100-fold averages of the instantaneous noise spectra, and
refer to a 1 MHz wave of peak amplitude 0.7 V. The input was monitored by means of a
Tektronix TDS620 oscilloscope; it is shown in Fig. 5-28b when d.c. = 50% and fIN = 200
kHz, with its rectified counterpart shifted one VBE down.
a)
R PCP profile
b)
Fig. 5-28 a) Noise power spectra recorded at the output of the board. The noise floor is due to the poor
noise performance of the square waveform synthesizer that drives the rectifier. b) The square wave at the
input, and the flat level detected by the rectifier.
The circuit shows the predicted behavior, keeping GBWP constant to 370 Hz ⋅ 2.02
mV/√Hz (-54 dBV2/Hz; the actual amplification is about 70). A very rapid decrease in the flat
part of the spectra is observed for duty cycles < 10%; thereafter the curves tend to superimpose
one over another. The measured spectra are sunk in a noise floor of –76 dBV2/Hz, clearly visible
at high frequencies. This is due to the noise directly injected in the circuit by the square wave
generator during TON intervals, with no attenuation; the polynomial synthesizer used features in
fact poor noise performance. Next measurements require sinusoidal inputs, which we can derive
from a much cleaner generator, then the noise floor will disappear (see Fig. 5-29). This
137
Chapter 5
Time-varying analysis of noise in the AAC servo-loop
experimental shortcoming possibly prevents the spectra from showing a behavior that is gradual
to our wanted extent.
5.10.2 Rectifier gm sweep
This measurement concerns variation of gm, here imposed by changing the amplitude of
the input. The duty cycle is always around 10%. GBWP remains constant over all of the
measurements, as is apparent from Fig. 5-29.
R PCP profile
Fig. 5-29 Experimental results when the gm of the rectifier is varied via the input amplitude. Since the
input generator is much cleaner the noise floor has disappeared.
τON was kept rather low in this test; this entails that the autocorrelation function of the
filter is quite narrow, leaving only minor room for further lowering settlements. The spectral
downsettling is even more pronounced when the VRC supply is lowered: after it has decreased
under –2 V, all of the spectra are almost stuck over the A0 = 940 mV curve shown above (since
gm increases and the “on” pole of the filter gets faster: a memory “overkill” for the peak
detector).
5.10.3 Input waveform frequency sweep
A conclusive measurement is performed by changing only the frequency of the sinusoidal
wave in input to the peak detector. Even starting from 50 kHz input sinusoid and terminating
with a frequency as high as 1 MHz, only minor adjustments are expected, because the duty cycle
is rather small already. This is effectively the case, as Fig. 5-30 reports:
138
Time-varying analysis of noise in the AAC servo-loop
-50
2
Noise power vs. Input frequency [dBV /Hz]
Chapter 5
-60
5 MHz
-70
1 MHz
500 kHz
-80
50 kHz
-90
RPCP profile
-100
100
1k
10k
100k
Frequency [Hz]
Fig. 5-30 Experimental results with variations of the input sinusoid frequency. Only very fast transients
(5 MHz input) can further reduce the d.c. and rise the spectrum level .
Only the shrink in d.c. caused by hastening up to 5 MHz the input frequency is capable of
modifying the noise spectrum, making it resemble a little more the “off” condition (upper curve
in Fig. 30).
As a final remark, note that - dealing with sinusoids - the transitions will be smoother
than in the square wave “on-off” case here treated; but since the analysis relies on the subsequent
lowpass action of the loop dominant pole, the study performed is indeed a fair approximation.
5.11 Design suggestions and SSCR correction inferred
In order to lower the low-frequency noise coming from the peak detector, the performed
analyses suggest the designer to work towards a minimization of GBWP, of course, and both
towards gm and TON (i.e., duty cycle) increase. For these rules to be valid, the AAC structure
must also carefully reject the noise coming from the stages driven by the peak detector, e.g. by
assuring signal amplification immediately after it.
Two simple formulas were given, which are capable of predicting the output noise
lowering versus the duty cycle of the rectifier. It has been highlighted that low-duty cycle,
switched implementations of the peak detector (the so-called C-class stages), while being
effective for low-power purposes, are not suitable for low-noise approach to the oscillator
design. It is instead preferable to operate the rectifier device keeping it active as much as
possible, and to rise the device transconductance through appropriate biasing. For instance,
average peak detectors instead of envelope peak detectors [37] can be exploited in the AAC.
Following these guidelines, the designer can tailor the rectifier and the lowpass filter to achieve a
suitable tradeoff between power consumption and phase noise issues. In our case, the current
generator of the peak detector was changed into a simple resistor, and the voltage drop across it
was shrunk via the adoption of a simple transdiode, acting as voltage shifter.
139
Chapter 5
Time-varying analysis of noise in the AAC servo-loop
For what concerns our AAC, at the end of Chapter 4 it was shown that the duty cycle of
the rectifier was around 47%. The pessimistic “off” noise estimate given there was -61 dBc/Hz,
against –96 dBc/Hz of the noise in the “on” case; the real phase noise lies in the middle. The
topology of the real peak detector is different with respect to the one analyzed, but the results
obtained are still trustworthy since, with the values of gm-1 and the time constants that can be
extracted from Fig. 4-30, the memory of the system is kept in much the same way (compliant
with Fig. 5-4). According to Fig. 5-21b, the present duty cycles can entail a correction of about
–12 dB to the rough prevision. A reasonable expectation for the final SSCR is thus around -73
dBc/Hz, against the -76 dBc/Hz that were measured. This fair agreement between the phase
noise measured and the prediction is a further proof of the soundness of the analysis here
discussed, for such a complex phenomenon; the approximation sinusoid → square wave can
easily entail some dB of error. The qualitative aspect of the noise reduction, prior unexplained,
has indeed been understood and given a quantitative weight.
140
Chapter 6
From concepts to circuit design
Chapter 6
From concepts
to circuit design
The analysis of the phase noise is complete. The main effects that have been identified to
threaten the SSCR performance of the oscillators examined so far, can be prevented and
rejected by means of circuit tricks. In particular, the existing cell has been modified in order to
ensure larger oscillation amplitude without incurring heavy degradation of its potential
stability. These variations have already led to a phase noise improvement in the FRAME6 cell.
The AAC was redesigned according to the chief guidelines suggested by the criticality of its
stability, and of the peak detector noise contribution. The advantages of the differential mode of
operation have been provided to the Colpitts stage, by instancing a mirrored topology and
inherently rejecting the common mode. The transconductor bipolars were brought towards
instability inserting an inductor on their base, which also provides a means for getting efficient
and linear VCO tunability. Last but not least, an alternative linearized tuning solution suitable
to reduce the PLL lock-in time is devised.
6.1 The key guideline
T
he concepts developed in the previous Chapters have been translated into practical
circuit proposals. In the following pages these ideas will be described. Some of
them have been already put on silicon by ST designers, fabricated, and tested;
indeed, some of the circuits characterized in the preceding sections already contain the
variations. Other findings have been converted into circuits and layout for the RUN0799 silicon
diffusion to be next measured at Politecnico.
Basing on Eq. (1.30) let us now consider what kind of circuit behavior is needed to meet
the GSM specification of -143 dBc/Hz at 3 MHz [81]. Even if the active elements were
noiseless, hence F = 0, at ω0= 1.8 GHz a quality factor Q of about 30 is needed, assuming an
oscillation amplitude A0 of about 400 mV. The requisite for Q gets relaxed if A0 rises up to 900
mV: in this case it must be about 10. Nowadays, in standard technologies repeatable Q values of
30 can be achieved only by using external tanks, while the integrated ones reach values on the
order of 10. The main responsible for the poor quality factors of the integrated solutions are the
spiral inductors, while the varactors usually set a limit when special inductor implementation
techniques are employed [11,82,83] or the frequencies grow over 3-4 GHz [35]. The example
highlights that the only chance to meet such a low noise requirements with fully integrated
VCOs is to increase the oscillation amplitude, driving the transconductor in hard-limiting
141
Chapter 6
From concepts to circuit design
regime. Otherwise, prohibitive values of Q may become necessary. All of the following solutions
have been proposed by envisioning a rise in the oscillation amplitudes, in order to strengthen the
carrier power and enhance the SSCR. But now, we know the exact consequences of this, and can
try to counteract them in advance.
6.2 Improvement proposed on the STARMAN cell
Instead of starting from a completely new project, let us begin by modifying the original
STARMAN oscillator. Along with the tank elements, the oscillating cell too must be carefully
optimized.
6.2.1 Cell core optimization
In particular, the high-pass coupling scheme applied to the transconductor removes the
VBC junction saturation limit. In the meanwhile, a similar inductive-transformer coupling has
been adopted in [38], while in [39] the capacitive ratio of an all-reactive voltage divider is varied
in simulation, until the SSCR minimum is sought. While TIBIA oscillator could reach
A0 max = V BC sat.max. ≈ 0.8 V
(6.1)
the STARMAN CUT 1 can now approach up to
A0 max = VColl.DC − VBase DC + VBC sat.max. ≈ ∆VCB statica + 0.8 V
(6.2)
as is clarified in Fig. 6-1:
CC
Polarizzazione
: <<V
BIAS: << VCC
CC
Polarizzazione
:V
BIAS : VCC
VB C
sat. m ax .
IP
Fig. 6-1
Passive network for base-collector voltage decoupling, and maximum oscillation amplitude
attainable before incurring saturation of the bipolar couple.
The present version of VCO features VCOLL = 2.4 V, VBASE = 1.7 V and VBC sat.max.≈ 0.8 V,
then the theoretical A0 max ≈ 1.5 V; the simulation of Chapter 2 gave instead A0 = 770 mV, due to
the AAC. The noise terms at the numerator of Eq. (1.30) for the SSCR does not seem to have
much room to be reduced, as the noise factor F is rather low already, and difficult to vary. The
carrier power should be improved. One of the first measures that can be suggested is the swing
improvement, through the elimination of the degeneration in the tail current source; this implies
the AAC redesign. The SiT term would surely increase, but the potential growth in A0 can
overstrike the effect and eventually prove beneficial. At a first order, we may write:
142
Chapter 6
From concepts to circuit design
S iT ∝ I TAIL
, but in turn:
A0 =
2 I TAIL
⋅
∝ I TAIL
π g 0t
(6.3)
and then
SSCR =
SvTANK / 2 SiT
I
∝ 2 ∝ TAIL
= 1
Þ SSCR ∝ 1
2
2
ITAIL
ITAIL
A0 / 2
A0
ITAIL
(6.4)
The well-known trade-off between power consumption and phase noise [3] has been reobtained in simple terms. But, a careless rise in ITAIL leads to high-injection phenomena in the
bipolars; and also consumption issues cannot be forgotten, when dealing with integrated wireless
transceivers.
6.2.2 Tail current optimization
The ITAIL → SSCR dependence of equation (6.4) is of course a first approximation. The
suitable refinement can be to simulate A0 with ITAIL, then extract Q after the set of relations
(2.13), after which the F factor is recomputed to give the phase noise estimation. The attention is
devoted exclusively to the best way of increasing the oscillation amplitude, regardless of the
noise up to now. The results of this procedure (at 10 kHz offset) are summarized in Fig. 6-2.
The SSCR values calculated via the non-linear formulas obviously do not feature the well
known rise, but evidence a very low minimum (-106 dBc/Hz @ 100 kHz). Since a frequency
divider ÷2 was integrated after the VCO, the data actually reads -112 dBc/Hz @ 100 kHz for f0 =
1.35 GHz. In that zone the efficiency of the oscillator cell, of which Q is indicator, is anyway
sub-optimal; the best trade-off Q-A0 will lie near the red vertical line, around 9 mA. This phase
noise performance will be very close to satisfying the GSM specs; nevertheless, we saw in the
previous Chapter 4 that such a smart result will not the reached so easily. From this point of
view, the presence of the 1.5 pF bridge capacitor between the emitters of the transconductor
(employed to free up the oscillator loop from low-frequency disturbances, [41]) seems to be
detrimental for the phase noise performance, because it enlarges the linear range of the stage;
i.e., it pushes towards the upper SSCR curve instead of lowering SSCR towards the more
effective high-limiting regime. The conclusions drawn at the end of Chapter 4 state that this is
not the case, and the zero in the detrimental conversion factor KAM-PM is precisely due to the
contribution of the capacitor to the loop delay.
52
197
432
643
740
817
958
1078
1178
Q
3.53
6.69
7.34
7.28
7.18
6.93
6.51
6.10
5.71
Linear
SSCR
[dBc/Hz]
-57.8
-70.7
-76.0
-78.1
-78.7
-79.0
-79.2
-79.3
-79.2
Non- linear
SSCR
[dBc/Hz]
-58.2
-72.1
-78.6
-81.8
-82.8
-83.7
-84.3
-84.9
-85.3
8.00
-55.00
-57.8
7.34
7.50
7.28
7.18
-58.2
7.00
Curve delle prestazioni
in funzione di Ip
Q
Q
6.93
-60.00
SSCR lineare
SSCR
lin
SSCR nonnon-lin
lineare
SSCR
6.69
6.51
-65.00
6.50
6.1
6.00
5.71
-70.7
-70.00
5.47
5.50
-72.1
-75.00
-76
5.00
-78.1
-78.7 -79
-79.2
-79.3
-79.2
-79.2
4.50
-80.00
-78.6
4.00
-81.9
3.53
-82.8
-83.7
3.50
-85.00
-84.3
-84.9
-85.3
-85.8
3.00
16
1288
5.47
-79.2
-85.8
-90.00
0.00
2.00
4.00
6.00
8.00
10.00
12.00
14.00
16.00
18.00
Corrente Idi coda
Ip
Tail current
TAIL [mA]
Fig. 6-2 Extraction of Q and SSCR@10 kHz after A0 simulations, and estimation of the ITAIL optimum.
143
SSCR after
(ideal
case)
SSCRcalculation
calcolato (caso
lineare)
1
2
4
6
7
8
10
12
14
A0 sim.
[mV]
Q inferred
after
A0
Q calcolato
da A0
ITAIL
[mA]
Chapter 6
From concepts to circuit design
6.2.3 Base biasing voltage optimization
The procedure followed in order to estimate the quality factor of the various elements
making up the VCO, can be adopted to find the best fit for the bias voltage of the transconductor
bases (much like in [39]). The noise, apart from folding effects, is not expected to change upon
variations of this voltage: the oscillation amplitude remains the sole parameter to maximize. A
transient sweep of the reference voltage has been simulated via a piece-wise linear generator,
obtaining the sequence of Q depicted in Fig. 6-3:
7.59
7.60
VBASE [V]
A0 sim. [mV]
Q
1.15
1.20
1.25
1.30
1.40
1.50
1.60
1.70
1.80
1.90
619
691
776
783
771
747
740
734
729
723
6.01
6.71
7.19
7.59
7.49
7.26
7.18
7.13
7.07
7.03
7.49
7.40
7.26
7.19
7.20
7.18
Q inferred
after A0
Q calcolato
7.13
7.07
7.03
7.00
6.80
6.71
6.60
6.40
6.20
6.01
6.00
1.00
1.10
1.20
1.30
1.40
1.50
1.60
1.70
1.80
1.90
2.00
V sulle BASIbase
(V) bias [V]
Transconductor
Fig. 6-3 Optimization of the Q by sweeping different bias voltages on the transconductor bases.
Too high a biasing pushes the base voltage towards the collector (i.e. VCC supply),
reducing the headroom available for the oscillation. On the other hand, low biasing compresses
the underneath current generator, pushing its transistors towards saturation especially when more
ITAIL is required. Even a sort of “squegging” was sometimes observed in Eldo simulation in those
conditions. Another simulation series suggested that the resistors of the C-R high-pass be
reduced from 2 kΩ to 1 kΩ each.
6.2.4 Transistor sizing and its benefits on FRAME6
The saturation of the transistors of the transconductor cell may impact in a deleterious
way on the phase noise efficiency of the VCO, as highlighted by the analysis of Paragraph 4.13.
Especially when the tail current is brought towards 10 mA, the cell can suffer heavy losses from
the Q and the indirect stability point of views, which ultimately spoil the performance of the
oscillator. The Q analysis of the STARMAN CUT 1.1 gave proof of this already in Chapter 2.
The original TIBIA version of the cell used double-base terminal transistors of medium
emitter length, the C6 type. New simulations were performed adopting instead C12 bipolars, i.e.
with maximum emitter size. For what concerns the signal, the measurement leads to an
improvement finally appreciable from Fig. 6-4a and b:
144
Chapter 6
From concepts to circuit design
V(Coll1) V(Coll2)
a)
Icollector
Time
V(Coll1) V(Coll2)
b)
Icollector
Time
Fig. 6-4
Enhancement in the oscillation amplitude obtained by passing from C6 to C12 bipolar
transistors in the transconductor (double emitter length).
Transition frequency [GHz]
The BJT enlargement proves surely effective from a noise standpoint, to enhance the
stability of the oscillator loop; the topic was discussed before in Chapter 4, and is linked to the
better current carrying capability of the devices without sudden increases in Cπ. In order to
exploit this promising possibility, the transconductor of the test VCO in chip FRAME6 was
realized no more with 4 but with 6 transistors, and of F12 type, having interdigitated structure
and the biggest emitter size available in the HSB2 technology. Fig. 6-5 depicts the transition
frequencies fT simulated for the three types of transistors that have been involved in these
oscillators.
Tail current ITAIL [mA]
Fig. 6-5
Transition frequencies for different kinds of bipolar transistors of the HSB2 technology, as
obtained from Eldo models. The F12 model endures by far the higher current, without showing
degradation of its dynamic performance.
145
Chapter 6
From concepts to circuit design
The beneficial effects of the variation can be readily inferred from the extended range of
constant Q, before the loading effects begin decreasing it. By comparing the next Fig. 6-6 with
the corresponding Fig. 2-25 of Chapter 2, it can be noted the higher current (14 mA against 6
mA) at which the bending starts.
Ampiezza
di amplitude
oscillazione
Oscillation
[V][V]
2.0
1.6
1.2
0.8
0.4
0.0
0
4
8
12
16
Itail [mA]
Tail current
ITAIL [mA]
Fig. 6-6 The widened linear range of the VCO cell. The known relation between the slope of this plot
and the Q indicates that the Q-loading effects do not arise well above 14 mA, guaranteeing a better
efficiency of the stage (equal amplitude at less current → less noise). The blue curve represents the
simulation results, and compares fairly well to the green experimental data.
The direct stability enhancement is instead testified by Fig. 6-7a and b. The zero in KTAIL
has been displaced at higher amplitudes, from 400 mV to 800 mV, hence the white “classical”
phase noise contributions will be lower in the new optimum. The frequency as a function of A0
features a broader peak, so that the AAC set point is tunable with less tight a tolerance. This
parameter indicates, more in general, improved robustness of the VCO. The distinct variability
of the data at high amplitudes in Fig. 6-7b is due to saturation phenomena affecting the output
buffer stages (PPA).
a)
b)
1600
2.59
2.58
@ 100
100kHz
kHz
KKTAIL
IT @
Frequenza
[GHz]
Oscillation
frequency
[GHz]
2.60
2.57
2.56
2.55
2.54
STARMAN
1200
800
FRAME6
400
2.53
2.52
0.0
0.4
0.8
1.2
1.6
2.0
0
0.0
0.4
0.8
1.2
1.6
2.0
Oscillation di
amplitude
A0 [V][V]
Ampiezza
oscillazione
Ampiezza
diamplitude
oscillazione
[V]
Oscillation
A0 [V]
Fig. 6-7 a) The sensitivity of the central frequency to the amplitude regime of the cell features a much
broader peak, occurring at higher A0 than for the Starman family; consequently, b), the KTAIL diagram is
smoother and its zero lies at nearly double amplitude.
146
Chapter 6
From concepts to circuit design
The final SSCR performance of the VCO in FRAME6 reaches at best -97 dBc/Hz; the
snapshot of Fig. 6-8a is taken after the ÷2 frequency divider. This noise floor is the limit set by
the tuning voltage noise. On the tuning node, by means of the low-noise amplifier described in
Appendix A we measured this time 18 nV/√Hz, increased if compared to the 11 nV/√Hz of the
STARMAN family; the sensitivity KVtune cannot have changed and is rather constant around 1100.
The inferior limitation set is:
2
KVtune
(α ) ⋅ SVtune (α ) = 196 ⋅10−12 1
SSCR (α ) =
2
Hz
2
Vtune
(6.5)
that is, -97 dBc/Hz. The oscillator successfully attains such a level this time. The digital circuitry
can be completely switched off (see the board option designed in Chapter 8), but unlike the
power amplifier PPA. The V-shaped SSCR remains, and is fitted by assuming a noise level of
even 0.3 nA/√Hz coupled to the tail: superior to the STARMAN case. Due to reuse of pre-existing
blocks, the relative position of the new VCO with respect to the noisy blocks has changed in the
FRAME6 floorplan, and the oscillating cell is in effect nearer to the last noise source left working.
a)
b)
SSCR @ 100 kHz [dBc/Hz]
-85
-90
-95
SSCR Vtune
-100
SSCR IT
-105
0.1
2
3
4
5
6 7 8 91.0
2
Ampiezza
di oscillazione
[V]
Oscillation
amplitude A
0 [V]
Fig. 6-8
a) Picture of the minimum SSCR read on the spectrum analyzer; the frequency is already
divided by 2. b) Interpretation of the SSCR, obtained summing the 0.3 nA/√Hz converted by KTAIL (blue
curve) and the 18 nV/√Hz tuning noise converted by KVtune.(red dashed), that has now become the limiting
term.
6.2.5 Decoupling issues – The output voltage follower
Up to now, except for FRAME6 (decoupled) the oscillation amplitudes have not been so
high to saturate the base-collector junction neither of the peak detector, nor of the emitter
followers that read the VCO output. After the 0.8 V threshold will be trespassed, some clamping
is expected, and unacceptable loss degradation is likely to happen. The trailing stages must then
be provided a separate (higher) supply or, more feasibly, an AC C-R coupling to the VCO. The
147
Chapter 6
From concepts to circuit design
base of the follower can be biased lower, and the swing towards the power rail can be properly
increased (as done for example in [38]). 10 kΩ and 1 pF can be integrated on chip, giving a 15.9
MHz pole that lies 2 orders of magnitude under the oscillation frequency. Fig. 6-9 recalls the
modifications actually needed:
TUNE
CDEC
CB
C12
1 kΩ
RB
CB
RDEC
C12
RB
1.3 V
OUT
VLOW
VBASE
F12
Fig. 6-9
Some modifications proposed for improving the phase noise of the STARMAN-like VCOs:
addition and enlargement of tail, and also transconductor, transistors; bias set point and optimal driving
resistor for the bases; AC coupling for the output followers to prevent saturation of the external blocks.
The emitter follower shall be dimensioned so as to eliminate the periodic load-pull
phenomena, that may induce spurs on the oscillation, caused by the variations of the parasitic
capacitive load at the output voltage, as noticed in [72].
6.3 Inductor enhancement
In order to fully grasp the beneficial effects that a technological improvement can confer
to the phase noise performance, some trials to modify the spiral inductors while leaving
unchanged the remainder of the STARMAN cell have been carried out. The cubicle of trenches
that disrupt the surface of the substrate has been redesigned to be even more dendritic and
effective in reducing the capacitive losses. A plane of metal layer has been drawn under the
inductor, so as to collect the eddy currents and prevent any thermal dissipation (or, loss) of them.
The plane has then been patterned to avoid the inductance reduction due to electromagnetic
mirror effects. Finally, the lower metal layer of the spiral has been removed to increase the
isolation between the passive element and the nearby substrate, at the price of a little more
resistivity. Completely alternative techniques such as the center-tapped inductor [84] have not
been enclosed in the test chips, because we had not access to electromagnetic simulation
software. Since the tentative variations entail principally a superior care in the layout of the
structure, they will be exhaustively discussed in Chapter 7.
148
Chapter 6
From concepts to circuit design
6.4 Design of the new Widlar AAC
The new amplitude regulator loop was designed keeping in mind the peak detector noise
issue and the swing improvement of the VCO cell. The block diagram of the AAC is not
changed; let us follow the signal path from the VCO tank to the VCO tail, according to the actual
schematic of the circuit that can be found in Table a.
The noise of the peak detector has been faced first. Several passive techniques are
candidate to the solution of this problem; however, the analysis of Chapter 5 indicates that the
higher the duty cycle and the rectifier transconductance (average detectors), the lower the noise.
The trade-off between noise and power consumption is unbalanced, here, towards the first of the
two figures. Examine the different configurations:
C
R1
Fig. 6-10
Two equal resistors assure a good dynamic behavior,
and also voltage shift towards the lower rail, needed to recover some
headroom and enlarging the available swing for the differential stage.
However the oscillation amplitude is divided by two, and this is
surely detrimental for the loop gain.
R2
Fig. 6-11
Two capacitors can equally partition the signal and
provide downshift. While C2 slowly discharges through the differential
amplifier base, C1 is charged during the “on” interval of the rectifier;
but once turned off, the transistor opens and prevents the discharge of
C1 onto which the charge builds up. This “bootstrapped” stage is thus
not working as desired...
C
C1
C2
Fig. 6-12
... but, once the charge buildup is avoided, the
principle works. A diode in place of C1 assures the desired voltage
drop, and during the discharge of C2 through the input resistance of
the trailing stage, the upper series of 2 junctions is simply shut down.
The current flowing through the diode must be high enough to ensure
a low value for gm-1, otherwise unfavorable signal scaling occurs.
Fig. 6-13
The discharge problem can be solved in the classical
way, by the shunt resistor acting as bleeding element for both rectifier
and diode, and regulating the discharge time constant. When the
resistor is set to 1 kΩ and with a capacitance of 1 pF, for a 300 mV
stepwise variation in the oscillation amplitude, the transient in Fig. 614 has been simulated.
R
C
149
Chapter 6
From concepts to circuit design
V(Osc1)
V(Peak detector)
Time
Fig. 6-14 Up- and down-step transient response of the peak detector in Fig. 6.13 .Note the “bands”
due to residual ripple (≈ 20 mV) and the slight loss (≈ 10%) of the detector.
Both charge and discharge are now fast (τDIS is estimated near 730 ps) and the 300 mV
step is sensed giving 270 mV. On the other hand, the ripple is worsened with respect to the
preceding cases, owing to the increased charge displacement on the R-C filter. The solution
can be further refined in relation to three figures of merit: the residual ripple, the injected
noise, and the input signal peak attenuation.
•
Residual ripple:
If we tolerate a maximum current of 500 µA at the beginning of the discharge, and set
for the steady voltage a reasonable level of 1.5 V (half the supply), we get:
V peak
ì
ï I ) I max = R = 0.5mA Þ R ≈ 3k Ω
ï
ï II ) ∆Q = tcharge ⋅ I charge = C ⋅ ∆V
ï
ß
ï
ï
í
æV ⋅ T / 2
ö
C ⋅ ç peak
÷ 2 ⋅V
ï
RC
C ⋅ ∆V C ⋅ ∆V
peak
è
ø=
ï I charge =
≤
≈
≈ 1mA Þ re DIODE = 25Ω
tcharge
T /4
T /4
R
ï
ï
ï III ) τ >> T / 2 Þ RC > 10 ⋅ T / 2 Þ C > 600 fF
ïî
(6.6)
where tcharge was overestimated with T/4 (rising front of the sinusoid) and tdischarge with the
entire T/2. The final ripple resulting by choosing C = 5 pF and R = 3 kΩ is surely overestimated,
but anyway rather high:
T /2
∆Vripple < V peak ⋅
= 18mV
(6.7)
τ
•
Injected noise:
This peak detector scheme fulfills the request we had imposed on it, i.e. it is “on” for
most of the time. The current into the capacitance of Fig. 6-15 flows in the opposite sense with
150
Chapter 6
From concepts to circuit design
respect to Fig. 4-30: the stage is “on” for 74% of the time, in the eyeball estimation proposed
here below.
Osc-
Osc+
Peak
26%
74%
Fig. 6-15 Simulated plot of the current flowing into the capacitor; the “on” interval of the rectifier has
increased from 47% up to 74% (with the usual eyeball estimate) in the new configuration.
In the “off” condition, the resistor injects its noise towards the 2rπ input resistance of the
subtractor-differential stage. The noise available to the next stages can be calculated by
performing the voltage partition:
SV Tx
æ 2 rπ ö
= 4kTR ⋅ ç
÷
è 2rπ + R ø
2
(6.8)
rms Voltage noise available [V/√Hz]
If ITAIL of the differential is for example 0.5 mA, it is 2rπ = 14 kΩ, and the effective noise
transfer to the amplifier stages can be figured out to help choosing the R of the peak detector.
Once represented in a graph, the (6.8) formula gives the Fig. 6-16.
Peak-detector R values [Ohms]
Fig. 6-16 Voltage noise available to the trailing differential stage for various values of the peak
detector resistor.
151
Chapter 6
From concepts to circuit design
The worst case is of course the matched resistance condition; in
order to avoid such a state, the easier way is to lessen the resistor of the
peak detector. The current drain and the ripple would be worsened; but, by
inserting a transdiode in series to the passive element, the voltage level at
the peak detector output is preserved without consuming large amounts of
current. By lowering R down to 300 Ω, after simulation it was observed
that the noise of the peak detector becomes comparable with the noise of
the successive stages.
The adoption of an additional follower in place of the diode was
tried, and it really led to reduce the ripple. Nevertheless, the noise of that
other version was a little worse than that of Fig. 6-17 (15 nA/√Hz vs. 10
nA/√Hz on the tail) and the solution was rejected.
C
R
Fig. 6-17
After the other stages were designed, the new curves of the current noise affecting the tail
have been derived; they are proposed in Fig. 6-18.
The subtractor/amplifier is implemented with a fully differential stage, with symmetrical
collector load. In Chapter 3 it was noted in fact the detrimental impact of the noise coming from
the voltage references; in the previous AAC it was not rejected, since the differential-to-single
ended conversion was performed right there. In this AAC the conversion is instead carried out
only in a second stage, after that the amplification and dominant pole filtering have taken place
in the more critical first stage. The enhanced symmetry of such a solution is testified by the
results sketched in Fig. 6-18:
-8
Noise 1st stage – ideal bias
Noise TAIL – AAC off
Noise TAIL – AAC on
Frequency
Fig. 6-18 The tail current noise generated by the overall AAC stages (blue and red curves) and by the
first differential stage without peak detector, and ideal bias (green plot). The noise of the first stage is
now dominant, almost unaffected by the bias disturbances and by the carefully reduced contribution from
the peak detector.
The simulations highlight the absolute noise reduction achieved thanks to the peak
detector, and the relative abatement of the biasing network noise contribution - indicated by the
difference between the two lowest curves. The noise addition is now much inferior to the 28%
featured by the prior scheme. Even better performance (the 3 curves practically coincident near 8
nA/√Hz) could be obtained without the diode, but with increased waste of power.
152
Chapter 6
From concepts to circuit design
Peak attenuation:
Especially at low amplitudes, the diode is weakly biased and tends to turn off. The whole
oscillator design is indeed aimed at accomplishing high values of A0, then the circumstance is of
minor importance.
The dominant pole compensation strategy, together with the noise considerations,
imposes to put a lowpass filter on the first amplifier. The pole was obtained with a symmetrical
π-connection of resistors and bridge-capacitor, to preserve the rejection of the bias disturbances.
The position of the pole was initially chosen by performing standard AC analysis of stability, i.e.
of phase margin. Later on, the non-linearity of the Widlar final stage of the system made it
compulsory to iterate the AC analysis in different amplitude conditions. In particular, the lower
values of A0 imply a strong stimulation of the Widlar current mirror, and a sudden gain peaking
that we must prevent from triggering the instability of the loop.
The large output voltage swing and the high gain requirements were in fact satisfied by
eliminating the degeneration on the tail of the VCO, and adopting a Widlar mirror to drive the
cell. We noticed that the noise factor was already rather low, then the signal amplitude was
privileged as design guideline. The indirect instability degradation could be avoided by
positioning the set point of the amplitude regulator in correspondence of the zero of the
conversion, that now we know how to tailor (with poles and zeros; see Chapter 4). The
exponential transfer characteristic of the Widlar stage has often proven instrumental in the
realization of AGC for transceivers, and is thus very popular and studied [71,75]. Its potential for
poor temperature stability can be softened by choosing resistors with appropriate, positive or
negative, thermal coefficients, and adopting PTAT in the stage.
The final stage was designed in order to be capable of supplying large amount of peak
currents, by using 6 F12 transistors on the driven branch, and only one F12 on the driving leg of
the mirror. To reduce the otherwise too large mirroring error due to the base currents sinking, the
driving device was reinforced by means of a transdiode-feedback-connected F4 bipolar. The
static transfer equation is eventually:
I TAIL / 6
=e
I DRV
RDRV I DRV
Vth
(6.9)
The driving current IDRV is supplied to the Widlar stage by a PNP constant current source,
whose current flow is partially diverted away from the Widlar by the second amplifier stage of
the AAC. The PNP transistors work only as active loads and are not truly involved in the signal
path, hence do not experience transients, and the circuit is not limited by their quite poor speed
characteristics. This “current stealing” technique allows us to use a minimal number of stages,
improving the noise performance of the regulator; moreover, using PNP and NPN we gain
enough voltage headroom to degenerate all of the service and signal blocks, further reducing the
noise. This is very useful, since the PNP can derive its current reference by mirroring the one of
the NPN current sources; this is not a low-noise technique, in principle, but does not impact the
overall noise figure in this circuit.
Fig. 6-19 reports an excerpt of the start-up current transient as controlled by the currentsteering transistor of the second stage:
153
Chapter 6
From concepts to circuit design
Icoll
Ibase
Iemitter of 2
nd
STAGE
Time
Fig. 6-19 The current sink performed by the second stage at the initial transient, to starve the Widlar
mirror and settle the oscillation amplitude under the self-limiting level of the VCO.
Initially, the whole current available from the PNP source is supplied to the Widlar (the
transistor does not draw current); after the oscillation has ignited, the AAC kicks in by sinking
current and starving the final stage. Thereafter a finer tuning of the current is accomplished.
The stability analysis must concern the instability effects caused by the non-linear nature
of the AAC. Of course, within such a framework the classical linear Bode analysis must be first
carried out, and proper phase margin is to be provided. Due to noise considerations, the
dominant pole on the first amplifier is set via passive resistors load; assuming that half the railto-rail swing is available for gain (1.5 V), we are given a limit:
Gmax =
∆VR
1.5V
=
= 60
Vth
25mV
(6.10)
In order to set the pole at sufficiently low-frequency, resistors have to be large. But the
tail current in the differential sets the ohmic drop on them, but also the input-referred noise,
which is to be matched with the one of the peak detector to achieve the noise optimum.
Eventually, ITAIL = 340 µA were chosen, and relaxing down the voltage swing requirement to 1 V
we accept to use 6 kΩ resistors. The gain of the first stage is about 40, or 32 dB, and ensures
good noise rejection to the trailing blocks.
To instance the minimal capacitance, we put a metal-to-metal 12 pF capacitor bridging
the two branches of the differential couple, in π-fashion, so as to see the cascade of the 6 kΩ
resistors:
RP
RZ/2
C
RZ/2
RP
H ( s) = gm RP
1 + s ( RZ ⋅ C )
1+ s
( (2 R
P
+ RZ ) ⋅ C )
Symmetrical π structure
of the pole-zero network on the first
stage of the AAC.
Fig. 6-20
154
(6.11)
Chapter 6
From concepts to circuit design
The dominant pole lies at fdp = 1/(2π⋅12 kΩ⋅12 pF) = 1.1 MHz, that is nearly the
maximum bandwidth we found to be compatible with a 60° phase margin specification. The zero
at 26.5 MHz also obtained in symmetrical way by the passive network in Fig. 6-20, is for polezero compensation purposes. In fact, the Bode diagrams of the loop with only the dominant pole
come as in Fig. 6-21:
Frequency
Fig. 6-21 Bode plots of the transfer from the peak detector to the first stage output (red line), and of the
entire Gloop (green line), with only the dominant pole compensation.
The phase margin is only 40°: unacceptable in a system that must also withstand hard
non-linearity. The red phase plot relative to the first amplifier stage let us ascribe the second pole
around 230 MHz to the subsequent stages. But simply compensating the other pole proves not
useful; interactions between the singularities exist, which make this trick ineffective. By adding
probe capacitances to the suspect nets, it was found that the puzzling singularity resides in the
driving leg of the Widlar mirror. Forcedly splitting its poles with a 2 pF capacitor across the
transdiode, the lower pole was displaced down to 26.5 MHz, were we could compensate it with
the zero (500 Ω in the π bridge). The definitive Bode plots obtained are shown in Fig. 6-22.
70°
27 dB
Frequency
Fig. 6-22 Bode diagrams relative to the final design of the AAC. From VP(V1) the pole-zero sequence
(lag network, in classic control theory) is seen, that compensates for the undesired pole on the DB(Gloop)
graph below that does not reach –40 dB/dec slope. Phase margin is 70°, gain margin 27 dB.
155
Chapter 6
From concepts to circuit design
The doublet near 20 MHz can be still observed in the phase plot, but is practically
inappreciable in the magnitude graph. The phase margin is > 70°, the gain margin runs about 27
dB, and the linearized loop gain is 42.6 dB (or, 135) at moderate current, 55 µA, flowing in the
Widlar. The real transient gain can burst to over 103 and crumble to practically zero, thanks to
the Widlar exponential control law. The ripple of the peak detector now is rejected less
effectively than before, due to the zero in the first stage; this is an item to be taken into account
to avoid spurious noise tone mixing in the VCO, possibly back-annotating this further spec in the
peak detector design (… and likely choosing the double-follower configuration for it).
We started from the highly unstable behavior in the case of 40° margin (Fig. 6-23), showing
evident squegging phenomena [37] that only on the average match the reference issued to the
AAC (Vrif):
V(Coll1)
V(Peak)
V(Coll1)
V rif. = 1.25 V
Time
Fig. 6-23 Instability (squegging) phenomena caused by the insufficient phase margin of the loop (40°);
the set point of the regulator is indeed caught, but only in average sense.
Now we have switched to a regular, smooth control transient. All at the simulated Widlar
current.
The main concern risen by the exponential driving of the final stage is stability. In effect
[77] recalls that a 2-pole AAC can engender regenerative behavior, and we resorted to a single
dominant pole (with pole-zero compensation doublet…); but in [76] the control law was found to
be not robust, and extensive simulation is needed in any case. The design has been done by
taking the Bode diagrams of the loop gain in a balanced condition of the first stage: but, when
the feedback is to increase the tail current, the loop gain is increased too, and risk exists to fatally
overestimate the phase margin. The non-linearity would generally require descriptive function
techniques, or attraction boundary identification; we exploited instead much simpler
considerations. The problem was addressed by trading off the maximum amount of current
supplied by the second amplifier stage (or, eventually, the dynamic range of the regulator) and
the Widlar gain resistor RDRV. By choosing 1.97 kΩ for gain, a steady current of 55 µA produces
11 mA in the VCO, that boost A0 to more than 1 V as desired. If we allow a too broad variation
range to the input of the Widlar, at the upper extreme of the swing we could have consumed all
the gain margin we had, and run into instability. For example, even if the nominal setup is found
to hold 27 dB of gain margin, when the current tuning range of the second stage is allowed 20
µA of steering capability the initial transient is the one in Fig. 6-24. It shows an undamped
amplitude modulation on the waveforms.
156
Chapter 6
From concepts to circuit design
st
OUT 1
STAGE V(Peak)
V(Coll1)
Time
Fig. 6-24 Start-up transient of the AAC+VCO control system with 70° of phase margin, but too large a
current swing left to the exponential Widlar stage (55 µA ± 10 µA): a limit cycle is started.
The start-up is the worst-case test for the AAC stability, since the first stage sweeps its
entire voltage swing, and the Widlar is surely forced to its peak current capability. The maximum
current manageable in the second stage without incurring persistent ripple is about 12 µA; the
final design sets the current of the second stage to 10 µA. Even with such a feeble current
modulation allowance, the amplitude can be swept from 0.90 V to 1.55 V (650 mV output
swing). The output this time appears very smooth, as depicted in Fig. 6-25:
st
OUT 1
STAGE V(Peak)
V(Coll1)
Time
Fig. 6-25
Stable behavior of the VCO coupled to the AAC with reduced current swing around the
nominal point (55 µA ± 5 µA). The worst-case transient delay comes about 100 ns.
The red curve represents the output signal of the first amplifier, evolving with the time
constant (≈ 140 ns) set by the dominant pole. The attack time [75] of the final version of the
AAC is about 100 ns, well below the switching delay specifications set forth by [2] for the local
oscillation synthesizers.
Finally, from the noise standpoint, a naïve prediction comparable with the one made in
Chapter 4 and leading to the (4.17) gives:
( 9.9 nA /
Hz
)
2
(
⋅ 26% + 7.7 nA / Hz
)
2
⋅ 74% = 8.3 nV / Hz
(6.12)
157
Chapter 6
From concepts to circuit design
where the noise amounts in the “on” and “off” states of the peak detector have been weighed.
Translating this estimation into SSCR at the output of the VCO in the known way, a phase noise
prevision of about –97 dBc/Hz at 2.6 GHz is obtained, against the –76 dBc/Hz of STARMAN with
AAC on. Moreover, from the currents reported in Fig. 6-15 it can be concluded that the series
resistance of the junctions should be lower than in STARMAN case; and the d.c. has increased, up
to 74%. Then after Chapter 5 the noise is inferred to have fallen much more than in the prevision
above. The performance of –103 dBc/Hz @ 100 kHz at half the frequency, 1.3 GHz, is therefore
surely an overestimation. Jointly exploiting the AAC new features with the improved FRAME6
oscillating cell described above, the SSCR optimum could be shifted to 0.9 or 1 V, i.e. in the
lower controlled range of the AAC, with greater benefits for the performance.
6.5 A pre-warped solution for linearized differential tuning
Apart from the phase noise issues, also the tuning problem is a central topic that has
entered this discussion, following ST demand. Having a linear tuning control law for a VCO will
become progressively more important, as 3-G wireless standards advance. For example, FHSS
(Frequency Hopping Spread Spectrum) standards such as 802.11 for WAN may be deployed
with a PLL executing periodical frequency jumps and lock-in transients. The settling time of the
PLL depends on the spurs generated by the VCO embedded in it [85]; naturally, the non-linearity
of the VCO tuning curve causes the generation of distortion, and the PLL will waste more time
tracking some spurious harmonics, before locking to the wanted oscillation. The varactor tuning
available for STARMAN is rather linear, but also limited in range: 12% with VTUNE ranging from
2.4 V to ground (2.77 GHz → 2.46 GHz respectively), with a maximum measured KVCO ≈ 240
MHz/V. Usually, varactor-tuned VCOs feature scarce linearity over their range of frequency; an
alternative tuning technique involving the operation of two LC tanks was proposed in [86], but
possibly suffers from multi-oscillation onset especially at startup.
After opening the PLL loop, we performed a frequency measurement also forcing in
forward zone the varactors, and obtaining the results reported in Fig. 6-26:
Oscillation
Frequenza difrequency
oscillazione[GHz]
(GHz)
2.80
2.60
2.40
2.20
2.00
1.80
-3000
-2000
-1000
0
1000
2000
Tensione
sul referred
nodo TUNE
al BGR
(mV)
V
as
torif.
BGR
[mV]
tune
Fig. 6-26 The tuning curve measured on the STARMAN series (reverse bias → PLL inserted, forward
bias → direct voltage driving of the varactor devices).
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Chapter 6
From concepts to circuit design
As expected, the tuning range is boosted up to 35% (2.77 GHz → 1.95 GHz) when the
diodes are biased with 1.3 V external forward voltage; the 5 kΩ internal resistor protects the
junctions from burnout, while their diffusion capacitance steeply increases. The slight ripple at 0
V abscissa derives from the experimental setup differences, passing from VTUNE > 0 (PLL loop
closed, input fREF changes) to VTUNE < 0 (loop opened, direct varactor driving). The SSCR was
recorded in parallel, and shows only minor (4 dB) worsening in the forward bias conditions. In
effect, also in [84,87] a limited forward bias condition was reached, but no dramatic phase noise
increase was reported.
The new tuning characteristic is quite non-linear however, and a negative voltage cannot
be easily achieved on-chip. We tried to drive the varactors in differential fashion: instead of
keeping the anode fixed and varying the cathode, we move anode and cathode in counterphase,
doubling in this way the voltage swing across the diodes. The idea was also attempted in [87]:
but moreover, here the driving curve is shaped so as to compensate for the reactive non-linearity.
The steep C(V) in forward bias can be driven smoothly, whereas the smooth C(V) in reverse bias
has to be swept steeply. The concept of tuning pre-warping is better clarified in Fig. 6-27.
a)
b)
2.80
V_tuning
Frequenza di oscillazione (GHz)
V across VARACTOR
2.60
2.40
2.20
2.00
1.80
-3000
-2000
-1000
0
1000
2000
Tensione
sul
TUNE
al BGR
(mV)
V
as nodo
referred
torif.
BGR
[mV]
tune
Fig. 6-27 The pre-warping idea: the voltage across the varactor is controlled so as to counterbalance
the slope of its C-V characteristic. The tuning circuit simultaneously adjusts both the anode and cathode
voltage of the component.
The needed circuit is substantially a variable-slope signal inverter. The solution
illustrated in Table b adopts a simple current mirror:
• when the tuning voltage is decreased, the current steered by the mirror lowers and
the anode is pulled-up by the usual 5 kΩ resistor, leading to forward biasing condition
• when the tuning voltage is increased, depending on the mirror area ratio the current
drawn by the driven bipolar can more or less rapidly raise; the diodes are brought in reverse
bias, then the current flows in the 5 kΩ resistor reducing the anode voltage until saturation of
the stage.
The control static characteristic illustrated in Fig. 6-27a is obtained by simulation of the
stage in Table b; it is not still optimized for low phase noise, but is surely effective for tuning
range enhancement and linearization.
159
Chapter 6
From concepts to circuit design
6.6 VCO with synthesized inductance - tuning capabilities
The bipolar transistor can be viewed not only as is done in traditional electronics, with a
π-equivalent circuit characterized by electrical parameters such as rπ and gm. When observed
from the microwave standpoint of s-parameters, the active device used for the implementation of
an oscillator can be completely described by the Stern stability factor [14,88] that gives an idea
of how much the transistor is prone to the oscillation. In microwave practice, it is rather usual to
modify the Stern number for a device, by adding some reactance on its terminals: for instance,
placing an inductor on the base of the transistor helps making it more suitable for oscillation.
Starting from this “cross-fertilized” knowledge, we understand that the smaller the extra-loop
gain [89] necessary at the start-up to begin the oscillation, the less the non-linearity incurred by
the VCO when the oscillation has settled. Then, both the spurious harmonics and the noise
folding effects will be relaxed.
The inductor on the base was instead adopted by Dauphinee et al. [7] to create a series
LC tank, even exploiting the Cπ of the bipolar transistor (see Fig. 6-28a). The aforementioned is
the bipolar VCO achieving the best SSCR performance in standard technology, -105 dBc/Hz @
100 kHz. Like in the Colpitts below, the fact that the circuit works without relying on the base
isolation properties (as instead happens in STARMAN) can help reducing the Q-loading effects
discussed in Chapter 2, and surely improves the indirect stability. In the half-period when the
bipolar is on, the Johnson noise of the resistors on the base is transferred to the collector, which
becomes noiseless in the remaining time. Moreover, the transistor is pushed towards the
oscillation in a natural manner; this can be asserted either with the microwave paradigm, or
noticing that the negative resistive part of Z(ω) in Fig. 6-28a counterbalances the losses of the
tank and allows the onset of oscillation. The sketched schematic represents one half of the total
differential circuit, that has been reproduced from [7] in Fig. 6-28b.
a)
b)
Z(ω)=r eq +jωLeq
LB
RB
IBIAS
C
Fig. 6-28 The negative-resistance impedance seen into the emitter of the device arranged as in a) can
be exploited within a series LC tank, b), to balance the resistive losses of the inductor (after [7]).
Moreover, the Leq is tunable via the IBIAS .
There is another important feature of this circuit that can be exploited: the tunability of
the equivalent inductance seen into the emitter of the BJT. According to the analysis presented in
[7] and [90] that impedance is:
160
Chapter 6
From concepts to circuit design
Z (ω ) = req + jω Leq =
1 − ω 2 LBCbe
RC
+ jω B be
gm
gm
(6.13)
The reactive part of Z(ω) is an inductance, but it does not depend on the actual LB, nor its
quality factor does. To a first order, the expression of L(ω) indicates that bias current variations
do not influence the inductance (both Cπ and gm are proportional to IBIAS); then, the only utility of
the inductor synthesis will be to obtain higher values of L, that nevertheless is important in fullyintegrated realizations [91]. Nevertheless, the indirect synthesis of inductance is usually
perceived as a noisy practice.
The whole schematic of the VCO is presented in Table c. The final layout of the VCO
permits to bias externally the bases of the bipolars, instead of resorting to the current mirror
solution depicted in Table c, better suited to complete integration. The differential working is
obtained by crossing the two mirrored stages, without adopting damping resistors. Unlike in [7],
the collectors also have been provided with a tank that sets the ω0 frequency together with the
transconductor reactance.
Running a simulation where the bias current is changed stepwise, and the oscillation
frequency is extracted at every step, Fig. 6-29 is obtained. The frequency sequence is plotted
versus the tuning voltage that drives the current source, obtaining a tuning characteristic that
nearly coincides with its linear best fit.
a)
b)
3.75
Frequency
Oscillation frequency [GHz]
3.70
3.65
3.60
3.55
3.50
3.45
3.40
3.35
1.1
1.2
1.3
1.4
1.5
1.6
Time
Tuning voltage on the tail [V]
Fig. 6-29 a) Linear tuning characteristic of the synthesized inductance VCO, with the voltage driving
the tail; in this circuit amplitude and frequency are inherently coupled. b) shows the sequence of
frequencies extracted by Xelga with a user-defined routine.
There is evidence that the higher order terms deviating from Eq. (6.13) for L(ω) have
considerable impact on the central frequency of the oscillator structure. The tunability shown
here of this VCO reaches 10% (340 MHz over the central value, 3.55 GHz), with a stable KVCO =
690 MHz/V, to be compared with the non-linear 70→270 MHz/V measured on STARMAN. The
tuning range is probably more extended; with 1.6 V bias of the tail, in fact, the oscillation
amplitude is already saturated to 1.4 V, while the frequency keeps linear to an excellent extent.
The great linearity of the current-frequency characteristic can be appreciated at a first glance also
from the Xelga-processed output of Fig. 6-29b. For this same reason, the “indirect” stability (this
time coinciding with the direct one, since the bias is the tuning variable) can be a major concern:
the greater the tuning sensitivity, the greater the tuning noise conversion. Anyway, this circuit
161
Chapter 6
From concepts to circuit design
condenses into one problem of noise minimization the two concerns, for tuning and bias noise,
that were additive in STARMAN. The adoption of a shunt capacitor in parallel to the B-E junction
adds an instrumental degree of freedom to tailor this tradeoff to a suitable compromise.
In summary, this VCO (Fig. 6-30) can be viewed as a basic Colpitts-Clapp [92] modified
with an active device better disposed to instability. The frequency region where the
transconductor can assure a negative resistance comes out of the equation:
ω>
1
LBCbe
(6.14)
To increase the negative resistance of the transconductor and the useful bandwidth, a
higher LB is desired, and Cbe is augmented by an external shunt capacitor. Since we could rely
only on “standard” spiral structure, a LB only double than the L of the collector tank was
employed (see Chapter 7).
Potential jeopardy for the VCO is the mismatch between the 4 tank resonances; at any
rate, it could lead to multi-oscillation phenomena [86], without deteriorating the phase noise.
Fig. 6-30 The cross-coupled, synthesized inductor oscillator.
6.7 Mirrored-Colpitts oscillator and output buffer issues
Single-device solutions such as Colpitts or Hartley have long been considered the best
option for implementing a low-noise oscillator, and are actually adopted in a variety of scientific
[93] and more practical [94] realizations. On the other hand, differential topologies are
appreciated for the greater A0 they can boast, the ease of connection with inherently differential
blocks such as image-rejection double-balanced mixers, and superior rejection to common-mode
interference affecting the outputs. We tried to compose the advantages of both kinds of
oscillators by designing a differential circuit out of the Colpitts-Clapp stage.
The classical Colpitts oscillator comprises a parallel LC tank, fueled by the collector of a
single transistor. The capacitance of the tank is derived by the series connection of two
capacitors, whose central node is tied to the emitter, biased by means of a current source.
Provided 1/(ω0C2) << gm-1 of the transistor, the Q of the tank is not loaded by gm. The actual
driving of the transconductor, that this time is to be identified with the standalone bipolar, is the
voltage sinusoid reported on the emitter.
162
Chapter 6
From concepts to circuit design
It does not seem to be trivial to couple two Colpitts circuits in order to obtain a
differential one. In fact, even cross-coupling the capacitive series of one stage with the emitter of
the other, since the emitters are varying in phase with their collectors (except for the base transit
time τTR) the loop is a common mode, and not a differential mode, one. A better resort is the
adoption of common mode quenching resistors, to be tied to the nodes lying onto the symmetry
axis of the mirrored structure [7].
The coupling of two identical systems gives rise to two different oscillation modes,
intuitively sketched in Fig. 6-31 (the degrees of freedom of the overall system must keep, as
usual). In particular, we can decompose the behavior of the circuit in the differential- (antisymmetrical) and the common-mode (symmetrical) oscillations.
Differential mode
Common mode
a)
b)
Fig. 6-31
The symmetry principle behind the differential-mode sparing and the common-mode
damping, exploited in the synchronization of the two Colpitts oscillator halves.
The nodes on the symmetry axis do not “see” the signals of the differential-mode. Each
half-oscillator node is out of phase with its mirrored companion on the other side; the central
nodes are in counterphase with themselves, thus the signal must equal zero there. The quenching
resistors’ presence is therefore not experienced by the system.
For what concerns the common-mode behavior: this time the central nets move
synchronously with every other node. The existence of a common-mode signal in the system is
sensed by these nodes, and the quenching resistors damp the signal progressively to zero,
preventing it from affecting the oscillation. After the start-up transient, the only mode that is left
alive is the differential mode, and the two halves of the compounded Colpitts are oscillating at
180° from one another. The mutual squelching action resembles closely the one reported in [95]
for a quadrature oscillator.
The oscillator engineered is shown in Table d. We talk of oscillator, and not of VCO: for
this first attempt, the use of varactors would have complicated both the analysis and the
experimental activity. The diodes could be anyway put in parallel to the series capacitors, or
mimicked by the collector-substrate parasitics of the transistors by driving them through the
inductors, from the supply rail as proposed in [70,87]. The test circuits have been designed at 3.6
163
Chapter 6
From concepts to circuit design
GHz, suitable for transceivers for the DCS1800 GSM standard; the division by 2 of the
frequency simplifies the extraction of the quadrature signals needed by the trailing mixers.
Small damping resistors of no more than 160 Ω are sufficient for a quick common-mode
blocking. They have been tied to the same external voltage reference, biasing the transistor
bases; this proved useful to reject high-frequency interference on the node, since it is coupled to
both sides of the B-E junction, and does not transmit to the collector. The optimal capacitor
series ratio was found to be 1:9 on amplitude simulation basis, in contrast with the general phasenoise-driven suggestion of 1:4 ratio [20]. With only 2.4 V of supply and total bias current of 5
mA, from simulations, A0 as high as 1.7 V is read. The transconductor is made with 4 maximumsize F12 BJTs in parallel, to relax the indirect sensitivity effects as much as possible. This last
trick was very effective, if we look to the (dimensional) sensitivity diagram in Fig. 6-32:
16
14
KTAIL [MHz/mA]
12
10
8
Frame 6
6
4
2
0
Double-Colpitts
0
2
4
6
8
10
12
14
16
18
Tail Current ITAIL [mA]
Fig. 6-32 Comparison between the indirect tail stability indicator of the FRAME6 prototype and the
mirrored-Colpitts: the latter is clearly advantaged in this key performance benchmark. The coefficients
are expressed in dimensional fashion in this graph.
The comparison is made with the FRAME6 VCO, which is already our best one. The
mirrored-Colpitts features KTAIL coefficient values 4 times lower than the cross-coupled VCO, on
the average. Only at very high currents the saturation effects are predicted to spoil such an
excellent performance. This behavior can be ascribed chiefly to the advantageous emitter driving
of the transconductor, that is the configuration assuring the widest bandwidth to the device, and
hence guarantees the maximum distance between ω0 and the unwanted poles. From the
discussion of Chapter 4, this means that the emitter driving enhances indirect stability, as
ascertained by Fig. 6-32.
In Table d, besides the oscillator, the output stage is reported. It consists of two
traditional emitter followers, which protect the oscillating core from the external loads, and feed
the open-collector output driver. Unlike in [38,96] the final differential pair is not degenerated, in
order to feature complete switching and act therefore as hard-limiter (or, AM-rejecting network).
As outlined in [97] such a hard limiter is subject to introducing AM-to-PM conversion, which
could encumber the phase noise measurement. A sequence of Eldo simulations was performed,
by injecting AM- and PM-modulated carrier in the buffer and examining the FFT of the signal
after the stage: in the former case the average AM rejection was –26 dB, whereas in the latter the
164
Chapter 6
From concepts to circuit design
PM passed almost unchanged (only -0.5 dB lost). The modulations were superimposed to the
carrier by adding appropriate phase/quadrature tones to it, generated with Cadence behavioral
library blocks. The stage is therefore suitable to fulfill our experimental aims.
Note, in Table d, that the adoption of a separate power supply for the output stages [98]
permits to raise the B-C voltage drop of the followers, preventing the saturation of the junction at
high amplitudes. The open-collector stage calls for the adoption of on-board RF chokes, to
supply the bipolars at DC while being opened well before ω0. This issue will be treated in
Chapter 8; here we can assert that it proved preferable with respect to the follower solution, also
simulated, from the swing and especially the power consumption standpoints. The collectors
directly drive the exit pads, as in [38,98]; an on-board SMD out-of-chip bias-T will route the
oscillation to a discrete balun for the differential-to-single-ended conversion. The adoption of RC compensation on the pads and external ladder filter [96], as well as fully balanced buffering
with L-C impedance transforming [56] to achieve low, power-independent distortion and
reduced pull-in, were not deemed mandatory in our case. In fact, minimal length bond wires will
be devoted to the outputs on the test chips (see the end of Chapter 7), and the buffer will be
located into a separate, independently biased trench.
Much like in [38] the tail generator delivers about 6 mA to the switching differential
couple, that once reported on the 50 Ω featured by the external balun translates into a 600 mVpp
square wave; the first harmonic (of 4/π⋅300 mV amplitude) has thus +1.6 dBm power on 50 Ω.
This carrier level, referred to the noise floor of our spectrum analyzer (warranting -135 dB
maximum sensitivity) still permits to measure GSM-compliant SSCR levels and beyond.
Of course, the previous one is only a principle analysis. The buffer functionality was
simulated at 3.6 GHz-worst case, with the equivalent of the bonding pads, of the package
(crosstalk) and of the external capacitive and inductive load of the pins and attached trace. The
stage output in Fig. 6-33 is more similar to a sinusoid than to a square wave:
V(BALUN) Icoll
V(Diff. out)
Time
Fig. 6-33
The output voltage driving the balun on the RF board. It is generated starting from the
sinusoidal signal driving the hard-limiter/buffer, that drives the 50 Ω through the bond and package
equivalent circuits. On the red wave the AM has been rejected, whereas the PM is left intact.
The power of the resulting first harmonic (≈ 170 mV) is still –5.4 dBm, anyway suitable
for our experimental purposes. The package has been modeled by a network taking into account
crosstalk (with transformers placed between nearest neighbors) and pad loading (with
capacitors); the external tracks have been reproduced with properly sized RC-ladder network.
165
Chapter 7
Layout of the new structures
Chapter 7
Layout of the new structures
In this Chapter the main features and techniques adopted in the layout of the circuits are
described. The salient characteristics of the 17 HSB2 bipolar circuits and the only CMOSF6Y
VCO are outlined: more in particular, the 7 versions of the STARMAN with modified layout and
inductor variants, the differential tuning solution, and the central symmetry layout of it; the 3
splits of the new AAC design, with filtered bias voltage; the 4 compacted layouts of the Colpitts
with modified inductors, and the design of the synthesized inductor VCO. Finally, the
organization of the circuits into the TQFP-48 package of the 6 test chips is presented.
7.1 Package-driven test chips organization
T
he analyses performed in the previous Chapters have concerned several aspects of
both the core cell making up the VCO, and the wrap-around servo circuits, such
as the AAC and the output buffer. In order to exploit the ideas that have been
developed and verify their effectiveness and on-the-chip feasibility, we had the possibility to
access a silicon run from STMicroelectronics, Catania site foundry, under the aegis of Italian
University and Scientific Research Ministry project “MADESS II”. The run was in HSB2-P30
technology, the high-speed bipolar process whose parameters have been used throughout the
previous simulations and circuit analyses.
The packaging option chosen is TQFP-48 (Thin Quad Flat Package with 48 pins, gullwing leads, 12 per each side; see Fig. 7-1) in order to achieve a sufficient number of inlets and
outlets for the test circuitry. In fact, despite in principle an oscillator does not require a high pin
count, we decided to supply our VCOs with externally filtered reference biases, which make the
number of needed connections appreciably higher.
166
Chapter 7
Layout of the new structures
Fig. 7-1 External look and mechanical dimensions of the TQFP-48 package (after STMicroelectronics
Web site).
For example, let us consider the simple mirrored-Colpitts described in Chapter 6. It
features 2 balanced differential outputs and one tuning input, along with its own analog power
supply and ground. The oscillation amplitude measurement proved essential over all the phase
noise characterization, and therefore will be sensed by means of a specific peak detector.
Moreover, the final buffer stage requires a separate voltage supply and ground. In fact it will
undergo a switched working regime, that makes it resemble more a digital than an analog block:
accurate power rail insulation is needed to reduce ground bounce issues [99]. Since the current
flowing in the buffer directly impacts on the oscillation amplitude available on the test board, the
buffer tail current source has external regulation capability in turn. These 9 pins are common to
all the designed VCOs. Additional lines have been devoted to the external control of the
transconductor (for bipolar base level, tail current generator driving), and to the biasing of the
heavily-doped guard rings, which have been used to decouple from the ubiquitous substrate
noise at least the wells holding critical devices. The total pin count raises then to 12; for the
worst-case, i.e. circuits comprising the AAC, it reaches 16. Since constraints exist about the
connection of the bonding pads - the ones in the corners for example, and to project one single
RF test board, the maximum number of chips that can be accommodated onto a single die was
fixed to 48/16 = 3 circuits at best.
The TQFP-48 package has been successfully tested for RF application in a number of
antecedent demonstrators, ranging from CT-2 (GIRAFE-European Community project) to DECT
standards (TIBIA test boards).
As the silicon run is performed contemporarily to 3 other Italian Universities, and the
overall dice available from the process stepper are 36, we could obtain a maximum of 12
different dice. Yield issues suggested anyway to lower the test chip number, in order to increase
the eventual specimen count to be delivered to our test and measurement laboratory.
7.2 Layout issues of the test VCOs
In summary, 6 versions of VCO circuits were mature for testing in the RUN0799 run:
1. the STARMAN-like VCO, standalone, with slightly improved symmetrical layout and
external bias tunability
167
Chapter 7
2.
3.
4.
5.
6.
Layout of the new structures
the STARMAN-like VCO, standalone, with anti-symmetrical layout
the STARMAN-like VCO with redesigned Widlar AAC
the mirrored-Colpitts VCO
the synthesized-inductor, emitter-driven VCO
the VCO with differential tuning circuitry.
Each circuit topology lends itself to a number of further variations-on-a-theme. The main
splits concerned the integrated inductor style, and the AAC structure. In the following, all the 17
oscillator layouts will be presented, and some details will be discussed. For sake of graphic
clarity, the complete series of the layouts is reported in the Table A-Q sequence; for ease of
reference, every circuit has been given a letter designator. The next Paragraphs have been sorted
for technological similitude regardless of the letter designation of the VCOs, and do not follow
the alphabetical order.
In Fig. 7-2 the most important technological layers are referenced, in order to ease the
interpretation of both the Table A-Q and the other figures of this Chapter:
Fig. 7-2 The main technological layers of the HSB2 bipolar process.
7.2.1 Layout A – Standalone STARMAN
Fig. 7-3 The new layout of the STARMAN-like VCO. The LC tank dominates the structure, that is
completed by the active transconductor (below) and by the output buffer (on top).
168
Chapter 7
Layout of the new structures
The layout is represented in Fig. 7-3. The topology is essentially oriented to maintaining
the symmetry, that is the paramount characteristic of the schematic and assures a common-mode
noise rejection, owing to the differential output. This is eased by the original symmetrical
configuration that was adopted for the inductor. All the L and Q (quality factor) data provided in
the previous Chapters were referred to this structure, that has been thoroughly tested in preexisting demonstrators and, thanks to the knowledge accumulated on it, constituted a safe
reference point for the development of all of the new layouts.
The inductor turns result from the parallel connection of Metal2 and Metal3 layers
[87],[100]; the contacts are visible at the ends of each half-L. The internal outlet of the passive
shows the classical bridge of Metal3 over Metal2.
Typical of the pre-existing projects is the placement of the capacitive elements inside the
inductor. The fixed metal-to-metal decoupling capacitors are kept outside, while the varactors
share the tuning line, and the central resistor string that biases them in reverse.
The LC tank is one of the most critical sub-networks within the VCO. Kelvin guard-rings
of decoupling around the fixed-value capacitors have not been adopted, since a precise value for
their capacitance is not required, and the symmetry does not call for further homogenization of
the border “landscape” seen by the metal plates. Anyway, sufficient room for introducing subtle
dummy capacitors has been left on top and towards the outer border of the plates.
The 5 kΩ resistors have been realized through the parallel of three 15 kΩ lightly-doped
polysilicon resistors; the device are alternately connected to the left and to the right varactor
blocks, via the horizontal red Metal1 lines. The other resistor terminal is put to ground, that is
routed throughout the VCO starting from the bottom, in blue Metal2. From a flicker noise
standpoint the increased area of this solution would bring beneficial effects, because the noise is
averaged on larger an area - a property widely exploited in low-noise MOS input stages. In our
case, the current flow is negligible (only Irev of varactors) and 1/f noise is not an issue; should a
direct-bias operation for varactors be chosen, this resistor configuration would be among the
best. Thermal noise remains unchanged of course. A possible concern is represented by the risk
of picking up some substrate noise, coupled through the oxyde underneath to the increased area;
notice however that the resistors lie exactly onto the symmetry axis, that is in principle the
cleanest point of the whole circuit.
The varactors are standard cells of about 1 pF each. If we could overlay the decoupling
capacitors to them, a greater parasitic suppression may be achieved, but the design rule checker
(DRC) did not allow this operation to preserve the planarity of metal-oxyde-metal “sandwich”
structure. The anode connects directly to the resistors via the Metal1 crossovers, and contacts the
Metal3 plate of decoupling capacitors (see Table a, purple oval) through the adjacent double-tier
of via12 (Metal1 → Metal2) and via23 (Metal2 → Metal3). The cathodes are attached in Metal2
to the tuning node that is routed from top to bottom. As observed in the FRAME6 tests of Chapter
6, tuning electrode is of crucial importance: it deserves then to be routed onto the symmetry axis,
before bifurcating to reach the varactors.
The tank components’ topology features only small variations from former test circuits.
The transconductor, the tail and of course the buffer structures have been instead completely
redesigned.
The collectors of the transconductor bipolars must be close to the tank, to reduce the
additional parasitic resistance that adds to the 5.7 Ω collector resistance. But they must also
permit a short and parallel routing out for the two oscillation outputs. The problem has been
solved by placing the transconductor at the bottom of the tank, and the final buffer at the top: the
bottom plate of the decoupling C (in Metal2) is tied to L and carries the oscillation, hence can be
viewed as a single node providing a lot of favorable connection choices. Placing the buffer under
the VCO would have meant to crowd up of output and control lines such a region of the circuit,
169
Chapter 7
Layout of the new structures
with interference risk and heavy burden of route un-puzzling to bring them to the bonding pads.
In Fig. 7-3 instead we pass under the upper side of the inductor: the two output lines are kept
very close to the vertical axis, near the inductor contact to the positive supply - where it shows
virtually no voltage variation.
The cross-connection between the transistors of the transconductor exploits the C-R
highpass coupling network. The bottom plate of the capacitor connects to the collectors, then the
upper one contacts one extremity of the resistor, that is biased by the line TRANSCOND-A
realized in Metal3 and kept over the axis. The more convenient Metal2 layer has been reserved
to the ground routing, which features a greater contact number. The unavoidable crossing of the
lines that drive the opposite transistor bases has been managed through a dummy metal bridge;
Fig. 7-4 zooms over this detail. These are the only paths that necessarily require to breaking
symmetry, which is to be recovered with the trick shown below.
equalized
Fig. 7-4 Zoom on the path equalization for managing the cross-coupling between the transconductor
bipolars. A dummy metal bridge symmetrizes the load on the crossing-under line.
The tail section has been organized by splitting the emitter resistors. One 520 Ω resistor
of the smallest feasible area is attached to every emitter. This time we know that the substrate
noise pick-up is highly deleterious, and one of the foremost aims of this test run is to minimize it;
hence the highest sheet resistance (about 1 kΩ/) has been chosen. The tail driving voltage
reaches the bases from symmetrical Metal1 paths, coming from outside, and once again starting
from the axis in order to enhance its noise immunity. The last layer that was left free is Metal1;
the axis is completely occupied in all of its three freedom degrees in the depth dimension, to get
advantage from the symmetry.
Last, the 1.5 pF bridge capacitor that DC decouples the emitter of the transconductor
bipolars opening the loop [41], is implemented as the parallel of two capacitors evenly placed
and connected. The collectors of the tail devices connect to the capacitors through via23, on each
side, equally starting from Metal3 plate; the crossing is then obtained by reversing the other half
of capacitance, in which the node becomes Metal2.
During the layout of the active parts of the VCO, special attention was paid to the
compaction of circuitry. The two halves of the oscillator core were enclosed in separate silicon
wells, delimited by a perimetric turn of trench [101]. Nevertheless, in the upper and lower parts
of the two regions some n-doped pockets have been inserted [102], in order to set the potential of
the well and divert away any substrate-injected noise. Liberal use of contacts, tightly organized
in predefined arrays, was done to strengthen their voltage-tying efficacy [102],[103]. An
170
Chapter 7
Layout of the new structures
insulating implanted belt of dopant was also provided between the tank area and the active one,
trying to moderate the possible unwanted interactions. The simulation and experimental activity
presented in Chapters 2-4 indicates how sensitive the active devices in the VCO are; thus every
attempt to lower the effect of noise coming from outside has been carried out in the layout step,
when other countermeasures at schematic level were unfeasible.
Given its position, embedded within the two additional power supply rails horizontally
drawn over the VCO, the output buffer has been optimized with respect to vertical pitch. This is
a non-critical interface block, hence the layout has not been as accurate as for the preceding case;
the only care was devoted to ensure a suitable position for input and output plain routing. The
two intermediate emitter followers, driving the final open-collector stage, enclose the other
elements and are placed in the traditional “totem pole” configuration. The current source
transistors of the trailing hard-limiter found room between the devices of the switched
differential pair. They are controlled by the external voltage VBOUT-A, thus giving the test
operator an additional means to set up a variable output signal amplitude. The degeneration
resistor ought to endure currents of the order of 6 mA; a general rule for this technology predicts
safe working (extended MTBF) of the elements if the current is kept below 0.15 mA/µm [27],
then the width of the polysilicon layer was increased to 40 µm, and the length consequently
raised to about 10 µm. For the resistors of the transconductor tail, instead, noise pick-up issues
prevail and the area was shrunk as much as possible; the current can possibly be less than the one
in the buffer.
The open-collector outputs exit the chip in Metal2, after some bridges to jump over
transversal lines. The signal is now rather strong and features hard-limited amplitudes, thus it is
no longer compulsory to minimize its path towards the out. The balanced collector signals drive
also the two tiny bipolars for amplitude peak detection. The simple R-C shunt appears to the
right of the circuit, in asymmetrical position; the capacitance has been adapted to the vertical
pitch. The tracks leaving the emitters are of very different lengths, but in practice the signal
PEAK-A is at very low frequencies and cannot interfere with the other lines. Bringing it at the
center of the output paths would be of no utility, and leads to avoidable routing problems. The
only concern can be the 2ω0 ripple coupling, since the tuning line is crossed: the path width has
been anyway kept minimal, and the capacitive load attached to the tuning should guarantee that
disturbances are allowed a very unfavorable partition.
7.2.2 Layout B – Standalone STARMAN with improved-Q inductor:
Metal1 plate
A first split of the previous design has been done putting a uniform Metal1 plate under
the inductor. As pretty intuitively explained in [104], the adoption of such a technique for
shielding the inductor from the lossy substrate can, in principle, improve the quality factor of the
inductor. The equivalent circuit of the inductor loses in fact the strong influence of substrate,
which in Fig. 7-5b is modeled by means of the series of capacitors COX (the insulation from the
substrate) and resistors RSUB (greatly varying between bipolar and MOS technologies), as in
[105]. The RSHIELD of the plate replacing RSUB is now on the order of milliohms. The drastic
reduction in the resistive component of the network makes the remaining reactive term almost
ideal, and could impact in favorable way on the quality factor.
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Layout of the new structures
B
R SUB
RS
1
Ieddy
C OX 1
tg δ
2
LS
RS
R SUB
C OX 2
R SUB
RSUB
a)
SUB
b)
Fig. 7-5
a) Simplified scheme for the description of the losses in a planar spiral inductor: metal
resistive, substrate-capacitively coupled, substrate-magnetic coupled (eddy currents), dielectric tangent.
b) Equivalent circuit for the spiral inductor, complete with loss-modeling elements.
This can be immediately inferred by the formula of QL due to ohmic losses in the turns
and in the surface of the silicon substrate, given by:
æω Lö æ
1
Q L = çç 0 ÷÷ // çç
è R S ø è ω 0 R SUB C OX
ö
÷÷
ø
(7.1)
In [9],[105] more general expressions can be found; the (7.1) gives only the effect due to the
lower part of the loss equivalent of Fig. 7-5b, that indeed is the sole taken into account in a lot of
cases [93],[106],[107]. Also the eddy currents penetrating deeper in the bulk (Fig. 7-5a and the
upper sub-circuit of 7-5b) can share the benefit of the resistance reduction. Anyway, the eddy
currents (otherwise called Foucault currents) induced by the magnetic field generated in the turns
will virtually have no limitation, and by circulating in the metal shield will:
1. create a mirror of the inductor structure. This can be directly visualized by recalling the
perfectly conductive infinite plane paradigm of electromagnetism [108]. After the Lenz
law, the mirror inductor will counteract the Metal2-Metal3 device, compensating for it and
causing a net decrease in L (a graph of the fall in inductance vs. the distance of the
grounded plane is given in [109])
2. more important: boost the losses of (ISUB 2⋅RSUB) kind. This term raises for very low values
of sheet resistance [104], just as metal, and can seriously hinder the overall QL of the new
configuration.
The capacitive component of the tank should be increased in order to maintain a fixed ω0;
anyway, by increasing C also the current consumption will rise and the transconductor will suffer
for early saturation at lower A0. For our test purposes, it was preferred to keep C constant and
verify the decrease in L by directly observing the growth in ω0.
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Chapter 7
Layout of the new structures
Fig. 7-6 Metal1 uniform shield underneath the spiral turns, connected to the power supply rail.
Fig. 7-6 outlines this modified detail of the VCO, which is otherwise identical to Fig. 73. The shield consists of a simple Metal1 rectangle that is tied to the power supply. This test has
been suggested to quantify the incidence of the substrate losses on the QL; in case of successful
results, a more complex modification to the process can be tailored, to change the doping of a
thin layer beneath the surface of the silicon. The unwanted effects due to the eddy currents can
be either predicted by 2-D electromagnetic simulations, or canceled out by patterning the new
shield layer.
7.2.3 Layout L – Standalone STARMAN with improved-Q inductor:
Metal1 patterned shield
As is common practice in power transformers, the parasitic eddy currents can be
noticeably lowered by breaking up the conductivity of their paths, and channeling them to flow
into very smaller domains [105],[109]. The smaller is the flux that couples to the domain, the
smaller will be the intensity of the induced mirror current. In our case, an easy-to-do and
effective way to disrupt the eddy current rings is to create a metal pattern, instead of adopting a
simple Metal1 uniform plane below the inductor. The pattern must be designed to be transversal
to the expected flow direction of the parasitic currents, so as to interrupt the flow. In [109]
several kinds of pattern are proposed, for the conductive substrate in the CMOS process taken as
reference; all of them share anyway this orthogonality principle. Since our inductor shows
octagonal geometry, the layout of the surrounding metal strips has been consequently
implemented perpendicularly to the 8 metal lines. Instead of drawing only one big cut into metal,
the plane under every inductor side has been divided into many 5 µm-wide sub-stripes, that
further fragment the eddy currents, thus leaving the total value of L almost unchanged. The
straight upper part of the spiral has been subtended with orthogonal “teeth” of Metal1. The shield
however does not include closed loops, but is an open structure (mathematically said: a
connected domain). The details of the resulting artwork are shown in Fig. 7-7.
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Chapter 7
Layout of the new structures
Fig. 7-7 Metal1 patterned shield; in order to effectively counteract the induced currents, the cuts in the
metal plane are always scribed perpendicularly to the direction of the spiral.
The stripes have been kept as near as possible to one another (fully exploiting the
correspondent design rule, i.e. 1.4 µm distance). The entire shield is tied to the nearest (and less
bouncing) VCO power supply line; the upper VCC rail has been shaped so as to surround 3 sides
of the plane, and improve the contact efficiency.
This version of the circuit is expected to enhance the slope of the ITAIL-A0 plot, while
minimally uplifting the oscillation frequency of the VCO. The complete experimental
characterization of test devices has been reported in [105]. [104] also shows the existence of an
optimum for the quality factor QL, with the substrate conductivity; however, this technological
parameter was not under our control, since it is fixed to about 10 Ω⋅cm (also the suggestions of
[110] were impractical). The only means we could exploit were circuit design ones, achievable
thanks to the Metal1 plane.
7.2.4 Layout N – Standalone STARMAN with improved-Q inductor:
Metal3-only spiral
The previous VCO in Layout A has been further modified by using a Metal3-only
inductor. The parallel connection of the 2-turn Metal2 and Metal3 structures, while reducing the
series resistance, surely contributes to rise the capacitive coupling with the substrate. In this
version, the sole Metal3 turns are left: being the highest layer, Metal3 features a special 3 µm
thickness against the much thinner Metal2, and therefore the series resistance is less than
doubled. Moreover, the silicon oxyde thickness between the conductive layer and the substrate
increases, so the shunt resistance parasitic effect lessens. The importance of the substrate losses
in limiting the QL of our two-metal inductor was experimentally verified: in different test chips,
featuring similar inductors but realized with the upper metal layer only, phase noise
improvements of up to 3 dB were observed. This happens at normalized frequency: the 1-level
inductance noticeably diminishes at equal area in fact (see the case of [87]). The trade-off
devised in [9] is then unbalanced towards the adoption of 1 metal layer in our case.
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Chapter 7
Layout of the new structures
From the layout standpoint, the inductor is even more simplified (one half is displayed in
Fig. 7-8). The contact arrays to join Metal2 and Metal3 no longer exist, and the final cross-under
to exit from the inner turn is realized directly with Metal2, as usual, complying to the next
contact with the decoupling C. The output lines are directly routed in Metal2.
simplified
Fig. 7-8 Zoom on the exiting metal bridge. The layout of the turns is greatly simplified if only one level
of metal can be employed.
7.2.5 Layout C – Standalone STARMAN with improved-Q inductor:
Single-turn Metal3 spiral
As reported in literature [9], higher number of turns means higher inductance, but also
higher losses. Designing an inductor with a single turn is then the exacerbation of the principle
that the center area of the spiral must be kept free [8],[9], since it cannot provide additional
inductance but does produce detrimental increase in the series resistance due to mutual coupling,
that is now minimized. On the other hand, ST simulated the single-turn inductance shown in Fig.
7-9 obtaining L of about 400 pH (tool: Ansoft HFSS).
Fig. 7-9 Layout of the 1-turn inductor. The width was reduced in order to rise the inductance value; the
octagonal geometry was kept, and is compatible with the pre-existing VCO topologies.
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Chapter 7
Layout of the new structures
Such a tiny value calls for a heavier capacitance in the tank, and this in turn will require
more current to reach the desired values of A0. In order to test exclusively the effect of
inductance variation, however, the varactor structure was left unchanged; eventual corrections
for the ω0 will be performed analytically. The oscillation frequency is expected to approach 3.6
GHz, then a fair comparison will be done with some of the next Colpitts oscillators, which have
been designed for similar frequencies.
As usual, the other characteristics of the circuit topology (transconductor, tail, etc.) are
identical to the former versions of the VCO. The differences in the measured phase noise
performance could thus be safely ascribed only to the inductor variation; this explains why the
inner space of the inductors has not been occupied by the active elements (and also due to Q
concern, see [106]). This layout arrangement will hopefully give indications also about the
advantage of employing hollow inductors, from a noise coupling standpoint [111]; the pads of
non-active VCOs could be used as probing points.
7.2.6 Layout M – Standalone STARMAN with improved-Q inductor:
Metal1 patterned shield and Metal3-only spiral
Eventually, the two modifications applied to Layout L and Layout N have been combined
together. The VCO shows then a classical inductor structure, though fabricated in Metal3 only,
with an underlying Metal1 patterned shield. Thus the two mechanisms of substrate loss reduction
described above ought to add, and the better phase noise performance is expected from this cell.
7.2.7 Layout D – Standalone STARMAN with
modified trenches surface shielding
One aspect of the techniques that have been adopted in the layout of the VCO has been
purposely neglected up to now: the green trench shielding underneath the inductor (“Trench”
layer in Fig. 7-2). It is well known that the magnetic field can penetrate into the silicon wafer,
down to a depth approximately equal to the planar dimension of the spiral [104]; but the lower
COX-RSUB sub-circuit in Fig. 7-5b identifies substrate losses that are determined by a much
thinner silicon layer (on the order of turn width, [104]). Moreover, with the present process
technologies and even more in prevision of SOI implementation for the passive devices, the
surface silicon stratum (n- epi-layer) is the only layer under the designer control and plays a
major role.
In all of the previous (and the next) VCO circuits, the upper few microns of silicon
substrate have been divided into several rectangular cells, 90°-oriented, by means of a minute
cubicle of trenches. Given the moderate silicon sheet resistance typical of this bipolar process
(10 Ω⋅cm), the excellent QL performance of these inductors seems to be primarily ascribable to
the efficacy of such a measure. In order to investigate this phenomenon, and maybe to squeeze
an even better quality factor performance by the integrated inductor, a new cubicle has been
designed. It is reported in Fig. 7-10.
176
Chapter 7
Layout of the new structures
Enhanced
cubicle
Fig. 7-10 2-layer 2-turn spiral inductor with modified trenches cubicle. The effect of the capacitive
coupling with the substrate, and of the losses in the surface epitaxial layer of silicon is minimized, and the
impact of this particular kind of loss will be finally quantified.
Only tee-like crossings were used for trenches; “crosses” have been carefully avoided,
because of process shortcomings that can otherwise hinder the correct etching (a sort of “funnel
effect”, the defect often spoiling the MOS memory cell manufacturing).
The granularity of the trench lattice has been further increased, by shrinking the unitary
cell from 7×4 µm2 down to 3×3 µm2, that is the lowest dimension allowed by the design rules.
The room left for the eddy currents to circulate is reduced; the area of magnetic flux coupling is
less than half, and the induced currents are expected to be lower. The new trench configuration
should then be a bit beneficial for both the parasitic effects on the effective L, and the resistive
losses.
We already noticed the importance of a correct orientation of the current-disrupting
domains, when Layout L was described. Even if the silicon epi-layer has been coventrized by
trenches, an additional effort was made to position the squares orthogonally to the overlying
metal turn; the cells are then rotated by -45°, 0°, +45°, +90°, and so on, to follow the octagon of
the inductor. At the junctions of the adjacent regions, and at the center of this pattern, the cubicle
is a little enlarged in order to honor the design rules.
A general consideration on the substrate problem has to be made. Contrary to the case of
the metal shield, in which patterning was a must, the HSB2-P30 substrate features a moderate
sheet resistance, and extremely high currents cannot be induced in it. The resistive loss is
computed as ISUB 2⋅RSUB, and has eventually shrunk. In conclusion, this issue is less important
than the metal shielding one.
7.2.8 Layout F – STARMAN with enhanced AAC servo-circuit
The VCO is now completed with the new AAC design discussed in Chapter 6. As Table
F depicts, the essentials of the oscillator have not been modified with respect to the preceding
layouts. In particular, the tank elements’ placement is identical to Layout A, whereas the
transconductor section shows minor adjustments: for example, the tail transistors have been
rotated to allow easier routing of the driving signal line from the diode of the Widlar mirror. A
zoom of the AAC layout is available in Fig. 7-11.
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Chapter 7
Peak detector
Layout of the new structures
Differential 1
PNP Current
reference
Differential 2
Fig. 7-11 Layout of the AAC: the peak detector on the left reads the envelope signal that has been
rectified immediately after the collectors, and routed in Metal2. The first differential stage reads envelope
voltage and reference, and filters them with the large capacitors on the right top. Then it feeds the second
stage, laid out inside it, that steers the fixed current coming from the PNP mirror structure to the right.
The two (F12-F4) transistors closest to the symmetrical tail make up the driving branch of the Widlar
mirror.
The floorplan of the circuit was chosen so as to keep the VCO active devices close to the
control blocks. The AAC loop analysis showed the criticality of the stability phase margin, then
the path lengths have been carefully minimized. For example, the peak detector used for
oscillation amplitude test purposes is not the one embedded in the feedback branch of the AAC:
it would be too far. The rectifiers (symmetrical B2 bipolars on center bottom of Table F) of a
specifically designed peak detector have been inserted exactly between the collectors, to avoid
any additional tank loading. To widen the room to place them, we moved the C-R decoupler of
the transconductor away from the vertical symmetry axis, after slight rearrangement of the aspect
ratio of the fixed decoupling capacitors of the tank.
The transistors of the differential pair preserve their horizontal alignment, and the line
crossover has been solved as usual. The rectified signal is centrally routed down in Metal2, to
drive the cascade of F12 diode and RPCP shunt to the right top. The aspect ratio of CP was
dictated by the arrangement of the other elements of the AAC.
The two following differential stages have been folded one into the other, to enhance the
symmetry that was required by the analysis in Chapter 6 especially for the former stage. The first
differential pair, working as reference comparator and amplifier, is kept outmost. The tail
generator is a simple B6/298 Ω-resistor series. Under the collectors are the 6 kΩ resistors setting
the dominant pole of the loop; the large CL capacitor, split in two symmetrical parts, is laid out to
the right. The second differential acts as current switch on the branch driving the Widlar; the
bases are driven directly by the facing collectors; the tail source requires a 17.5 kΩ resistor, that
is obtained with the cascade of two polysilicon devices, put aside the former stage’s
degeneration. To better compose this line-overcrowded zone, the Metal1 connection between the
178
Chapter 7
Layout of the new structures
two halves of the resistor crosses over the polysilicon of the first stage tail resistor. The current
reference and final driver comprise the three bulky PNP bipolars visible in the yellow square.
The F12 diode of the Widlar mirror is degenerated by the 1.9 kΩ above, whose tolerance
was tightened by manipulating the DIVA DRC program parameters. The diode is protected by
the F4 in feedback, near the upper ground rail. The two stabilization capacitors occupy the top
right corner of the AAC region, and are separated by the Metal1 rail that supplies the remainder
of the control system.
The Widlar AAC ground has been separated from the VCO ground. They will be tied
together once at the board level [101], where the bounce of the first circuit will no longer affect
the other one, since bypass decoupling capacitors will be placed near the chip. The supply rail is
common instead, so that an ECL-like power supply steering is finally realized. The voltage bias
for the servo-circuit will be provided from outside the chip, therefore it will be carefully filtered.
Moreover, the improved symmetry of the circuit layout is expected to abate the transfer of
common noise coming from the bias (CMRR enhancement). The regulator design in Chapter 6,
and Figs. 3-1 and 3-2 comparison in particular (with ideal a bias and not), highlighted how
important these former stages are, from the AAC noise standpoint.
7.2.9 Layout G – STARMAN with enhanced AAC servo-circuit and
Noise-filtered current sources
In Chapter 5 we noticed that the noise affecting the early stages of the control loop was
especially detrimental for phase noise performance. Since this AAC deals with a very high
frequency input signal, it is possible for the ripple to find the way to couple to the first stages,
possibly generating noise folding in the AAC and unwanted 2ω0 harmonic component in the
VCO tail driver. Once such a tone is beaten with the oscillation, additional undesirable noise
folding could occur in the VCO either. To avoid this signal’s return onto the voltage reference
line, and thus its back-propagation to the other stages towards the crucial amplifier nodes, two
counteracting techniques can be pursued:
• drive the tail generators through buffer stages, to decouple them one from another
• lowpass filter the base control lines of the generators.
RC filters
Fig. 7-12 The AAC layout improved with three R-C passive filters onto the bias lines of the current sources,
used in the AAC as active degeneration loads (see Table a).
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Chapter 7
Layout of the new structures
The first method is less area-expensive, but adds the noise of the buffers to the current
sources. The second one applies a technique more typical of microwave environment, anyway it
does not require too high a value for both R and C, since we want the reverse-filtering effect to
hold for spurs lying near 2ω0. A good tradeoff has been found by using C = 3 pF and R = 100 Ω,
risen to R = 1 kΩ for the single-ended last stage. Making this choice has safeguarded the
additional noise and base voltage drop due to resistors. The pole is located at 530 MHz; higher
frequency components coupling to the base electrode are shorted to ground by the capacitor.
Fig. 7-12 shows the three R-C filters added to the original AAC structure. The symmetry
properties of the layout have been maintained, since the filters are placed at the bottom of the
circuit where all the generators were located. The adoption of metal-on-poly crossovers allowed
for smart routing of the additional lines needed.
7.2.10 Layout Q – STARMAN with enhanced AAC servo-circuit and
Metal1 patterned shield
Just to permit the performance comparison of VCOs on a fair basis, the previous circuit
has also been completed with the best inductor shielding; i.e., the Metal1 plane patterned with
radial cuts.
7.2.11 Layout H – Mirrored Colpitts
Another circuit that will be tested in this run is the mirrored Colpitts-Clapp oscillator
proposed in Chapter 6. Its structure allows symmetrical layout, and such a characteristic has been
thoroughly exploited.
Fig. 7-13 The whole layout of the mirrored-Colpitts oscillator. The L-C1-C2 series develops vertically
in each column, with the 4 transistors of the transconductor positioned between the capacitors and the
180
Chapter 7
Layout of the new structures
current source situated on the top. For sake of compactness, the differential buffer is laid out along the
central symmetry axis of the circuit. The peak detector exits instead from the bottom of the structure.
Of course the starting point has been the inductor, whose structure has not been modified.
Nevertheless, whereas all the circuits discussed up to now were VCOs, here a pure oscillator is
described: it does not use varactors. This feature permits to fully include the oscillator in the void
between the spirals, free from substrate-fragmenting trenches; the output buffer was also
embedded there, thus the final layout has a very compact appearance. Because the decision
whether to design the peak detector was taken only during the final steps of the project, for our
convenience it has been placed far from the other blocks. The common “dirty” ground rail has
been supplied to both the top and bottom parts of the chip.
Each of the halves of the Colpitts schematic includes 4 transistors tied to a series
connection of capacitors. The layout respects this geometry: the 4 F12 BJTs stand in the middle
of the lower C2 = 1.2 pF capacitor, and the big upper C1 = 10.8 pF one. Their emitter is a critical
node: the current signal coming from the LC tank shall not see resistive paths before arriving to
C2, that shunts it away in reactive fashion - hence leaving the Q unabated. The emitter, along
with the current sources collectors and the tied plates of the capacitors, is therefore implemented
in Metal2; the connection is realized by sharing a unique Metal1 plate that runs from top to
bottom of the structure. The current generators feed the transconductor via the lower plate of C2;
thanks to the trick they can be kept far from the common-base transistors, the “tail” biasing
resulting much easier. The collectors join the Metal2 net through via12 arrays; the plate
completely covers the transistor, hence they are tied together virtually without resistance
addition. The degeneration resistors are designed as wide as possible, to account for the
reliability purposes mentioned in Layout A. With the given capacitors and the parasitics of the
inductor, the oscillation frequency is set to 3.6 GHz for the reasons discussed in Chapter 6.
Instead of occupying precious silicon space on the vertical symmetry axis, the two
common-mode damping resistors for C2 have been split in two parts, which are put aside the
capacitors. The horizontal Metal1 line that breaks up the contact tier provides shunting. The
same method has been followed for the base resistors of the transconductor, which were kept
even larger, and inserted near C1.
The oscillation output has to be read from the C1 capacitors. The floorplanning chosen set
them in the bottom inner side of the oscillator structure; this facilitates the routing of the signals
towards the auxiliary peak detector, placed on the bottom of the circuit. However, the output
buffer must be designed in folded fashion, starting on the bottom of the central column and
providing the buffered oscillation towards the top. The biasing lines for the current sources are
brought to the transistors with paths far from the axis; the power ground is instead sunk from the
top on the vertical axis; the base biasing is on the axis too, but it lifts from the bottom side. Just
to mention one among the many problems of such a packed realization, note that all of these
signals had to be routed in Metal2, since on the circuit bottom the space to place the contacts is
not enough (in particular for the large vias23). Undermost, the two emitter followers are
designed. Their outputs drive the differential couple made up by two horizontal F12 transistors
per side, lying above them. The tail generators are always kept adjacent to the ground line on the
axis.
The final outputs (Metal2) run parallel to the ground line, which acts thus as a shield
between the two long paths, before being uplifted in Metal3 and fed to the bonding pad. For the
RF circuits, a larger space left between devices could in principle be beneficial in terms of
isolation [9]; especially in cases other than high-doping substrates [111]. On the other hand,
keeping devices closer helps achieving good matching characteristics. One solution of this
tradeoff is to capitalize on the symmetry properties of the differential schemes, and accomplish
181
Chapter 7
Layout of the new structures
the desired matching without excessive coupling increase; isolation could then be obtained by
carefully placing trenches, or heavy doping pockets, or similar purpose means available from the
technology. For example, the remarkable area occupation of the capacitors raises suspicion about
the risk they face, of picking up interference near the borders or capacitively coupling noise from
the substrate. The first design rule pursued to escape the substrate coupling was the avoidance of
polysilicon-Metal1-epi capacitor structures also available in HSB2. A much worse coupling is
expected for these devices, one plate of which is directly the silicon epi-layer. Each metal-tometal capacitor has been insulated into a separate silicon island, surrounded with continuous
trenches and an additional turn of n+ pocket. The pockets are connected together in Metal1, and
through the central contact array they are fixed to the buffer ground potential (that will be tied to
a whole copper plane on the final board). Where Metal1 had to be shortly interrupted (at C2
horizontal connection), at least the buried part of the pocket was continued; in fact, the noise
capability to slip inside the uniform shield apertures is well known [103] and was watched for.
7.2.12 Layout I – Mirrored Colpitts with improved-Q inductor:
Metal1 patterned ground shield
As witnessed by Fig. 6-32 of Chapter 6, the quality factor enhancement could bring, via
oscillation amplitude increase, effects on the Colpitts oscillator even more favorable than on
STARMAN-like VCOs. Of course, the substrate loss rejection by means of Metal1 shield has been
tried in this case as well.
7.2.13 Layout P – Mirrored Colpitts with improved-Q inductor:
Metal3-only spiral
The other improvement that we can try to impart to the oscillator is the Metal3-only
layout for spiral inductor, to reduce the capacitive parasitics towards substrate. The C1 capacitors
are directly fastened to the spiral in Metal3, then the modification does not entail changes to the
design.
7.2.14 Layout O – Mirrored Colpitts with improved-Q inductor:
Single-turn Metal3 spiral
The spiral made with the only Metal3, 3 µm-thick layer, and one single turn has been
used in the Colpitts case. Unlike in Layout C this time the oscillator cannot be tuned; the small
value of the inductance will thus cause the oscillation frequency to reach 4.7 GHz if C1 was
maintained to 1.2 pF. This would make it difficult to perform the measurements, because the test
board components on the RF output path (e.g., baluns and chokes) are no longer nominally
operated over about 3 GHz. Moreover, the performance of the test socket we plan to use will
proportionally degrade, making the results not comparable with those pertaining to other VCOs,
and consequently losing significance.
The value of C1 was risen to 4.8 pF; C2 passed only to 30 pF to avoid the area explosion,
keeping a ratio of about 1:6.25. The structure of the central column of the oscillator, where the
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Chapter 7
Layout of the new structures
main parts of the circuitry are concentrated, has not been changed. The inductor had to be
changed, then it was convenient to increase its horizontal width, and free up in such a way the
space needed for the capacitors to be enlarged. The additional inductance given by the straight
Metal3 extension should vary the predicted L value by a negligible amount. The horizontal side
of C2 was multiplied by 2.5, passing from 90 µm to 230 µm.
7.2.15 Layout E – Standalone STARMAN with central symmetry
While all of the previous implementations of the STARMAN-like oscillators featured
symmetry with respect to the vertical axis, Layout E has been designed symmetrical with respect
to a point. In Chapter 4 the importance of the noise affecting the tail current source was
recognized; the tail was qualified as the critical net of the VCO. This new layout tries to exploit
the advantages provided by a symmetrical floorplan, by placing the tail transistors scattered
around the center of the circuit, in common-centroid fashion.
First of all, the two spirals of the usual inductor have been split and mirrored, sideways
and upside-down; though the actual inductance of the new geometry is not precisely known, only
the small contribution due to the straight strip of Metal3 once connecting them will be lost. The
central frequency displacement is expected not to exceed few 10 MHz. The oscillator is tunable;
the tank has been split in turn, and as usual the fixed capacitor lies besides the inductor, and the
6-varactors array is attached. The biasing 5 kΩ resistor is one polysilicon device alone, this time;
the Metal3 ground line is routed from outside towards the core of the VCO.
In order to place the tail block in pivotal position, the transconductor must be moved
outwards. The three F12 bipolars are designed to facilitate the collector-to-tank routing, with a
large Metal2 contact; also, the emitters are connected to the tail by means of a Metal2 large line.
The connection of their bases is realized trying to equalize the signal delays between the
transistors. This is made to minimize the phase delay; from the results presented in [48], and more simply - from the well-known hard-limiter behavior, the importance of a transient steep
slope to minimize the phase noise can be inferred. The commutation uncertainty is worsened by
operating the transconductor in cascaded manner, i.e. having the BJTs driven in cascade. This is
just the effect happening when the bipolar bases are routed over the devices, and drive them in
sequence. The parallel connection proposed in this implementation, and zoomed in Fig. 7-14, at
least partially eliminates this potential source of phase noise degradation.
Fig. 7-14 Snapshot of the parallel connection of the three transistors of the transconductor. The
routing-over-the-cell strategy is accurately avoided, because it can lead to skewed driving of the active
183
Chapter 7
Layout of the new structures
element of the oscillator, hence degrading the switching slope at the zero crossing – the crucial instant,
for what concerns phase noise [20].
A 120° disposition would have been best, but the proposed layout has to trade-off with
many other connectivity constraints.
To reach the transconductor halves in their mirrored locations, the length of the capacitor
of C-R coupling has been extended till near the opposite BJT bases. The Metal2 cap plate
connects to the relative resistor, and then to the input of the crossed bipolars. Since the symmetry
type has changed, the problem of avoiding the line superposition at the crossings no longer
exists. The transconductor external bias is highly crucial, then it is furnished to the two 2 kΩ
resistors starting from the center of the structure. The same care is devoted to the tail bias
distribution: the signal joins the center with a Metal2 line, then passes in Metal1 to drive the four
F12 of the tail. As usual, the emitter-bridging 1.5 pF capacitor is divided in two parts, and the
two halves of the tail see both plates (Metal2 and Metal3) of these passives. The 4-side fashion
connection allowed placing the components without resorting to undesired bridges.
The differential couple has been comprised into 2 isolated zones; the entire tail fits into
another central island of silicon. The sides of the bulk facing the tank were provided with a
doped pocket, that can be biased at will from outside the chip; the isolation has been further
strengthened by including the whole circuit within another trench, which features an additional
n+ well barrier. The pocket bias, along with the other references and even the supplies
themselves, is often doubled in order to be appropriately routed to the chip (see [112] about the
importance of achieving reduced bonding inductance for the guard rings). Unfortunately, the
main drawback of this symmetry is the difficulty to manage the signal lines, from the external
interface standpoint. They have to join the circuit from both sides, as the high density of the
median part impairs the routing over the circuit. The tuning voltage has been provided to the
varactor arrays from opposite corners, which will eventually be derived from the same pin.
Albeit the final part of the routing is symmetrical in principle, the lines must travel long around
the chip, and could produce crosstalk and interference with the nearest circuits. The outputs are
most important: the two balanced lines ought to be laid out in close proximity until they reach
the output buffer. In this case, the buffer is instead placed on one side of the VCO, and the output
paths are necessarily not equal: symmetry went lost in this last signal transit. Anyway this circuit
topology can prove useful if the trailing stages could be in turn realized respecting the central
symmetry. For example, when the VCO drives the frequency divider in a PLL, the two path
lengths can be equalized and digital differential logic such as DSL (Differential Split-Level
logic, [99],[103]) could be adopted on both sides of the VCO. As a last resort, dummy cells
could be issued in order to balance the output paths.
The outlet driver is almost equal to the ones presented previously. The peak detector is
designed prior to the differential buffer, so that only the Metal1 line carrying the rectified
oscillation is travelling towards the RPCP filter, and does not suffer from the imbalance of the
path.
7.2.16 Layout J – Synthesized inductance tunable oscillator
By following the same design principle (derived from the Q-loading analysis of Chapter
2) that led us to develop the mirrored-Colpitts oscillator, another trial has been done to drive the
transconductor from the emitter rather than from the base. A seen in Chapter 6, the alternative
circuit adopts a nearly-Colpitts mirrored structure, but the collectors are now crossed to drive the
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Chapter 7
Layout of the new structures
capacitor series on the opposite branch. Moreover, the bases of the transconductor BJTs are no
longer tied together and connected to a common resistor, but to an external voltage reference
through an integrated inductor.
The feasibility of such an oscillator has been tested by means of the layout in Fig. 7-15.
Fig. 7-15 Layout of the synthesized inductor structure. The topology repeats basically the one of the
Colpitts in the right part, and attaches the larger base inductors coming from the left; this entails the
complete reversal of the floorplan of the output buffer.
The topology of the top part is quite similar to the Colpitts scheme of Fig. 7-13:
capacitors and active devices occupy the center of the floorplan, and the output buffer lies on the
symmetry axis. This time, the bottom of the circuit is however devoted to the large base
inductors, and cannot be conveniently used as entry for the external biases. The block placement
of Colpitts Layout-H has therefore been repeated upside-down, so as to provide the voltage
references line from the top, and to get the balanced outputs at middle height of the circuit.
The variation implied a number of additional line crossings; for example for the buffer
power supply, now descending in Metal3 from the top, and the buffer ground, routed centrally in
Metal1. The blocks are located nearly as in Colpitts case: the broad Metal2 plate used to connect
the transconductor emitters and the capacitors was kept, for instance. The line crossing due to the
new schematic topology has been managed as illustrated in Fig. 7-16.
185
Chapter 7
Layout of the new structures
From the
inductor
From the
inductor
Fig. 7-16 Management of the line crossing in the synthesized inductor scheme. The lines coming from
the tank inductors could be routed along the opposite sides of the bottom capacitors without actually
cross each other. The detail of the guard ring on the perimeter of the capacitors, and also shielding the
transistors of the transconductor from the other nearby blocks, is apparent in the picture.
The terminal coming from the tank inductor, after contacting the collector of the
transistor on its own side, is routed in Metal3 to reach the C1 of the other side. The paths are
symmetrical, and the two output lines in Metal2 at the center of the image are thus kept balanced.
In order to shrink the vertical space unused between the two inductor couples, we decided not to
put the peak detector in the middle of the layout, but to place it apart (bottom side of Fig. 7-15).
For, by keeping rectifiers very close, we have to route only the Metal1 line carrying the nearly
constant envelope voltage; the long line adds some parasitics to the CP capacitor, but they are
negligible in percentage. Note that the peak detector line has been extended on both sides of the
layout even if the RPCP shunt is only placed towards the bottom: this helps improving the overall
symmetry, and makes the ripple a common-mode interference for the base inductors. The same
arrangement has been applied to the current sources biasing coming from the top.
In Chapter 6 the tuning capability provided by the synthesized inductance control was
described. By extending the ideas leading to define the sensitivity coefficient KTAIL, the
importance of the tuning current cleanliness (direct stability) emerged. The line controlling the
tail sources is therefore brought from the VCO top to the transistors, assuring the shortest path
length, and placing it on the axis.
The bases of the transconductor BJTs are carried towards the nearest terminal of the
bottom inductors remaining in Metal1. The discussion developed in Chapter 6 indicates that the
base spiral must be greater than the one in the LC tank. As the highest known inductance is 680
pH in our layouts, the only way to increase the L without diverging in real estate consumption is
to put two spirals in series. From other tests performed by ST on passive devices we learnt [113]
that the mutual inductance coefficient k is very low, unless full or partial internal-area-sharing
spirals are designed. Even by bringing the two spirals moderately near the mutual term keeps
little relevance. The other electrodes of the base L are tied together, and biased through the line
entering at bottom.
The vertical dimensions of this layout are nearly double the ones of all the others (1300
µm, against 800 µm typically). The Layout J will be therefore placed on a special die, where the
many bonding pads set free will be connected in parallel to reduce the bonding inductances.
7.2.17 Layout K – Differential-tuning STARMAN
Last but not least, a conventional STARMAN-like VCO scheme with the usual inductor,
tank and active circuitry has been laid out. In this configuration, the tuning node is not obtained
186
Chapter 7
Layout of the new structures
“as is” from outside; the alternative varactor tuning technique outlined in Chapter 6 has been
implemented.
The two current mirrors that perform the tuning signal inversion and voltage limitation
are placed at the two sides of the transconductor. The distance from the active VCO blocks has
been set rather high, to prevent coupling problems on such a sensitive node. The layout can be
anyway greatly compacted, provided an appropriate isolation of the mirrors is realized; the
present placement is for test convenience only. The output of each half-driver regulates the
voltage of its own tank capacitor net, as shown in Table b; the plate to be piloted is the one
facing the varactors, in Metal3, then it is sufficient to connect the mirror output to the outer side
of the decoupling C. Thus the central string of resistors has been eliminated. The tuning node
feeds the varactors’ cathodes from the top, as usual. The supply lines have been routed down
from the upper rail, together with the tuning signal whose branches embrace now the whole
VCO in symmetrical fashion. A 2 pF capacitor is placed on the derived lines, to filter the tuning
voltage.
7.2.18 A tentative layout in MOS technology
Since we were given by STMicroelectronics the possibility to test an automatic
component sizing software, we decided to exploit this opportunity by implementing a widely
used structure of MOS VCO, depicted in Fig. 7-17a. It is a cross-coupled differential scheme
with floating inductor, supplied by a power MOS device; the output buffer is not shown, but it is
the MOS-translation of the bipolar circuit depicted in Table d, and features nearly the same
performance. After some simulations, the oscillator is expected to give A0 > 2.5 V when the
flowing current is ISUPPLY = 7.2 mA, and the power supply is VDD = 3 V. This is in agreement
with some similar configurations presented in [8],[87] and operated at lower voltages, with
roughly double the current.
a)
b)
Fig. 7-17 a) represents one well known CMOS implementation for a cross-coupled VCO. The layout in
b) adopts fixed, metal-to-metal capacitors, since no suitable junctions are available that can be
acceptably used as varactors in this technology.
The layout in Fig. 7-17b was drawn by the manufacturer’s designers. Notice that the
varactors are non-existent in this technology, and have been substituted manu militari by metalto-metal capacitors. As a matter of fact, this layout will not be diffused during the Run of July
187
Chapter 7
Layout of the new structures
1999, which is devoted exclusively to bipolar HSB2 technology designs. This circuit was laid out
instead in the new 0.35 µm CMOSF6Y technology.
7.3 Chip floorplanning and the I/O ring
The principle that inspired the global circuit floorplanning on the chips was repeatability.
Under the constraint that only one board design had to be performed, the VCOs have been placed
so that different splits of the same schematic were laid out in the same position.
The HSB2-P30 run has been finally organized in 6 test chips, 5 of which contain 3 VCOs
and the last one only 2 structures. The eventual dice arrangement is represented in Fig. 7-18.
H
A
I
B
O
H
F
C
Q
Chip I
Chip II
Chip III
P
E
D
K
Chip IV
L
J
M
N
Chip V
Chip VI
Fig. 7-18 The organization of the 17 bipolar VCO versions into 6 types of test chips to be manufactured
in July ’99. Homologous oscillators have been tentatively kept in analogous position within the test chips;
this also helps in the design of one single test PCB.
The complete chips constituting our contribution to the 07/99 run have been labeled with
roman numbers, and are correspondingly depicted in Tables I..VI. The overall dimensions of the
die were 3 × 3 mm2, allowing an effective silicon real estate as large as 2.4 × 2.4 mm2.
Let us clarify the I/O ring organization. There is a standard placement of the pads for the
package TQFP-48, whose geometry is reproduced in Fig. 7-18 and in the Tables aforementioned.
Each pad is attached to the ring of four Metal2 lines that encompasses the die active area;
starting from outside we find the VCC rail, the VEE rail, the FIELD rail (that ties the substrate to
ground) and the inner auxiliary ring, that we put to ground either. Of course, during our tests we
188
Chapter 7
Layout of the new structures
will operate one oscillator at a time, to avoid the undesired leakage of spurious harmonics around
the die; hence the I/O ring must be broken in 3 parts, one per each VCO.
The internal square of silicon is surrounded with a trench. Moreover, each VCO was
enclosed in a smaller silicon tab, delimited by trenches and shielded from the other circuits with
a series of adjacent substrate contacts, connected to VEE. The Metal1 ring that assures the
polarization of the contacts goes active only when power is supplied to the pertaining VCO. Of
course the Metal1 ring is not a closed structure but has been ripped up in two points, not to create
inductive loops.
This technology allows diversifying the bonding pads in three distinct categories: I/O
pad, VCC pad, and VEE pad. They basically differ in how the protection diodes connect to the
I/O ring. It is very important to remember that we chose to detach the output stages’ supply from
the normal VCO power: otherwise, the ring of metal lines will automatically short together the
two nets, thus impairing the implementation of our intention. Since the ESD (Electro-Static
Discharge) protection diodes will prevent the input voltages from overcoming the VCC provided
at their anode, and set via the VCC pads, obviously the VCC pads must carry the highest voltage:
i.e., the one fed to the output buffer blocks. The power supplies must be identified either as
output-VCC or VCO-VCC ones, in order to choose the correct pin style.
A systematical approach to the circuit placement, and consequently to the sequence of
pins to be issued, has been followed. The STARMAN-like versions show similar pin patterns
towards the I/O ring, and are always placed to the right of the die. The bottom left corner is
mainly exploited to accommodate the oscillators with AAC. The top left corner lodges instead
the Colpitts-derived oscillators. The orientation of the layouts discussed so far have been chosen
giving paramount importance to the output routing: the VCOs are laid so that the output lines can
reach the bonding pads following the shortest path. A very popular pad sequence used for RF
differential outlets is GND - SIGNALplus - SIGNALminus - GND, to leave the lines balanced and
shielded by the outer interferers. To better comply with the VCO layouts, however, we inserted a
dc signal (usually, the tuning voltage for STARMAN, and the tail bias for the Colpitts that features
reversed topology) between the RF pads: the symmetry is indeed left intact.
As a general rule, the corner pads have been used for the ground. This happened because:
•
•
•
the bonding wires are longest for such a fastening
the package performance slightly worsens there
to permit the p-substrate biasing to ground, that is accomplished with special vias at
the corners.
Wherever possible, the ground or other voltage references, were imported through two or
more pins and thereafter tied together, to lower the parasitic inductance (e.g. in Chip VI, as
permitted by the large number of unused pins available).
The line widths are nearly always proportional to the amount of current they have to
deliver (even if electromigration is not an issue for these test circuits). Were the VCO to be
integrated in a complete transceiver, a suitable routing and sizing approach would be anyway the
one proposed in [114], to counteract the substrate coupling by means of a smart distribution of
the power lines.
The outputs are designed with reduced width (6 µm) to diminish both the capacitive
loading and their coupling with the substrate. Sometimes the supply voltage lines have been
prolonged, seemingly in vain, beyond the net requiring power or ground: this can be seen for
example on top of the inductors. The bias of the current sources for the Colpitts stage apparently
shows such an arrangement, too. This measure was made to assure a symmetrical disturbance
pick-up by the line, that almost elides the interference. In Chip VI, the Metal3 line starting from
189
Chapter 7
Layout of the new structures
the third pin from bottom in the left side seems to be useless; in reality, its purpose is to
counterbalance the effect of the peak detector rail found on the opposite side of the base
inductors. With the same symmetry goals in mind, all the lines were kept as far as possible from
the inductors. 45°-diagonals could often be used instead of 90°-Manhattan routing for these
attachments, but the strict grid constraints discouraged us from exploring this chance. At least
the ultimate contacts of the metal lines with the bonding pads are realized in tapered fashion, to
ensure enhanced robustness.
190
Chapter 8
The test setup - design of RF boards
Chapter 8
The test setup –
design of RF boards
This last Chapter presents the design of two RF boards for the testing of the new chips for the
RUN0799. The structure of the cards is similar, with the pad ring of the chip placed at the center
and the service test points, and wrap-around circuitry and devices, scattered all around it. The
board for RUN0799 is provided with a manual load socket, since the test chips to be delivered
are in excess of 150 and direct bonding must be avoided. In particular, the issues of microstrip
impedance matching, proper grounding against EMI (Electro-Magnetic Interference) and line
bounce, and the choice of components are paid attention.
8.1 RF board for FRAME6
I
n Chapter 6 the chip FRAME6 was introduced, which was modified (with FIB
procedure) to permit the shutdown of the main PLL blocks. In order to execute the
definitive measurements on the 3 VCOs selectable inside the FRAME6 test chip, an
existent RF board [115] of the STARMAN project had to be redesigned. Fortunately, the package
of the chip under test was already TQFP-32; after consulting1, we decided that 12 over 32 pins
were to be reorganized.
The circuit schematic of the modified FRAME6 is outlined in Fig. 8-1, followed by:
• a brief discussion of the components that will be mounted on the final PCB
• the RF layout techniques adopted in the design.
1
Many precious indications about the modifications needed have been provided by Ing. F. Torrisi of
STMicroelectronics, while Ing. G. Cantone highlighted some especially critical issues in the board design; they
deserve here my grateful acknowledgment.
191
Chapter 8
The test setup - design of RF boards
U6
U3
C29
2
3
4
J18
VCC
1
C18
1
5
g sn
g g
g
4
5
6
VCC
3
GND
BalPort
UnbPort
GND
GND
BalPort
5
1
2
1
4
3
2
g
g g
sn g
C28
U7
BALUN
C17
S3
J16
S1
VCC
SW SPDT
S2
J20
C15
1
1
5
1
Plock
Xref
x1
outBUFF
T1
T2
VPdig
VRdig
S4
3
HFoutput
GND
2
C27
4
C12
Ub
VCC
NC
1
U5
TDA7425
X101
U9
g
g g
sn g
1
4
3
2
C30
1
24
23
22
21
20
19
18
17
U4
VCC
g
g g
sn g
J3
5
1
16
15
14
13
12
11
10
9
VCC
Vclt
VbOSC
Vpeak
VpeakOSC
en
s1
s2
CAP2
selectVCO
LF
VRpll
CPadj
CAP1
CAP0
VRpll
VPpll
1
2
3
4
5
6
7
8
VPpll
noutPPA
outPPA
VPpll
Vreg
VRpll
GainAdjPPA
enPPA
CON1
U8
25
26
27
28
29
30
31
32
1
J17
C16
VCC
J7
RV1
C4
4
3
2
J4
VCC
1
C13
C14
RV2
1
C5
2
1
T1
V4
GND3
S2
GND2
X1
V3
V2
S1
GND1
V1
VCC
15
14
12
8
9
VCC
1
5
4
V5
GND
7
GND4
T2
10
GND5
Vcc
1
VccIN
VCC
2
3
U2
11
C6
13
C3
J12
U1
J5
1
VCCin
J19
R3
VOLTAGEREG
J15
1
6
3
SW101
Fig. 8-1 Circuit schematic of the RF board needed to test FRAME6.
8.1.1 Preliminary design choices
The printed board will be constituted of 4 copper planes. The outer planes will be used to
route the signals (TOP layer), or solely to assure rugged support for the final solder step (the
BOTTOM layer); the inner metal planes will be traceless, and used exclusively for ground and
supply distribution. In such a way, the supply steering has virtually neither parasitic resistance
nor inductance, since the supplies are accessed through a tiny in-site via: this is very important
issue to consider for RF cards. Next Figs. 8-2 and 8-3 effectively highlight the beneficial effects
of such a design practice against electro-magnetic interference (EMI) that couples to the circuits
on the board.
The indirect grounding provided to the SMD sample filter by the simple surface tracks
laterally joining it (Fig. 8-2a) does not cancel out the spurious tones affecting the signal line:
192
Chapter 8
a)
The test setup - design of RF boards
b)
Fig. 8-2 The scarce rejection of the electromagnetic interference (EMI) vs. frequency, b), when only a
superficial ground routing is guaranteed on the board , a) (after [116]).
The undesired harmonics get instead quenched, once the more effective ground contact
provided by the under-plane vias of Fig. 8-3a are realized near the component:
b)
a)
Fig. 8-3
The remarkable improvement in the insensitivity to the EMI, in b), when a ground/power
distribution strategy is organized around an entire copper plane, to be connected to the routing layers by
means of in-situ via holes, a) (after [116]).
Moreover, the two internal layers will act as insulation for the signals carried onto the
external planes, besides automatically implementing a bypass capacitor with the parallel metal
planes - featuring rather reduced capacitance-per-area, but of very high quality. For the
fabrication of this board, a manufacturing process was used that does not create a homogeneous
copper pour, while instead giving a tiny-spaced web of 90° copper wires that is electrically
similar to a contiguous metal deposition. Only a little degradation in the isolation from external
interference and ground bounce rejection is therefore expected.
8.1.2 The rationale behind the physical PCB design
The electrical network tied to each of the 32 chip leads is reported below, following the
pin disposition from 1 to 32, in clockwise fashion.
193
Chapter 8
The test setup - design of RF boards
8.1.2.1 Left chip side
Pin 1
– Vctl
:
output of the AAC associated to the VCO2. It can
be tied to the tail current source of the oscillator, closing the loop, or left floating; a soldernail
makes it readable with a standard tester
Pin 2
– VbOSC
:
driving input of the tail generator of VCO2. With
one soldernail, adjacent to the one mentioned above, it makes up the S1 switch that can be
shorted with a simple metal cap (to set close the AAC loop) or left open (to directly operate the
tail current source externally). Another jack is placed just near, for ease of reading bias voltage
(indicated by Vbosc in silk screening)
Pin 3
– Vpeak
:
input of the differential stage of the AAC
(reference comparator and error amplifier), connected to a soldernail
Pin 4
– VpeakOSC
:
output of the peak detector of the AAC for
VCO2. Like for Pin 2, the AAC loop can be closed or the loop amplifier can be driven from
outside, by simply commuting a mobile short-circuit cap (switch S2). The peak detector output
can be read by means of the test point Vpeak
Pin 5
– PLLen
:
digital input for PLL enabling. After the FIB
processing was done, the analog blocks remained “on” also with PLL disabled, and the desired
measurements could be done. The voltage is regulated via the 10 kΩ RV1 trimmer (with filtering
capacitor C3, 100 nF) and can be read through the associated PLLen test point
Pin 6, 7
- S1, S2
:
these are the selection bits to choose the active
VCO (the sequence is reported in [117]). Since there are 3 more digital entries in the chip, but
located on the opposite side, the controlling DIP-switch SW101 was laid out near the right side of
the PCB. The routing for these two signals results rather long and was performed on the back
plane of the card, but since these are digital signals the board performance is left unaffected. The
traces avoid passing between the SW101 pins because they are spaced with standard pitch (100
mils, or 2.54 mm; mil is for “inch thousandths”, i.e. 1 mil = 25.4 µm), and the clearance
tolerance will be violated
Pin 8
- CAP2
:
it is the connection with the external capacitor
setting the dominant-pole for the VCO2 AAC loop (C15, whose value will be near 220 nF). By
changing the element (soldered or not) the AAC behavior could be examined, much like in the
STARMAN-CUT1 and CUT1.1 boards where the noise was injected from this 30 kΩ-resistance
node. The Cap2 soldernail has been added to ease the operator access to the node.
8.1.2.2 Bottom chip side
Pin 9
– VPpll
:
the positive analog power supply of the chip. One
via connects it to the second plane of the board; since this is a critical node for the voltage
stability and cleanliness of the signals in the whole IC, it gets filtered by a 100 nF bypass
ceramic capacitor (C4) mounted very close to the lead
Pin 10, 14 – VRpll
:
the negative analog supply of the chip, directly
connected to the GND plane by a via
Pin 11, 12 - CAP0, CAP1
:
as for Pin 8, the AAC of VCO0 and VCO1 can be
filtered. C13 and C14 will be removable, and usually set to 220 nF
Pin 13
– Cpadj
:
the trimmer RV2 (50 kΩ maximum) is used to
adjust the PLL charge-pump filter duty cycle interval. It will be kept to a nominal position of 17
kΩ
194
Chapter 8
The test setup - design of RF boards
Pin 15
– LF
:
the charge pump filter load. The second-order
loop filtering is accomplished through the well-known RC-C shunt connection (namely, R3 and
C6 will give 5.6 kΩ × 47 nF, and C5 will be 2.2 nF). The external readability of the voltage is
allowed by Vtune soldernail. The entire element group has been kept very close to the chip, since
the interference coupling with this critical node generates highly detrimental effects on the
output phase noise
Pin 16
- VCOsel
:
this is the output that let us control the correct
VCO selection, when the PLL reference frequency varies. In fact, the 3 VCOs are tuned at
slightly different central frequencies ω0, so as to overlap their tuning ranges and cover a wider
frequency interval. An internal frequency division could be performed by properly setting the
digital T1 and T2 pins; however, this is beyond our measurement aims. The pin output is based
on the on/off charge pump states monitoring, and is available on Nvco soldernail
8.1.2.3 Right chip side
Pin 17
- Vrdig
:
digital ground, immediately routed to its relative
plane with a via, located right under the chip
Pin 18
- Vpdig
:
digital power supply, connected to its internal
plane and bypassed with C12 (100 nF)
Pin 19, 20 - T2, T1
:
two control bits that set the chip’s functionality
(test mode, normal mode, etc.). They are set by the SW101 DIP-switch and loosely routed on the
top of the board, but enjoy anyway a high noise immunity
Pin 21
– OUTbuff
:
it is the output of the frequency-phase detector
(FPD) of the PLL. Although this signal is a square wave as slow as 2 MHz, for sake of the PCB
uniformity it has been exported by means of SMA female plug (labeled with FPD in Fig. 8-7),
after the DC decoupling achieved with C27 (1 nF). The SMA export of the signal is realized by a
trace joining the drill hole prepared for the central connector; the 4 square-shaped outer contacts
will be connected to the ground plane, thanks to the 4 big thermal reliefs that stand out clearly in
Fig. 8-8c – “GND metal plate”. Thermal reliefs of course assure the electrical contact, in 4
points, but minimize the thermal conductivity of the inner pad; this permits to shorten the
soldering time, and consequently to limit the thermally-induced damage on the PCB surface.
This trace features standard width (12 mils, or about 0.30 mm) as drawn from the chip
lead. Such a dimension is used for all the traces that do not need impedance matching, all over
the board. After the decoupling capacitor with standard EIA-0805 footprint, the solder pad
introduces anyway a mismatch on the line: at least the final stretch leading to the SMA plug has
been matched to 50 Ω, by tailoring the width in the way discussed in Paragraph 8.3.1
Pin 22
- x1
:
digital input, driving the frequency divider that
processes the external clock before delivering it to the FPD of the PLL. Our measurements were
performed always at 16.384 MHz and with x1 set to zero logic level. The final arrangement for
the 5 switches of the SW101 used, illustrated in the picture of Fig. 8-9, is then:
Cyan
Green
Yellow
Orange
Red
T1
T2
X1
S2
S1
195
Chapter 8
The test setup - design of RF boards
Pin 23
- Xref
:
external clock reference; it can be 16.384 or
18.432 MHz. The switch S4 lets us choosing between a crystal oscillator (X101, in rectangular
package and 4 leads) or a sinusoidal generator coupled from the SMA inlet Xref (with the series
capacitor C30, 100 nF). The adoption of a simple switching cap for S4 is still convenient at
frequencies of the order of tens of MegaHertz, as demonstrated by analogous test boards
previously realized in STMicroelectronics
Pin 24
- Plock
:
this digital output signals the lock status of the
PLL (lock achieved = Plock high) and is provided out with the Plock soldernail.
8.1.2.4 Top chip side
Pin 25
- VPpll
:
analog power supply, to be connected with the
layer PWR and filtered with a local bypass capacitor
Pin 26,27 - noutPPA, outPPA :
these are the balanced outputs of the circuit. The
output power pre-amplifier (PPA) receives the oscillation from the VCO, already squared and
divided by 2 in frequency (i.e., at about 1.3 GHz) and rises the power up to -10 ÷ -5 dBm over 50
Ω-single ended. The differential signal is converted to single-ended in order to read the phase
noise with the HP8593E spectrum analyzer. The conversion takes place thanks to a
LDB20C201A1500 Murata microwave balun [118], a SMD component with ±100 MHz
bandwidth centered around 1.5 GHz, 200 Ω of differential input impedance and 50 Ω matched
output (element indicated by U3 on the board). Fig. 8-4 reports a picture of a similar device and
the essentials of this element, as furnished by Murata catalog:
Fig. 8-4 Photograph of one type of discrete SMD balun, and mechanical and electrical characteristics
of the component (after [118]).
The input traces joining the balun are AC coupled via the C16, C17 1 nF capacitors in
order to avoid the DC short of the PPA outputs through the primary balun winding. The output
trace voltage is referred to ground (the two vias on top of the U3 balun in Fig. 8-7,
asymmetrically laid out) and is decoupled in turn, with the 1 nF C28, from the SMA plug OutU.
It is of fundamental importance to exclude DC offsets from the output, because the spectrum
analyzer does not stand steady voltages; a coaxial capacitor of 66 nF was always inserted before
the analyzer N-plug during the measurements. The value of 1 nF is chosen since 1 nF⋅100 Ω (50
Ω balun out + 50 Ω SMA impedance series) gives a 1.6 MHz pole, after which the signal passes
unaltered.
By knowing that each branch of the balun presents 100 Ω impedance to the input, and
that the PPA driver shows 80 Ω output impedance [117], we synthesized an intermediate value
of the characteristic impedance for the track. The typical gradual tapering of the line would have
196
Chapter 8
The test setup - design of RF boards
been impossible with our PCB technology; our solution is instead based on a simple “λ/4
transformer” principle, that allows us to match two different Z0 lines with a trace junction
featuring Z 0 = Z1 ⋅ Z 2 impedance. The tapering was then realized in a geometrical average
sense. The mean between 80 and 100 Ω comes about 90 Ω, which were practically obtained with
a 0.19 mm-wide trace, as explained in the next 8.1.3 Paragraph.
A further issue is symmetry. To keep the output balanced, two short and perfectly
mirrored traces were designed from the chip till the balun. The only exception to balancing is the
C29 (1 nF) that leads to the OutB plug, that was requested in order to try the single-ended
measurement of the signals before the balun
Pin 28
- VPpll
:
this supply feeds the internal voltage regulator
that biases the PPA. In fact, due to rush fabrication requirements the final amplifier belonged to a
3 V-library cell, against the 5 V supplied to the global board
Pin 29
- Vreg
:
output of the integrated voltage regulator for PPA
biasing. It calls for a 100 nF (C18) capacitor, and can be monitored through the Vreg soldernail
Pin 30
- VRpll
:
the regulator dedicated ground
Pin 31
- GainAdjPPA
:
power control for the PPA buffer stage, must be
always high to 3 V. It is tied directly to Vreg, passing under the chip
Pin 32
- enPPA
:
connected to switch S3, it allows to turn on and
off the PPA; during the test operations it will be always active in order to read the VCO
oscillation.
The external power voltage can be directly fed to the PCB via the VPpll and VRpll
soldernails. In addition, the board might be supplied through a 5 V voltage regulator, for
example LM78L05ACH, requiring at least 7 V on the V+ soldernail. Aluminum or tantalum
SMD capacitors are usually required by this IC, and three large, solder-resist-free metal pads
have been prepared on the TOP layer for this purpose. Even if the regulator is not mounted, it is
anyway preferable to attach the VPpll-VRpll bypass capacitors, to enforce the local bypass
capacitors already put in place near the chip leads.
8.1.3 Trace-matching issues
The two oscillation outputs travel from a 80 Ω voltage source (PPA final follower stage,
with both differential and common-mode feedback) to a 100 Ω single-ended impedance featured
by the balun. The structure of the line is indeed a conventional microstrip, air-on-dielectric. In
order to figure out the trace width needed to assure the 90 Ω characteristic impedance for
matching the intermediate line, we shall know the parameters of the board dielectric: FR4Multistabil [119],[120]. It is a non-hygroscopic epoxy stratification with high dimensional
stability (< 4.5 mm/mm/°C up to 125 °C, peak temperature of operation); hence the microstrip Z0
will undergo negligible variations with temperature. This information is useful when making
climatic chamber experiments, such as the ones in Appendix B. The dielectric loss is tan δ =
0.019, compliant with the MIL-P13949 rule that applies to this kind of devices. The data needed
for the calculations are:
• relative dielectric constant εr = 4.5 (typ @ 1 MHz)
• the total board thickness, H = 1.6 mm
• the surface copper thickness of the tracks, t = 35 µm
The thickness of the effective dielectric section for the microstrip is (Fig. 8-5):
197
Chapter 8
h=
The test setup - design of RF boards
H − 4t
= 486.7 µm
3
0.4867 mm
1.6 mm
(8.1)
35 µm
Fig. 8-5 Stratification and thickness of the copper layers.
The Z0 computation was based on microwave theory formulas for the microstrip on
homogeneous substrate. An effective width weff is defined, that depends on the trace thickness t;
the effective dielectric constant εeff accounts for the heterogeneous dielectric around the track
(air-FR4), however without considering the inclusion of frequency dependence (after Getsinger)
and is influenced from w. Finally, the Jansen’s approximations for Z0 in the two different weff /h
aspect ratio situations are found. In our case, we have combined three estimation expressions
taken from the manuals [88],[121]:
weff / h = w / h +
ε eff =
1.25t æ
2h ö
ç1 + ln ÷ w / h ≥ 0.159
t ø
πh è
εr +1
εr −1
+
2
2 1 + 10h / weff
60
ì
Z
=
ln(8h / weff + 0.25weff / h )
ï 0
ε
eff
ï
í
ïZ 0 = 120π [weff / h + 1.393 + 0.66 ln(weff / h + 1.444)]
ïî
ε eff
(8.2)
(8.3)
weff / h ≤ 1
(8.4)
weff / h ≥ 1
Notice how weff depends in general on the w/h ratio in turn; h is about 500 µm while the
final width w is expected to be much superior to 80 µm, and only the (8.2) formula is adopted. A
Matlab routine solves the formulas in cascade and plots the impedance behavior, for w values
198
Chapter 8
The test setup - design of RF boards
ranging from 0.1⋅w/h to 10⋅w/h. Fig. 8-6 depicts the results obtained when the nominal spread is
applied to the εr (3.5 < εr < 5.5); it has been used as operational diagram for the choice of w.
120
ε =4
r
Z0 [Ohms]
100
90Ω
80
ε =4.5
r
ε =5
r
60
50Ω
0.19 mm
0.85 mm
40
1.00E+2
1.00E+3
W microstrip
[µm]
Larghezza
pista
[um]
Fig. 8-6 Nomograph obtained by the application of the (8.2)-(8.4). Once the desired characteristic
impedance Z0 is known, for the given type of dielectric and thickness, the width of the surface microstrip
is read on the abscissa intersected on the curve.
The scattering of the curves is rather low, in fact the 25% spread of εr impacts onto Z0
only through a square root. The circle and cross indicate the 90 Ω and 50 Ω widths set up in the
Orcad design:
• the 50 Ω traces used towards the SMA plugs will be 0.85 mm wide (33.5 mils)
• the 90 Ω traces leading to the balun input will be instead of 0.19 mm (7.5 mils), in the
second range of the Jansen’s equation
The standard width of the lines, as well as the standard line spacing, is around 12 mils;
the latter dimension obtained is therefore very near the limit that calls for costly laser
manufacturing.
It is worthwhile to observe that the other constraints that must be verified during the
microstrip design are fully satisfied, thanks to the relatively low frequencies involved in the
project. Namely:
1. the losses caused by air radiation and surface waves emission are negligible till
λ0
> 4 εr
h
(8.5)
At 1.5 GHz the light wavelength in free space is λ0 ≈ 20 cm, and the condition is by far
verified
2. the second transmission mode of the microstrip waveguide is not excited when
λ0
> 2 εr
w
(8.6)
that does not impose limitation again
199
Chapter 8
The test setup - design of RF boards
3. transversal resonance modes (that usually ignite for very low values of Z0) are again
prevented by the low value of w with respect to λ0.
8.1.4 Physical design of the PCB
The final design of the board has been produced with the Orcad® Layout+ suite. The
circuit implemented is concentrated all around the test chip; the TQFP-32 package helps in
distributing the external components in even way on the board, much like the analogous board
presented by Abidi in [73]. The only privilege was reserved to the output paths, kept symmetrical
and as short as possible.
The footprints of many components were built-in in the default libraries of Orcad. In
order to lay out the other elements, and upgrade the footprint list, we resorted to:
• for the DAB FRAME6 chip: mechanical specifications of TQFP-32 packaging with gullwing leads
• for the DIP-switch: SCS-G-023 Erg series mechanical dimensions
• for the trimmers: Cermet 3224W Bourns series
• for the SMA plugs: standard size, as found on RS catalog
• for the balun: Murata on-line catalog
• for the optional quartz: TQSMT series of Tele Quarz
Automatic routing of the paths was then performed, after that some obstacles to redirect
the first-trial solution were placed around the balun and the charge pump external filter. The final
via placement and trace tailoring has been hand-made, following these former router attempts.
The final product is a board having total dimensions of 87 × 75 mm2, then the decoupling
capacitance between the supply planes can be computed:
87 × 75 mm 2
C supply layer = ε 0 ε r
= 0.55 nF
(8.7)
0.49 mm
The final version of the PCB for FRAME6 VCO testing is represented (in Massteck
format) in Fig. 8-7, together with the drill specification:
Fig. 8-7 Global view of the multilayer final board (blue = top layer traces, red = bottom layer traces)
and drilling table.
200
Chapter 8
The test setup - design of RF boards
The Orcad file can be compiled, and the information contained in it can be split into
many levels, corresponding to the steps of the manufacturing sequence. Hereafter we present the
standard Gerber format for the Computer Aided Manufacturing (CAM): each of the files stores
the geometrical data needed to produce the 4 copper layers, the silk screening, the solder mask,
etc. in ASCII object-oriented style. The main files are:
1. TOP
: top layer metal etching, designating the main signal tracks
2. PWR
: the layer under the top, used to distribute the supply voltage to the circuit
3. GND
: third metal layer, which works as stable ground reference
4. BOT
: bottom layer, for soldering purposes and spare non-critical routing
5. APP
: list of all the apertures made into the FR4 card. The diameter of circular holes,
the x-y size of the rectangular ones, and inner-outer diameters plus angles and widths of the
bridges for thermal reliefs are written there
6. DRL
: the holes to be drilled in the epoxy card. The different diameters count has been
minimized, since the board cost is proportional to the complexity of the automatic drilling
step
7. SST
: the silk screening to be reproduced over the top plane. Labels and element
outlines to ease the component placing and soldering are depicted here.
The first 4 files are represented in Fig. 8-8, nearly in 1:1 scale.
FRAME6.TOP (Layer 1)
a)
FRAME6.PWR (Layer 2)
b)
201
Chapter 8
The test setup - design of RF boards
FRAME6.GND (Layer 3)
FRAME6.BOT (Layer 4)
d)
c)
Fig. 8-8 Gerber files of the 4 layers: a) top, with all signal traces and mounting pads; b) power supply,
in negative, with insulation holes and thermal reliefs; c) ground, alike, with the chassis connection of the
SMA plugs, in negative; d) bottom, only soldering pads and some non-critical digital routing.
The modified corners of the two inner planes permit to insert 4 screws of 3.2 mm
standard diameter, in teflon or steel, used both to lift and fix the board to the lab workbench.
After the manual mounting of the components the card looks like in Fig. 8-9, with the chip at the
center; this version is without the quartz and voltage regulator.
Fig. 8-9 Photograph of the completed FRAME6.board. Together with the wrap-around components, one
TQFP-32 test chip has already been directly soldered to the board. The voltage regulator U102 and the
crystal X101 are not shown.
202
Chapter 8
The test setup - design of RF boards
The list of components is reported in Appendix D. The capacitors are divided in C0G and
X7R types only due to their nominal value; in general the C0G composition (for C < 10 nF) was
preferred, owing to its better temperature stability.
8.2 RF board for RUN07/99
By providently distributing the TQFP48 available pins between the test circuits (leaving
unused, in one chip, the pads needed to operate another one) a unique configuration for the I/O
ring was finally obtained in Chapter 7. This means that all the 17 oscillators can be tested onto a
single RF printed circuit board, designed to comply with the signal arrangement shared by the 6
chips. The goal of placing comparable VCOs in the same positions on the die has been also
achieved, except for some splits of STARMAN.
The sequence of leads is directly readable by looking at the layouts reported in Tables
I..VI. The test board was designed starting from the series of 48 electrodes, and adding the
minimal acceptable amount of wrap-around circuitry. It is worthwhile to note that no VCO
current sensing capability was provided on the 6 test chips; in fact, the current flow can be
inferred directly by the PCB consumption, provided no circuits other than the desired VCO are
on. Even simple LEDs signaling the power-on could perturb the drawn current measurement, and
were not included. Lowering its separate power supply, or quenching its tail current source, even
the final buffer stage can be turned off: the real current sinking of VCOs is then univocally
derived.
Since 6 different dice (to give at least 180 specimen totally) have to be characterized in
this run, to make the specimen preparation easier the direct soldering of the chips to the board
copper pads must be eluded. Every soldering and de-soldering operation in fact degrades the
quality of the board surface, due to the tin layer buildup; after 3-4 chip de-attachments the test
card becomes virtually useless. To overcome this problem, we decided to adopt a chip socket to
hold the various pieces under test. Since these devices can be mounted on the PCB by means of
standard screws, the board substitution (for example if failure suspicion raises) becomes almost
immediate task. The normal commercial sockets are of course unable to manage the over-3 GHz
RF outputs synthesized on the chips: a device specifically designed for high-frequency
applications was sought, and purposely purchased.
8.2.1 Main features of the socket
We examined products from Johnstech, Z-Tech and MuCon companies. The final choice
was the Johnstech® socket, JTI-MS048-QFP07-0.50, of the Giga-3 series [122]. The device
allows to manually load the chip, and the cover depicted in Fig. 8-10a blocks it steadily during
the test. The chip pins do not contact directly the board, but compress some little springs (in
beryllium copper, hard-gold plated) that in turn get in touch with the board. The certainty that the
contact actually takes place is guaranteed by the pushing action of two elastomers, which drive
the little springs against the underlying copper area. The device provides surface mount
capability, and permits to shrink the overall board.
203
Chapter 8
a)
Fig. 8-10
The test setup - design of RF boards
b)
Drawing of the manually operated socket a), and b) picture of the base chip-holder (after
[122]).
Fig. 8-10b illustrates the external look of a standard Johnstech device; the upper opening
is for thermal conditioning purpose. Ours will be a smaller version of it, 38.1 × 38.1 mm, to
further reduce the board size. Mechanical specifications are collected in [123]. The endurance of
the socket exceeds 100000 insertions, enormously superior to our requirements [124].
The nominal operating frequency of the device ranges from 0 to 3 GHz. However, our
mirrored-Colpitts oscillator can be safely tested by using the socket, since the additional
attenuation remains under -3 dB @ 10 GHz, and is much less than -1 dB @ 3.6 GHz, as can be
inferred from the Fig. 8-11a:
b)
a)
Fig. 8-11 Main performance figures of the socket: attenuation of the signal with frequency (insertion
loss < 1 dB below 7 GHz), and percentage of crosstalk between adjacent pins (< 2% at 1/3.6 GHz) (after
[124]).
Remember from Chapter 7 that the differential outputs have been separated by a steadyvoltage line in the chips; then the crosstalk of Fig. 8-11b can perhaps be taken as worst-case
estimation. The additional self-inductance is less than 0.9 nH, thus the results of the simulations
performed to tailor the output buffer stage in Chapter 6 are still reliable. The added resistance
204
Chapter 8
The test setup - design of RF boards
does not reach 6 mΩ. A Spice-format equivalent circuit of the parasitics is also available from
the manufacturer [125] and is reported in Fig. 8-12 in the case of Giga 3 model. It is
substantially similar to the equivalent circuit that was adopted to model the TQFP-48 package,
but the parasitics values are even less and will bring minor impact on the simulation outputs.
Fig. 8-12 Equivalent circuit for two adjacent pins, to be added in cascade to the lumped circuit model
of the package and before the parasitics of the board (after [125]), for example when simulating the
differential pair of RF outputs.
Fundamental importance has to be accorded to the coplanarity of the socket landing
points. As no soldering is performed, the springs must be kept at the same level, to avoid
geometrical imbalances that could translate into cross-talk performance degradation. Besides
keeping at uniform height the 48 copper pads on the board, also the 4 landing points of the
socket core must be at the same level. 4 additional copper pads must compulsorily be designed
there, and the copper thickness must be identical for all of these regions (as indicated in Fig. 813a). The required coplanarity is 0.05 mm, i.e. the present accuracy limit of standard PCB
manufacturing machinery; fortunately, it can be assured with little overcost.
a)
Fig. 8-13
b)
Coplanarity requirements on the copper+gold thickness uniformity of pads and socket
landing zones electroplated on the board a), and geometrical specification of the socket b) (after [123])
205
Chapter 8
The test setup - design of RF boards
Also reported in Fig. 8-13b is the footprint to be reproduced on the epoxy card. In
particular, the mounting area for the socket is a keep-out zone, in which neither solder mask nor
silk screening is allowed. Moreover, the metal signal traces ought to be routed outside from this
zone; the only metal paths tolerated are the ones from the lead contactor to the nearest border of
the keep-out zone.
Together with height alignment, x-y alignment was also important. To aid the correct
assembly process, the socket offers two alignment pins, along with the 4 holes for the mounting
screws. The tolerance of their position is kept very tight, and so does the corresponding holes
position tolerance on the board: less than 0.02 mm (once again, the accuracy maximum of the
drilling machinery). Reaming process was also recommended for the alignment pins, and
performed during board manufacturing [123]2.
8.2.2 General organization of the PCB
The principle that stays behind the test chip is very simple: clean voltage references are
externally provided to the VCOs, and the balanced buffered outputs are converted to singleended oscillation to measure the phase noise spectra with the HP8593E spectrum analyzer. The
signal processing to be performed on the test board is therefore minimal:
• input bias filtering
• output oscillation differential-to-single-ended transforming.
The traces of the test card start from the socket leads, and irradiate towards the inputoutput terminals scattered around the square package.
8.2.2.1 Fabrication constraints
The socket footprint (comprising the no-routing zones and the cover lock area) was
specifically prepared in Orcad libraries, and is based on the drawing of Fig. 8-13b. The tolerance
for the pin alignment was very tight, set to 0.01 mm. The schematic organization of the board is
illustrated in Fig. 8-14, which represents the starting point of the Orcad synthesis of the design.
2
The author wish to thank the staff of GraphicMaster S.r.l. and of Ramidia S.r.l. - Milan (Italy) for their timely and
competent help in the final definition of board layout and process flow, and for the outstanding board manufactured.
206
Chapter 8
The test setup - design of RF boards
5
4
3
2
C1
1
2
1
TP1
TPBis
1nF
TP2
TPBis
P
P
RF3
SMAplug
4
5
6
IN
2
OUT
VP_VCO1
GND
+ C37
22uF
1
1
1
U1
1
GNDaBALUnBal NC
GNDbBAL+
U3
BALUNBis
1
U10
LT1584CT-3.3
+ C38
22uF
2
2
3
3
2
1
2
2
VP_PWR3
VP_PWR3
C3
1nF
TP8
TPBis
2
C2
1nF
2
TP9
TPBis
P
L2
Choke
P
1
1
L1
Choke
2
1
2
1
2
2
2
2
2
IN
2
OUT
+ C41
22uF
220nF
GND
220nF
1
2
TP11
TPBis
U12
LT1584CT-3.3
1
1
+ C40
22uF
P
2
220nF
1
1
220nF
R5
0k
C9
1
2
R4
5.7k
C8
P
1
100nF
TP10
TPBis
1 1
2
R3
5.7k
C7
VP_VCO2
2
P
1
100nF
1 1
1
R2
5.7k
C6
2
OUT
3
P
C4
2
1 1
1 1
1
R1
5.7k
C5
IN
+ C39
22uF
GND
Poc1
TPBis
2
Vb9
TPBis
1
Vb8
TPBis
P
P
Vb7
TPBis
P
Vb6
TPBis
FerriteBead
1
1
1
GND_VCO
1
GND_PWR
1
1
1
1
U11
LT1584CT-3.3
+ C42
22uF
VP_VCO3
2
2
3
VP_PWR3
VP_VCO3
24
23
22
21
20
19
18
17
16
Pocketa
Vbiasd
GND_VCOb
R6
GND_OUTb
25
1
1
2
220nF
C12
VP_PWR3
220nF
5.7k
VP_VCO3
2
1
2
3
9
1
8
7
P
TPBis
27
Vpeakc
GND_RFc
Vbiasl
OUT+b
28
L3
29
1
1
P
1
5
2
Vbiask
Vbiasf
Vbiasj
OUT-b
Vbiasi
GND_RFd
4
30
31
32
R9
C15
100nF 1
C17
5.7k
100nF
TPBis
C18
1
BAL+ GNDb
NC
UnBal
BAL- GNDa
6
5
4
BALUNBis
2
VP_OUTa
VP_VCOb
VP_VCOa
34
2
1
1
1
GND_OUTd
GND_VCOc
2
VP_PWR1
2
C22
1nF
Choke
220nF
C23
1
2
5
4
3
2
36
220nF
Vbiasg
GND_VCOd
GND_AGC
Pocketb
VP_OUTb
Vbias/Vpeak
GND_RFe
OUT+c
OUT-c
Vbiash
2
Vpeakb
GND_RFf
C24
220nF
5.7k
1
VP_VCO1
35
1nF
1
C21
2 1
GND_VCOe
R12
1
U7
1
2
3
P
L4
VP_PWR1
2
3
2
P
TPBis
2
1nF
Vb11
1
33
VP_VCO2
2
Vb1
VP_PWR1
C14
1
1
C19
220nF
5.7k
C20
220nF
5.7k
2
Choke
TPBis
1
1
TPBis
2
Vpeaka
2
R10
1
TPBis
1
GND_OUTc
VP_VCO/VP_OUTa
2
6
2
P
R11
1
Vbiasm
11
C16
220nF
Vb3
P
26
Vp2
TPbis
JVp1
Jumper3Bis
2
5.7k
Vb2
Vbiase
2
1
10
1
Vp1
220nF
P
P1
P2
P3
1
1
P
R8
TPBis
VP_VCO/VP_OUTb
C13
2
Vb4
11
2
1
TPBis
2
1
1
P
R7
1
C10
5.7k
220nF
C11
Vb5
Vb10
2
GND_VCOf
1
GND_OUTa
Vbiasc
Vbiasb
GND_RFb
OUT-a
Vbiasa
OUT+a
GND_RFa
GND_VCOa
P1
P2
P3
12
15
14
13
1
2
3
JVp2
Jumper3Bis
U9
SOCKET_TQFP48
RF1
SMAplug
37
38
39
40
42
41
43
44
45
46
47
48
C25
C28
2
C30
220nF
C29
2
2
C34
22uF
C35
22uF
C36
22uF
1
1
1
TP3
TPBis
TP4
TPBis
P
2
2
C32
VP_PWR2
1nF
P
VP_PWR3
VP_PWR1 VP_PWR2
1
1
C31
VP_PWR2
1nF
Vb12
TPBis
2
P
L6
Choke
P
1 1
1
Poc2
TPBis
2
1 1
2
1 1
L5
Choke
2
R15
220nF
5.7k
220nF
R14
0k
P
1
Vb13
TPBis
1
2
1
1
Vb/p
TPBis
+
VP_PWR2
P
2
P
2
+
C27
11
R13
100nF 100nF
5.7k
Vp4
TPBis
+
C26
2
1
1
220nF
1
2
1
1
1
P
P
BAL+GNDb
NC UnBal
BAL-GNDa
P
1
2
3
TP5
TPBis
TP6
TPBis
TP7
TPBis
1
1
2
2
U8
BALUNBis
6
5
4
RF2
SMAplug
C33
1
2
1
1nF
2
3
4
5
Fig. 8-14 Global schematic for the Run0799 RF board.
The mechanical dimension of the socket imposes some limitations. For example, onto the
areas where the cover latch is to be locked, or that the cover itself will occupy when opened
wide, only SMD components featuring especially small height must be placed (< 0.5 mm); we
tried to keep them completely free from components anyway. Such critical areas were delimited
with silk screening boundary-marking lines. For sake of safety an additional clearance of 0.5 mm
was drawn, external to the keep-out profile highlighted in Fig. 8-13b; this prevents eventual
solder mask diffusion towards the prohibited region. A plot of the final top layer of silk
screening (Orcad Gerber file .SST) is represented in Fig. 8-15:
207
Chapter 8
The test setup - design of RF boards
RUN0799.SST
Fig. 8-15 Silk screen layer on the top of the board, defining the soldering areas of the SMD components
and the keep-out zone needed for maintaining the required coplanarity for the socket to be screwed.
The four trapezoidal pockets adjacent to the branches of the cross-shaped keep-out zone,
have been utilized to place the small-outline SMD components needed for critical decoupling.
Namely, all the chokers for the open-collector output driver biasing, together with the decoupling
capacitors preceding the balun, where placed in the pockets. In fact the maximum height reached
by the chokes and the capacitors is < 0.55 mm, whereas the maximum height allowed is 1.5 mm.
To keep the power supply connections shortest, they were routed to the respective planes through
vias that violate by far the planarity requirements needed by the landing surface; the pockets
proved excellent also to place these latter ones.
The TQFP-48 chip pitch between the leads is as low as 0.5 mm. The load board copper
pads are very close to each other, hence they require a tight process tolerance in order to assure
that the footprint terminals are not shorted together. Without the socket, the bonding procedure
would have been very complicated. A drawback of using the chip socket against soldering is the
need for a particular pad plating process: the standard galvanic deposition of copper-tin alloy is
not suitable to ensure a correct contact with the socket springs, and electroplating of nickel or
gold is required. We opted for a gold layer, meeting MIL-G-45204C recommendation (i.e. gold
pureness of 99.7%, and minimum thickness of 1.3 µm). The manufacturer verified the quality of
the impedance matching by means of a final reflectometric analysis.
In case of socket failure, the dimensions of the crown of copper pads is such that direct
soldering could be anyway performed. The pad length on the card was extended from 1.30 mm
up to 1.50 mm, so that the gull-wing leads of the chip are vertically in line with the underlying
landing areas; a little loss in the impedance matching will be paid for such a modified
arrangement.
For what concerns the materials for the board production: again low-cost FR4 dielectric
(i.e. conventional epoxy) was used, without resorting to more expensive solutions such as duroid
208
Chapter 8
The test setup - design of RF boards
(or even alumina, or esthers). Dielectric constant variations remain bounded to a minimum,
within the industrial temperature range.
8.2.2.2 PCB drilling issues
The effective diameter of every hole was added 0.2 mm, to obtain the drill diameter
really set in the design. The diameter of the surrounding copper pad was kept 24 mils larger than
the hole border; within the copper pours, the inner pad diameter was arbitrarily enlarged of
further 0.5 mm. When the hole had to be isolated from outside, an annulus 12 mils wide was
issued to avoid shorts due to metal “whiskers”.
To implement the planarity recommendations set forth in [123], four copper circles were
laid out in the TOP layer (see Fig. 8-17a). At corresponding positions of the BOT image (Fig. 817d) appear the 4 copper islands at which the screws will be locked, insulated by the outer metal
pour. The drill for the screws will of course remain insulated from the inner planes, as can be
seen from the drill scheme Fig. 8-16. The content of the Gerber file .DRD, the list of drills, is
visualized below:
RUN0799.DRD
Fig. 8-16 Drill Gerber file, indicating the different types of holes needed. The non-plated holes are for
the 4 screws and the alignment pins, and undergo a special reaming process.
The fixing screws and the alignment pins will pass through the non-plated, and especially
reamed, holes indicated in the adjacent table.
8.2.2.3 Stacked layer assignment
The double set of power supplies and grounds (VCO and output buffer) called for 6
layers, that we reduced to 4. The global thickness of the board is 1.6 mm, then the card is rigid
209
Chapter 8
The test setup - design of RF boards
enough to withstand the mechanical compression imparted by the closed socket without
requiring additional backing plates. Here is the layer organization:
1. as usual, the uppermost plane (TOP) is reserved for the normal signal tracks, and to the
labels - in silk screening - indicating the positions of SMD components
2. the VCO analog ground (GND_VCO) is immediately under, so as to minimize the
inductance of the connections with the tracks and filters laid out on the top. Since the
ground paths do not create loops either on the PCB or into the chip (see Chapter 7) the
entire plane is to be considered a star point (also called “Kelvin point”)
3. the different power voltages are two per every circuit, but since we will operate one VCO
at a time (to exclude interference coupling) we deal in practice with 6 power lines. In order
to decrease the layer number, we devoted entire copper planes only to the grounds; then
one copper plane was partitioned in 6 parts. This copper pour (PWR) is the third layer from
top; it lies between the two ground planes in order to provide inherent bypass capacitances
(the geometrical parallel plates) towards the ground. The low R and L of the metal plane
sandwich enhance the efficacy of the decoupling it provides. Instead of realizing them on
different layers and be overlapped, wherever possible the power planes have been
separated by > 2 mm of insulating gap, following a highly recommended practice [126]
4. the buffer ground is at the bottom of the board (GND_PWR), as it presents less stringent
need to minimize parasitic inductance; this plane will be also used to mount some SMD
decoupling capacitors. Such an arrangement of the two ground planes is expected to
improve the EMI (Electro-Magnetic Interference) performance of the board [126].
Other useful hints for achieving a successful board design were also taken from [127].
8.2.2.4 Floorplan of the board
The domains of the PWR plane mentioned above were shaped by taking into account the
position of the power inlets on the chip, and the location of the pins that needed more direct links
with the power plane. The Orcad Gerber views useful to describe the board arrangement are
reported below:
RUN0799.TOP (Layer 1)
RUN0799.GND_VCO (Layer 2)
VCO3
VCO1
VCO2
a)
b)
210
Chapter 8
The test setup - design of RF boards
RUN0799.PWR (Layer 3)
RUN0799.GND_PWR (Layer 4)
PWRvco-3
PWRout-3
PWRout-1
PWRvco-2
PWRvco-1
c)
PWRout-2
d)
RUN0799.SSB
RUN0799.SMT
e)
f)
Fig. 8-17 Gerber files of 6 layers: a) top, with all the signal traces, mounting pads, and circular
screwing pads; b) analog ground, in negative, with insulation holes and thermal reliefs; c) power plane,
partitioned in 6 areas – for VCO and output buffer separate supply; d) buffer ground, with the pads of the
large supply-decoupling tantalum capacitors and some paths of the tuning nodes; these are physical
layers. Other useful views: e) sketches the surface mounting areas of the elements, i.e. the regions free
from green solder resist; f) depicts the silk screening on the bottom side.
In Fig. 8-17 the Gerber files of the 4 copper layers are first depicted. The last two views
(.SMT of the solder resist removal to allow surface mount on top, and .SSB of the silk screening
211
Chapter 8
The test setup - design of RF boards
on the bottom) are related to the geometry of the components, and help understand the device
disposition on the available space.
8.2.3 The chip leads arrangement
The TOP (Fig. 8-17a) layer shows the landing pads of the socket footprint, at the center,
from which all the signal tracks depart. To correctly read the lines’ connection their function
must be recalled, as identified in the Tables I..VI of the chips for the 07/99 test run. The pin
numbering reflects exactly the one used for the Orcad circuit schematic proposed in Fig. 8-14:
lead 1 is at the bottom of the left column, and the count advances clockwise. Only the main
features of the tracks will be outlined next.
Given the division of every die in three circuits (except Chip VI), every chip set of leads
is partitioned in three sets of 16 pins. Proceeding clockwise:
1. leads 7..12, 13..22 pertain to VCO3
2. leads 23..38 belong to VCO1
3. leads 39..48, 1..6 are relative to VCO2.
Pin 7, and all the pins that carry a bias signal to be furnished to the oscillator (i.e., 19-2023-24-26-38-40-4-5-6-7), comes from R-C lowpass filtering of the input. As a DC signal, it can
be coupled to the board through a simple soldernail (indicated by VBx in the top labels); all the
jacks are scattered only on the top layer of the board, for wiring convenience. The filtered
voltage is eventually testable on the broad line that joins R and C solder pads; the capacitor is
then tied to ground with a via, finding the analog ground at the layer immediately below. All
SMD resistors and capacitors adopt the standard EIA-1206 or -0805 footprints.
Pin 8 is a peak amplitude output (like 28 and 48), hence it is read by means of a test point
and left unfiltered, not to perturb the peak detector working.
Pins 9 and 11 are respectively buffer and VCO supplies in the Chips I..V; they exchange
their function in Chip VI. To fix this anomaly, they are routed to the central lead of a switch, that
can be tied to one of the two suitable supplies by means of short-circuit cap. The arrangement
can be better observed in layer .PWR of Fig. 8-17c, top left, where the two sides of the 3-lead
switches belong to different power domains. All the power leads have been provided with a 220
nF SMD capacitor towards its respective ground; since the reference ground for these pins could
vary between Chip I..V and VI, we tied the socket Pin 9 to PWR_GND and Pin 11 to
VCO_GND, that is the right connection for the first 5 chips – hence, in 80% of cases! Other pins
are not in the best configuration when Chip VI is mounted in the socket; some grounds, in
particular, result swapped between VCO_GND and PWR_GND in such a case.
The decoupling capacitors for power leads are mounted on the bottom side of the board.
Being the only components that must be put there, they can be always placed in the most
convenient position to minimize the track length; then vias coming from the top are almost
adjacent to their bypass capacitor. Metal clearance issues forced us to fix the vias directly onto
the track for Pins 9 and 11, but DC lines cannot suffer of these discontinuities.
Pin 12 (and 13-14-19-22-29-33-36-37-39-43-47-3) is an analog “clean” ground. The
metal path is drawn away from the socket as soon as enough space to place one via is found, and
connected to the underlying copper plane. At the VCO_GND level the grounds of the oscillator
and the AAC are joined together, after they were kept distinct inside the chip for bounce
rejection prevention.
212
Chapter 8
The test setup - design of RF boards
The Pin couple 15-17 (and the analogous 30-32, 44-46) routes the output differential
oscillation, thus it is the most important in the project. The lines carrying the signals are drawn in
highly symmetrical way: they diverge at 45° until sufficient room for a via in between is created,
then direct towards the footprint of the decoupling 1 nF capacitors. These tracks face impedance
matching problems, since they must reach the balanced-to-unbalanced translation element - the
SMD balun in our case - that requires standard characteristic impedance of 50 Ω on the lines
reaching it. The suitable connection scheme is suggested in [118], and implemented as in Fig. 817a. The calculations for deriving the correct line widths are identical to the ones performed in
Paragraph 8.1.3 for the FRAME6 board; the only variation is to be ascribed to the thicker line,
since additional, MIL-compliant gold electroplating is now to be done. By performing an errorbar analysis on the (8.2)-(8.4) equation set, this time with respect to the parameter t, a deviation
less than 0.12% is found for the 1.3 µm additional gold layer. The 0.85 mm thickness cannot be
realized over all the line length, due to the tiny 0.5 mm lead pitch; the starting width was since
then of 10 mils for each path. We applied the line tapering technique, by changing the trace
width when the path features 45° corners; in such points the line impedance would have suffered
anyway a discontinuity, so the cumulative perturbation is minimized. Moreover, the path
extremes have been designed in round fashion, to alleviate the sudden local inductance increase
caused by bendings. The chokes for the open-collector buffer bias join the line on the lower
solder pad of the capacitor, where another impedance mismatch is inherently created, and a
further tee-shaped branching brings less impact. The chokes are shorts at DC and open circuits at
ω0, thus their traces should be as thin as possible: the equivalent open-circuit parallel stub entails
in fact lesser effect. The 1 nF capacitor after the balun offers the chance to insert a right bending
on the line towards the SMA plug, by rotating the component. Standard 50 Ω line is adopted for
this last connection stretch.
Pin 16 (and 31, 45) carries some critical DC bias lines to the VCO. Tight symmetry is
required for this input; at the top level this is assured by the surrounding differential outputs, but
no space is left for the R-C filter. A via is placed between the lines, and two identical 100 nF
capacitors (to improve symmetry) are placed on the bottom plane, before returning to the top for
mounting the resistor and its jack. The resistor is mounted on the top layer to allow easier
voltage sensing with the tester plug.
Pin 21 (together with 25-27-1) is connected to the bottom plane, PWR_GND. The via
pad was designed very small, thus the contact to the bottom plate (Fig. 8-17d) looks like a cross
without the central pad. The parasitics of this via are a little worse than the equivalent ones for
VCO_GND plane, but the net is indeed less critical.
Pin 34 (and 41) is used for the power supply of the buffer. Immediate decoupling of the
pin (“freezing” in technical jargon) in achieved by using a 220 nF ceramic capacitor on the
bottom plate, towards GND_PWR. The parasitic inductance of the ceramic component is
certified extremely low. The element could not be put within 2 mm from the pin (as suggested by
[126]) because of the keep-out zone impairment.
The same procedure has been followed for Pin 35 (and 2) of analog VCO power; the
trace is connected with the capacitor on the bottom side, and one via ties it to the inner plane
GND_VCO.
The high number of supply/ground lines among the 48 leads automatically assures
shielding for the adjacent lines, which are eventually decoupled from one another. In particular,
the output traces remain enclosed within the near ground-shield paths as far as possible. As a
general rule, all over the board we avoided sharp bending of the traces to lower the parasitic
inductances. Diagonal 45° layout has been forced for automated routing, and the final manual
corrections have been performed consistently.
213
Chapter 8
The test setup - design of RF boards
8.2.4 Components for on-board wrap-around
The three power supplies for the VCOs can be directly fed to the circuit through
purposely placed soldernails; but three landing areas to mount suitable voltage regulators were
predisposed, in correspondence of the PWR plane zones. The regulator shall be in TO-220
package, with central input voltage (V1+, V2+ and V3+ on silk screening). These characteristics
have been tailored for the LX8385-3.3CP regulator. As usual, the “in” and “out” pins are
filtered towards GND_VCO with high-value low-parasitics 22 µF tantalum capacitors, that can
be clearly seen on the .SSB bottom view, in Fig. 8-17f. The + sign indicates the polarity of the
element for mounting ease. The tantalum capacitors warrant lower inductance than their
electrolytic counterparts, but they need anyway some shunting by lower ceramic capacitors,
which are the ones sparingly distributed on the PCB to bypass the power pins. The remaining
three power plane regions for supplying the output buffers are biased by different soldernails.
Each domain is given its own tantalum capacitor towards the bottom plane GND_PWR.
The two grounds are connected in the right upper corner of the card to the soldernails
labeled GNDPWR and GNDVCO (see Fig. 8-15). They are placed very close to the ferrite bead
that couples the two planes at low frequencies, but blocks the bounce disturbance at GigaHertz
frequencies that will affect the two rails. Intermodulation of the two sections is prevented, in this
way. A toroidal winding would minimize the magnetic interference of the element, but for size
convenience we chose a standard 47 µH radial element. Besides the soldernails and the voltage
regulators, the ferrite was the only component mounted through-hole of the entire card (Fig. 816).
The R-C filtering applied to the input reference voltages could be avoided by substituting
the 5.7 kΩ resistor with 0 Ω resistors, commercially available to realize “wired” switches. All the
SMD resistors and ceramic capacitors featured a 1205- footprint small outline package, hence
could be placed in the decoupling pocket under the socket (Fig. 8-17e).
Much like the FRAME6 board, the balun was chosen from Murata and M/A-COM
catalogs. In cases whose output frequency is expected about 2.6 GHz, the ceramic, copper-wire
Murata LDB20C101A2400 [118] is apt for the purpose since its band exceeds 200 MHz. For
the chips containing 3.6 GHz-Colpitts oscillators another chance was to exploit a printed balun,
by combining 90° hybrid realized with transmission lines; or, simply employ the same SMD
balun. The first solution required considerable PCB room, since λ ≈ 8.3 cm @ 3.6 GHz and raterace and branch-line implementations require branches of length λ/4. With our process
tolerances, the synthesis of characteristic impedance controlled up to the necessary degree of
precision is also a serious obstacle. We decided to maintain the same component for the singleended conversion, and in case to resort to the 18 GHz-bandwidth, low-noise single-ended
amplifier Miteq AMF-4D-001180-24-10P to restore the output power level. This block
has a 30 dB gain up to 18 GHz, and a noise figure as low as 2.40 dB.
Last but not least, finding SMD chokes at wireless frequencies is not easy due to the low
self-resonant frequencies, fSR, that transform them in capacitors before 3.6 GHz. We discovered
suitable chip coils from Murata (LQW1608AR12G00, 120 nH and fSR = 1.6 GHz; or
LQP10A22NG00, only 22 nH but fSR = 2.8 GHz). In order to rise the self-resonance frequency,
basically limited by the shunt capacitance of the case, the chip coil sealing was removed in those
models. Because of the potential EMI generation of the naked spiral or winding, we discarded
them, and decided to adopt the BLM11HB601SD (with tiny EIA-0603 footprint) that is
completely enclosed in Mu-metal anti-magnetic foil. A graph representing the impedance
214
Chapter 8
The test setup - design of RF boards
magnitude up to 2 GHz for the chosen coil series is given in Fig. 8-18 together with the image of
an element sample3.
Fig. 8-18 Impedance magnitude graph for the SMD chokes BLM11HB from Murata, and the external
look of the EIA-0603 package (after [118]).
The residual impedance at 2.6 GHz is expected to exceed 600 Ω, whereas at 3.6 GHz
only < 400 Ω remain. When put in parallel to the 50 Ω-single ended of one balun input, this
leads to a total impedance of 44 Ω; this will eventually lower the signal available at the balun to
89% of the nominal one. As interference is not tolerated, this is however the best choice among
SMD implementation: a smart microwave alternative would have been the layout of spiral
inductors with the top copper metal. They could have been simulated with the microwave circuit
solver Touchstone, and operated as chokes (given the rather lossy substrate, tan δ = 0.019 for
FR4, the Q would not probably be satisfactory, and the self-resonance frequency will be rather
low). The rules valid for the IC design of inductors become nevertheless hazardous in this new
environment, and could not be easily applied on such a magnified scale; perhaps only Wheelerlike formulas [128] or even the Greenhouse’s methods [129] would analytically cope with such a
task.
The footprint of the chokes, and of many other components (the ferrite bead just to
mention another) were not predefined and have been created in the Orcad libraries.
8.2.5 The final product – Ready for the tests
The complete board design for the RUN0799 project, from the decomposition of which
we obtained the Gerber views depicted in Figs. 8-15 through 8.17, is finally illustrated in Fig. 819.
3
The author wishes to acknowledge the staff of Murata Elettronica Italia S.p.A. for providing a free demonstrator
collection of baluns and chip coils, greatly facilitating the final choice.
215
Chapter 8
The test setup - design of RF boards
Fig. 8-19 Overall view of the board project (cyan = top, blue = analog ground, green = power plane
zones, red = bottom plate, as the color number of layer on the top right indicates).
where cyan pads and traces identify the copper islands on top layer ( 1 in the layer identification
label on right top), whereas blue areas indicate the metal present on the inner ground plane 2 ).
The green plates outline the copper pours created on the inner power layer ( 3 ); the residual red
uniform area is the bottom ground plane (labeled with 4 ). In white, the silk screening.
In the last Fig. 8-19, two snapshots of the completely mounted, operational, ready-for-test PCB
are eventually reported.
Fig. 8-20 Pictures of the compact mounted board, taken from the side and from the top.
216
Conclusions
Conclusions
A
t the end of the Ph.D. activity, a brief wrap-up of the targets accomplished and of the
perspective opened proves quite useful. The main contribution of this work to the
state-of-the-art has been surely the identification of the noise conversion
mechanisms that bedeviled the industrial oscillators available for our characterization at
Politecnico di Milano. The role of the indirect stability in VCOs embedded in complex mixedsignal environments has been identified, and quantitatively assessed by resorting to the
sensitivity coefficients. The predictive apparatus has been completed by devising some
computationally efficient techniques, that allow the estimation of the SSCR of a system with the
cheapest commercial tools, and in a fraction of the CPU time required by conventional methods.
This theoretical result has been given practical application, by tailoring the core
oscillating cell of a bipolar fully-integrated VCO so as to reduce the impact of the noise coupled
to its bias current. The experimental activity so far carried out on that test chip leads us to assert
that the phase-noise-engendering effect was correctly addressed, and properly minimized.
Moreover, this result has the worth of having been achieved only thanks to careful circuit design,
adopting the standard bipolar process without calling for technology adjustments. Other test
circuits, both variants of the original LC-tuned oscillator topology and completely new structures
have also been designed, but could not be tested before the end of this Course.
In conclusion, starting from the phase noise minimization problem, through the
understanding of the phenomena potentially hindering the SSCR performance, a circuit synthesis
- in broad sense - was done: from the schematic level of CAD to describe the topologies, down to
the physical full-custom layout, and beyond, with the design of the external RF board needed for
the test. Such a design flow virtually encompasses all of the stages of a modern Electronics
project, also needing the aid of a variety of tools. My personal balance, at the end of this Ph.D.
Course, surely closes with a net gain.
The most immediate step to be taken after this work will be the experimental
characterization of the 6 test chips of the 07/99 run, using the board purposely set up. From the
theoretical side, instead, the extension of the stability-based phase noise quantification to the
noise sources lying at high frequencies (2ω0 and more) is strongly recommended.
The main future perspective of this work is the adoption of the new VCOs into PLL
structures, suitable for the local oscillator frequency synthesis on wireless terminals. Work has
already been started towards this accomplishment in multi-standard mobile transceivers, using a
BiCMOS process technology with performance comparable to the HSB2 employed here.
217
Appendix A
Realization of the low-noise voltage amplifier
Appendix A
Realization of
the low-noise voltage amplifier
Here are described the circuit analysis, the practical fabrication and the final measurements which
attested the safe employability of a differential instrumentation amplifier scheme for the low-noise, highimpedance probing of the voltage signals that was required in Chapter 4.
A.1 Necessity of a low-noise voltage amplifier
O
ne of the problems that must be solved in order to perform phase noise-related
measurements, and consequently validate our perceptions, is the high-impedance low-noise
sensing of the nets of the VCO: in particular, BGR output and oscillator tail driver.
A number of commercial amplifiers are available, that anyway do not comply with our inputreferred noise requirements (unless resorting to very expensive biomedical instrumentation). Basing
on a former work [130], a differential instrumentation amplifier has been fabricated: it features 2.4
nV/√Hz of input equivalent noise source, and a +34 dB gain. Even better performance could be
achieved by fabricating the circuit in [131], but at the price of increased complexity. The complete
schematic of the device is illustrated in Fig. A-1, where the two common-mode rejection feedback
loops are especially highlighted.
218
Appendix A
Realization of the low-noise voltage amplifier
+12 V
_
2.2 k Ω
1
10 k Ω
_
2.43 k Ω
15 k Ω
+
7.5 k Ω
J2
47 MΩ
150 Ω
OUT
IN-
7.5 k Ω
15 k Ω
J1
50 MΩ
IN+
50 MΩ
3.3 nF 1.8 k Ω
A1
5.6 MΩ
+
A2
2.2 µ F
3.3 k Ω
J3
4.3 V
1.8 k Ω
-12 V
2
Fig. A-1 Schematic of the low-noise, high-input-impedance amplifier, with the mirrored input stage and the
two feedback loops (with the opamps) highlighted; loop 1 acts on the right side of the J2 couple, whereas
loop 2 drives the left one. The feedback paths have been intended to balance the input structure and eliminate
the offset respectively.
The schematic in Fig. A-1 assures high input voltage range, and very reduced noise due to
the adoption of JFET transistors. The first feedback loop reacts against any asymmetries of the input
stage, thus enhancing the CMRR of the structure and the eventual voltage offsets.
A.2 Circuit description – The two feedback loops
The schematic can be partitioned in three sections:
1. A peculiar mirror structure for the input stage. The differential fashion of the input is not
exploited now for BGR measurements, but could be instrumental for future characterization
on balanced critical outputs. The choice of the input JFET couple is dictated mainly by noise
considerations; in fact, these transistors feature a flicker noise much less than their MOS
counterparts, and input voltage noise and linearity that overcome those of bipolars. The poor
matching is counteracted by the loop, and the adoption of a monolithic JFET-couple discrete
component greatly improves the symmetry of the input network, and thus the CMRR. The
lower FETs could be instead interchanged with BJTs, since they simply carry out bias
function; a little decrease of the degeneration efficacy is to be accounted for, in this latter case.
2. The A1 operational amplifier. It works in the classical differential-to-single-ended
configuration, acting both as signal-mode converter and as gain stage for the common-mode
219
Appendix A
Realization of the low-noise voltage amplifier
loop. The single-ended output allows to directly linking the amplifier to the spectrum analyzer,
or to an oscilloscope.
3. The A2 operational amplifier. When working as ideal integrator, it inserts a DC pole in the
feedback path of the second loop of Fig. A-1, i.e. it annihilates DC offset and also very slow
offset harmonics affecting the two “totem poles” at the input. The loop is able to reject both
differential and common-mode offsets. The position of the pole trailing the DC zero in the
transfer from offset inputs to output, can be regulated by changing the gain of the integrator
(or, its intersection with the 0 dB axis). A three-states switch allows the selection of different
resistors, to modulate the band.
The circuit is supplied with ±12 V rails, to comply with the diffused NIM (Nuclear
Instrumentation Module) voltage levels. The adoption of tracking power supplies is recommended
for this circuit, because all the other noise sources have been minimized, but the one coming from
the power lines could spoil the amplifier’s performance. The complementary voltages assure
anyway the avoidance of AC coupling, since the input gates are biased at 0 V; two input resistors tie
the gates to ground, autonomously biasing the system.
A.2.1 First feedback loop: the main working principle
The two 50 MΩ shunt resistors at input do not degrade the high impedance of it, that is one
of the requirements for using this device in VCO measurements. Mounting metallic layer resistors,
the cleanest available from noise standpoint, safeguards the low noise of the system. Even the
measurement of BGR noise would not require AC coupling, as the 0.62 V between one input and the
other (connected to ground) would be compensated for by the loop; but the little residual imbalance
can be avoided, without side effects, by inserting a 66 nF coaxial capacitor on the BGR input. This
creates a 50 MΩ⋅66 nF → 48 mHz pole!
The more symmetrical the input topology, the better the CMRR. Then the resistive ratios on
the gates are kept identical (in the range of tens of kiloOhms, as the gates do not drain appreciable
currents) and the lower JFET couples are optimized for matching, via component selection. The
resistors RI and RII carry no current, then they are also clean from a flicker noise standpoint; simple
carbon resistors will be chosen for surface mounting. Starting from the bottom of Fig. A-1:
1. the lowest couple, J3, acts as current source. The gates are biased by a common Zener-diode
voltage reference, BZX Motorola of 4.3 V with 3.5 mA of reverse current flowing. The
lower rail disturbances do not affect the synthesized currents, but the Zener diode is
potentially a very noisy element, and its effect must be elided by manually selecting identical
RE resistors. By taking RE = 1.8 kΩ we obtain VGS = 0.9 V (while the pinch-off drop is VP =
1.2 V), and a current of 1.87 mA in each column of the stage
2. the couple in the middle, J2, completes the A1 feedback loop. The gate to the right reads the
A1 output, and converts it into a current signal via the π-bridge RII. The transistors of J1 can be
seen as common-gate and shunt the current signal away from RI in their sources, delivering it
to the drain gain resistors RD, and then to A1 as a differential driving voltage
3. the J1 couple converts the input differential signal into current through the π-bridge resistor RI;
the current reaches RD and eventually becomes differential voltage on A1. The negative
feedback loop forces the current driven in RII by A1 to counterbalance the current signal in RI,
220
Appendix A
Realization of the low-noise voltage amplifier
so that the signal voltage drop taken on RD is minimized. The loop can be viewed as current
mode feedback in the network RI-RII, that must neutralize their voltage drops when Gloop → ∞.
The loop gain is:
2R
R2
Gloop = D ⋅ G A1 ⋅
(A.1)
R II
R1 + R2
The values of RD and GA1 ought to be designed high. Due to input equivalent noise sources
issues, the current in the JFET columns cannot be lowered, and a tradeoff between loop gain
and drop voltage on the drain is pursued.
The direct path gain is figured out by noting that the only J1 is driven from the signal, when
the loop is opened:
2RD
G forward =
⋅ G A1
(A.2)
RI
hence the closed-loop transfer is approximately:
G AMPL ≈
G forward
G loop
=
R II R1 + R2
⋅
RI
R2
(A.3)
Of course the gm transconductance of the JFETs must be raised in order to shunt the entire
current from the bridge resistors. With 1.87 mA we get gm = 12.5 mA/V, or gm-1 ≈ 80 Ω; the total
shunt approximation is thus well verified on J2, more critical on J1.
A.2.2 Second feedback loop: for offset abatement
The second feedback loop works in very similar manner; it reads the A1 opamp output, then
it emphasizes the low-frequency components via the integrator, reversing their sign. The J2 couple
is then driven and corrects in RII the signal flowing in RI. In practice, the first loop drives the right
transistor of J2, whereas this second drives the left one. The feedback loop gain is given by
multiplying the transfer computed in (A.1), times the gain GA2 of the ideal integrator.
The inferior limit of the band into which the offsets - no matter whence they come - are
rejected is controlled by a mechanical switch that can take 4 different values:
221
Value of RR resistor
Low border of the Bandwidth
Detached
47 MΩ
5.6 MΩ
10 kΩ
No offset compensation
1.5 mHz
12.9 mHz
7.2 Hz
Appendix A
Realization of the low-noise voltage amplifier
The switch is incorporated within the amplifier chassis (see Fig. A-2).
Fig. A-2 Photograph of the amplifier enclosed in the metallic chassis, with the shielded power supply
cables. The knob of the switch on the second feedback is shown to the left of the metal tank.
A.3 CMRR performance
The schematic in Fig. A-1 shows two main paths through which the common-mode signals
find their way to the output:
1. the bounded CMRR of the input structure, whose asymmetries join the RD as differential
voltage, and are transferred to the output by the amplifier A1
2. the bounded CMRR of the A1 amplifier, that converts at the output the common level
displacements of the voltage on the drain.
The second mechanisms can be minimized by carefully choosing the opamp; in fact, the
LF412 IC has been taken into consideration, which features up to 100 dB of CMRR. The first nonideality must be reduced instead identifying the real parameters that impact on it. By proceeding to
open-loop CMRR estimation:
• under the couple J1 the current sources are almost ideal; the CMRR can be conveniently
defined as the ratio between differential and common-mode transimpedance gains from the
input to the drain, i.e. by writing:
V
I
CMRR = CM ⋅ D
(A.4)
VD I CM
where only the upper section of the circuit plays a role
• the expressions for ID and ICM can be computed by analyzing the simple equivalent network
for the input couple J1, drawn as in Fig. A-3 and driven with VCM ±VD/2 signals:
222
Appendix A
Realization of the low-noise voltage amplifier
VDD
RD1
J'1
r 01
RD2
r 02
gmVGS
J''
1
RI
VCM+ VD /2
I1
I2
VCM- VD /2
VSS
R tot = R I + r01+ r02+ RD1+ RD2
Fig. A-3
The mirrored input “totem pole” simplified for CMRR evaluation purposes: only the J1
differential pair has been actually considered, with its equivalent circuit.
The voltage loop RD1-J1’-RI-J1’’-RD2 can be solved for the differential and common-mode
currents. Once a factor γ has been chosen to define
g m r0
γ =
(A.5)
1 + g m r0
where µ = gmr0 indicates the maximum voltage gain of the JFETs, it can be written
æγ +γ 2 ö
+ç 1
÷ ⋅ VD
è 2 ø
= I CM + I D
+ r01 ) − γ 2 ⋅ (R D 2 + r02 )
(γ 1 − γ 2 ) ⋅ VCM
I tot =
Rtot − γ 1 ⋅ (R D1
(A.6)
• finally, the expression given in (A.4) for the CMRR can be rewritten as:
CMRR =
VCM I D
(γ + γ 2 ) / 2 = 1
⋅
= 1
1
1
γ1 −γ 2
VD I CM
−
µ1 µ 2
(A.7)
The parameter that truly influences the symmetry of the stage is thus the maximum voltage
gain of the transistors, µ, that is not usually optimized from the matching standpoint. This factor
indicates the voltage source of the Thévènin equivalent circuit for the JFETs, that is the source
involved in the input loop voltage balance depicted in Fig. A-3.
Discrete JFETs can assure a best µ value of about 80 dB. To further rise this figure of merit
we ought to resort to cascode solutions, which however reduce the available voltage dynamic range
(headroom) and threaten the noise performance of the first stage.
223
Appendix A
Realization of the low-noise voltage amplifier
A.4 The input-referred noise
Noise computations are simplified by the differential structure of the amplifier; they can be
carried out on one half of the circuit and then mirrored. Moreover, the second feedback loop acts
only onto very low frequencies, and can be safely neglected for our purposes (the BGR
measurements require that instrumentation be low-noise at about 100 kHz). The first loop does not
alter the signal-to-noise ratio, and thus does not interfere with the noise calculations, that can be
carried out at open loop.
A.4.1 Noise due to passive components
• RI resistor is at the forefront of the amplifier; as for the source followers, its voltage noise
contribution can be shifted on the gate and added at the input (Blakesley’s shifting theorems).
The series noise is:
4kTR I
(A.8)
• RII resistor sees two current sources below, and conveys its noise towards the J2 couple; this is
acting as grounded gate stage and transfers such a noise towards the input J1. From there to the
IN+ and IN- gates the transfer law is known; then:
4kTRII ⋅
RI2
(R II + 2 ⋅ rs 2 )2
(A.9)
• the two RD resistors are in series for the differential signal; the cumulative noise is to be divided
for the voltage gain of the first stage, leading to
(RI + 2 ⋅ rs1 )2
2 ⋅ 4kTRD ⋅
(2 ⋅ RD )2
(A.10)
• the degeneration resistors of the current sources J3 sum their noise density contributions at RD,
one for each branch. Their current noise flow can be calculated up to the drain of J1, and are
finally amenable to the input gates, after division for 1/4:
2 ⋅ 4kTRE ⋅
1
⋅
( RII + rs 2 )
2
⋅
( RI + rs1 )
2
( RE + rs 3 ) ( RII + 2 ⋅ rs 2 ) ( RI + 2 ⋅ rs1 )
2
2
2
1
⋅ ⋅ RI2
4
(A.11)
where the current partitions on J2 and J1 have been considered
• finally, the parallel connection of the feedback resistors R1 // R2 injects its noise in J2 and RII;
from there, it follows the same path as the RII noise, and can be thus accounted for in the same
manner. The contribution is:
R I2
2 ⋅ 4kT ⋅ (R1 // R2 ) ⋅
(A.12)
(RII + 2 ⋅ rs 2 )
224
Appendix A
Realization of the low-noise voltage amplifier
The previous relations highlight how the circuit components have to be chosen in order to
lower the overall noise. They suggest that:
RD >> RI
RI << RII
RI << 2⋅RE
RI << RII2 /[2⋅(R1 // R2)]
to minimize the noise coming from the gain resistors on the drains
to keep the RII noise low
to abate the noise from the tail
to reject the noise of the feedback shunt of passives.
The above inequalities hold provided the noise flows into the transistor transconductances
and avoids the bridge resistors. We chose a rather low value for RI = 150 Ω, complying with the
low series noise requirement; RII = 2.43 kΩ to guarantee a factor > 10 between them. Also RE
were selected high, at 1.8 kΩ, also in order not to decrease the currents in the two input columns:
this will raise the gm-1 terms, and be detrimental from the point of view of the active elements.
RDs eventually feature 3.3 kΩ each, to improve the loop gain while maintaining reasonable
voltage range on the two drains.
A.4.2 Noise due to active components
The main noise terms come from the transistor couples:
• J1 requires that its series noise equivalent inputs be simply summed together, thus giving:
2 ⋅ E nJ2 1
(A.13)
• for what concerns the J1 parallel input equivalent, they happen to be shorted during the
evaluation of the total voltage equivalent EnI2, and shall not be accounted for
• the series noise of the J2 couple sees the same transfer path that was pursued by the noise coming
from R1//R2, i.e. the J2-RII elements; the double noise transfer is found to be
2 ⋅ E nJ2 2 ⋅
RI2
(R II + 2 ⋅ rs 2 )2
(A.14)
• the parallel noise InJ22 between gate and source can be broken in:
• gate injection, that is transformed by R1 // R2 and undergoes the same transfer described before,
leading to:
(R1 // R2 )2
2
⋅ RI2
2 ⋅ I nJ 2 ⋅
(A.15)
2
(RII + 2 ⋅ rs 2 )
• source injection, that is partitioned between RII and the transconductances, and then joins the
drain resistors RD in the usual way to give:
2 ⋅ I nJ2 2 ⋅
225
(R
R II2
2
II
+ 2 ⋅ rs 2 )
2
1
⋅ ⋅ R I2
4
(A.16)
Appendix A
Realization of the low-noise voltage amplifier
• J3 couple is heavily degenerated, hence its series contribution becomes a current that, after the
intermediate partitions, reaches one of the resistors RD; eventually:
(RII + rs 2 ) 1 2
E nJ2 3
⋅
⋅ ⋅R
2
(RE + rs 3 ) (RII + 2 ⋅ rs 2 )2 4 I
2
2⋅
(A.17)
• once shifted, the J3 parallel contribution reduces to a current injection from the source, from
which it climbs the JFET column ending up by creating a noise term:
æ RE ö
(R II + rs 2 )2 1 2
÷÷ ⋅
⋅ ⋅ RI
⋅ çç
2
è RE + rs 3 ø (R II + 2 ⋅ rs 2 ) 4
2
2⋅ I
2
nJ 3
(A.18)
A.4.3 Noise minimization
If we already arranged the circuit so that
RI << RII
RI << RE
then the series addendum by J2 and J3 is negligible. Unfortunately, this does not hold for the parallel
terms: they are dependent from resistive partitions that are practically fixed, thus the only way is to
minimize them at the source, by appropriately choosing the active devices. This is the reason why,
even for these two “service” stages over which no linearity requirements are imposed, high-noise
performance JFETs have been used instead of cheaper BJTs. The noise coming from J1 element
accounts in full at the input of the stage: the dual 2SK146 by Toshiba was chosen as the solution,
for all the three couples of the amplifier. The nominal levels of input white noise are:
0.85 nV/√Hz for ID > 1 mA
0.70 nV/√Hz for ID > 5 mA
Last, the A1 opamp noise remains. The series term is already differential on the drain nodes,
then it reports to the inputs in the known way:
E
2
nA1
(RI + 2 ⋅ rs1 )2
⋅
(2 ⋅ RD )2
(A.19)
The current parallel contribution differentially circulates in the input loop, and is converted to the
inputs following the relation:
2
2
I nA
⋅ (R I + 2 ⋅ rs1 )
(A.20)
1
Once again, having set
226
Appendix A
Realization of the low-noise voltage amplifier
RI << RD
(A.21)
cancels out the series term, while the other is not increased since a low value for RI was chosen.
Anyway, here also a low-noise opamp family was sought to minimize this addendum, and found in
the BiFET National LF412. The dual packaging of the circuit allows us to compact the layout
of the second feedback loop, that also needed an opamp in order to be implemented.
The biasing section of J3 is realized by means of BZX83-C4V3 Motorola Zener diode.
The typically high noise of such a reverse-operated device is common-mode with respect to the
input, and gets totally rejected - provided the symmetry of the stage is respected. The whole
amplifier had to be implemented in two different versions, in order to elude the noise injection
coming from the Zener voltage reference.
Eventually, the only two noise contributions that cannot be effectively reduced via suitable
circuit choices were:
2
(A.21)
E nAMPL
= 4kTRI + 2 ⋅ E nJ2 1
According to the device characteristics cited in the Datasheets, the total amount of input-referred
voltage noise can be estimated by writing:
2
E nAMPL
= 2.4 ⋅ 10 −19 + 2 ⋅ 7.2 ⋅ 10 −19 V 2 / Hz ò E nAMPL = 1.3 nV / Hz
(A.22)
and, adding the contribution due to the A1 opamp, the overall result comes out:
E nAMPL ≈ 2 nV / Hz
(A.23)
By the way, observe that the parallel input noise depends substantially on the InJ12 of the
input couple, which is extremely low. All the remaining contributions will be referred to the input
through the CGS of the JFETs, that at 100 kHz indeed assures an effective isolation. Since our
measurements will be devoted mainly to the BGR of the test oscillator tail, however, it was the
voltage noise that must be minimized.
A.5 PCB fabrication
The amplifier has been implemented with discrete components on a standard, lowperformance dielectric board. The simplicity of the structure lent itself to be laid out manually, in a
mixed SMD/passthrough design style. In particular, because of the need for transistor couples
sorting, we adopted 3 sockets to ease the component interchange; the passives are instead chosen
with SMD package, in order to condense the final product. The board looks like in Fig. A-4 (1:1
scale)1:
1
I have greatly appreciated the work of Mr. Sergio Masci, the Laboratory Assistant of the Physics Department, for the
PCB layout revision and final mounting.
227
Appendix A
Realization of the low-noise voltage amplifier
Fig. A-4 The layout of the PCB for the amplifier mounting. The DIP-8 pin package of the double opamp is
identified to the left, and the three 6-pins oval patterns for the JFET couples are folded on the left side of the
board.
The mirrored JFET totem pole appears to the right of figure, folded in half-circle way. The
layout of its tail resistors (top left) and gain resistors (center bottom) tries to improve the symmetry,
that goes instead lost for the feedback paths involving the operational amplifiers (the DIP 8-pins
package to the left, bottom). As usual, the ground routing proves of fundamental importance to
lower the noise: GND has been assigned the residual part of the upper metal plane. After some cutand-tries also the external metal chassis, and cable shielding, were connected to ground.
The dual power supply reaches the circuit through a shielded twisted-cable. Inputs and
outputs are instead externally wired with standard BNC cables, since the operating frequency will
never reach the GigaHertz. In Fig. A-5 the eventual appearance of the amplifier is depicted.
Fig. A-5
The final mounted board, with BNC inlets and outlets and the lower bandwidth limit control
switch.
228
Appendix A
Realization of the low-noise voltage amplifier
The black knob at the bottom of the picture is used to switch the internal resistors that
control the bandwidth of the second feedback of the schematic in Fig. A-5, for offset compensation.
In the snapshot only the capacitors featuring highest values are visible; many of the SMD
components were mounted on the bottom face of the card.
A.6 Test of the amplifier performance
The amplifier tests were performed with a network-spectrum analyzer HP4195A, stretching
the measurement range from 10 Hz to 10 MHz. The behavior of the circuit with respect to signals
was characterized by driving one input, the other being tied to ground: in fact, this kind of driving is
the same needed to test the BGR. The analyzer reports directly the input → output gain of the device
under test: after a flat-gain region (following the initial high-pass cut-off, not shown in Fig. A-6) a
–40 dB/decade decrease occurs:
40
Guadagno
differenziale
[dB]
Differential
gain [dB]
30
100
25
20
50
15
10
0
Experimental
curves
Curve sperimentali
Magnitude
Modulo
5
Fase
Phase
-50
Phase
of the
Diff. Gain
[°]
Fase del
Guadagno
[gradi]
150
35
0
-5
-100
+1
1E
+2
1E
+3
1E
+4
1E
+5
1E
1E
+6
+7
1E
Frequenza [Hz]
[Hz]
Frequency
Fig. A-6 Gain and phase of the circuit amplification, tested by means of the HP4195A network analyzer.
By reading the phase plot, the descent is derived to be due to two conjugate poles having
moderate-to-low quality factor. From the analysis of the circuit it stands out that
1. the first pole of the opamp A1, together with
2. the dominant pole of the input stage, set by the bridge capacitor onto the drains, and
3. the zero set by the resistor in series to the capacitor (much like the technique adopted in the
AAC circuit explained in Chapter 5),
create a singularity constellation such as the one illustrated in the Gauss plane of Fig. A-7. From
datasheets we educe a 12 Hz first pole and > 30 MHz second pole for the opamps; with the values
given in Fig. A-1 the first stage pole is located to 8.4 kΩ⋅ 3.3 nF → 5.7 kHz and the zero lies about
229
Appendix A
Realization of the low-noise voltage amplifier
1.8 kΩ⋅3.3 nF → 26.8 kHz. The pole splitting towards the imaginary axis explains the light bump
featured by the Bode diagram of the gain. The intermediate zero accounts for a slope reduction of
the phase diagram, that – were it only for the many poles of the loop - would decrease even more
steeply.
IMAGINARY axis
Pole-zero map of the amplifier
Bifurcation zoom
REAL axis
Fig. A-7 The scatter of singularities of the loop transfer function, and zoom on the low frequencies region
of the root locus.
In Fig. A-7 the real position of the highest pole has been shifted, to better represent the
scatter of singularities. The zoom provided in the figure shows the two conjugate dominant poles,
and further underlines that they are quite damped. Our high loop gain (almost 1.8⋅105) implies that
we already went over the maximum complex frequency of 50 kHz in figure, but the predicted pole
position can justify the measured Bode diagram. Moreover, the ideal gain is determined by the
resistor ratio
15 kΩ + 7.5 kΩ 2.43 kΩ
= 48.6
⋅
(A.24)
7.5 kΩ
150 Ω
and is almost precisely obtained by the measurements in Fig. A-6.
The theoretically predicted CMRR has been also verified. The “chirp-like” probing signal
furnished by the network analyzer has been fed to both the inputs; then the output has been
measured and normalized, giving:
230
Appendix A
Realization of the low-noise voltage amplifier
80
70
-30
CMRR[dB]
[dB]
CMRR
Common-mode
gain [dB]
Guadagno
di modo comune
[dB]
-20
-40
60
50
40
-50
30
+1
1E
a)
+
1E
2
+3
1E
+
1E
4
+5
1E
Frequenza [Hz]
Frequency
[Hz]
+6
1E
+
1E
7
1E
b)
+1
+2
1E
+3
1E
1E
+4
1E
+5
+6
1E
+7
1E
Frequenza [Hz]
[Hz]
Frequency
Fig. A-8
Common mode gain measured with the network analyzer, by tying together the inputs, a);
numerically computed CMRR, b) (from Figs. A-7 and A-8a gain ratio).
In Fig. A-8a the common-mode noise reduction due to the feedback loop is apparent, like the
loop gain lowering due to the progressive weakening of the feedback action. When used as dividing
term for the differential gain of Fig. A-6, the common-mode gain leads to Fig. A-8b for the CMRR.
The value of 78 dB at low frequency is very close to the estimation, even if the couple of resistors
that are employed to degenerate the first stage was not as identical as we hoped (a residual noise of
the Zener diode found at the output indicates this). The notch (“trap”) in the common-mode gain is
probably due to the elements of the tail; were it caused by the stages J1, A1 or RD, we would have
seen it also in the direct path transfer function.
The HP4195A works also as spectrum analyzer with –150 dB of sensibility margin; we
collected the output noise spectrum of the amplifier, and referred it back to the inputs by
automatically dividing it for the gain previously found in Fig. A-6. The inputs were shorted to
ground to measure the equivalent voltage noise (brown curve in Fig. A-9); then left open, with the
only 50 MΩ connected to the gates of J1, for reading the equivalent current noise (dark red plot).
The first plot is affected by a large amount of flicker noise (slope: -10 dB/decade) up to 10 kHz,
whereas the JFET were certified to have a noise corner frequency < 7 Hz, and the opamps have < 50
Hz declared on the datasheet. Presumably, a little current flows into the input resistors (as said in
jargon, they are not completely “cold”) giving rise to the 1/f contribution. The second curve clearly
shows the 100 Hz lowpass-shaped profile set by the resistors and the input capacitance of the
transistors, that has a value of about 30 pF.
The 50 Hz tone and relative harmonics are the usual leakage of the supply network; also
spurious tones near the kiloHertz coming from the oscilloscope CRT monitor are evidenced,
however the totally closed metal case of the amplifier provided satisfactory isolation.
231
Realization of the low-noise voltage amplifier
Rumore riferito
all'ingresso
Input-referred
voltage
noise [uV/Hz^.5]
[µV/√Hz]
Appendix A
10.000
NOISE
SPETTRISPECTRA
DI RUMORE
Input
GND
Noise
In -to
GND
1.000
Noise
In to
- 50
Input
50MOhm
MΩ
0.100
0.010
0.001
1
1E+
2
1E+
3
1E+
4
1E+
5
1E+
6
1E+
Frequenza [Hz]
Frequency
[Hz]
Fig. A-9 Noise characterization at the input of the amplifier, for both voltage equivalent noise source
(input shorted to ground) and current equivalent noise source (open input).
Around 100 kHz, our frequency of interest, the amplifier guarantees about 2.4 nV/√Hz of
input voltage noise. When compared with the hundreds of nanoVolts expected from the BGR
simulations, and also from the enhanced phase noise theory, this looks like a very appreciable noise
level. The slow up-ramping of the noise after the dip at 10 kHz is due to an imperfect readout of the
amplifier gain, which in turn impacts on the quality of the output noise equalization.
232
Appendix B
Temperature influence on sensitivity
Appendix B
Temperature influence on sensitivity
A slight correction to the KTAIL devised in Chapter 4, due to the thermal effects acting within the package of
the test chips, is reported. The ω0(IT) curve is a little affected by the temperature increase, so that the
theoretical sensitivity coefficient is brought even closer to the experimental results, by considering also this
effect in the computation.
B.1 Oscillation frequency characterization
in temperature-controlled environment
O
ne suspicion can be risen about the SSCR measurements of the STARMAN VCOs: the role
of temperature variations. Since the experimental technique for determining KTAIL
sensitivity relies on the carrier displacement when the tail current is changed, one may
wonder if the frequency modification is due to loop delay modulation or heating effects affecting the
LC tank. The open-loop analysis of Chapter 4 has clarified the dominant role of the additional pole
jitter in determining phase noise; anyway, the thermal effects are of completely different nature, and
their contribution is additive to the ones found so far. Once the known sensitivity to the tail noise
has been properly reduced, this independent mechanism could become limiting.
The idea behind this new measurement is relatively simple1: the change in ITAIL modifies the
power consumption of the VCO cell too, and - through the thermal resistances - the die temperature.
This environmental variation could in turn change the parameters of LC tank (possibly, the
capacitance of varactor) and induce a shift in the oscillation frequency. Rather than indirect issue,
this can be classified more effectively as a matter of direct stability [37].
Our experimental procedure has been carried out in the most general possible way. The test
board carrying the VCO chip was hermetically closed in the climatic chamber ACS Minity 55,
capable of generating temperatures in the range -55°C ÷ +130 °C. The climate conditions are
electronically stabilized by a PID ACS J6000 controller. Thus, the external parameter - TAMB - of
the chain depicted in Fig. B-1 is under our control.
1
... but, like most simple ideas, it required a kind of genius to be devised: I wish gratefully acknowledge the original tip
by Prof. R. Castello.
233
Appendix B
Temperature influence on sensitivity
TJ
θJ-P
θP-A
Tamb
PDISS
TP
CP-A
Fig. B-1 Equivalent thermal network of the system under test (ambient ← package ← dissipating junction).
For every constant tail biasing, the dissipated power PDISS is constant too; the voltage drop
along the resistance series is then fixed, and controlling TAMB is like controlling TJ. We performed
measurements at four different external temperatures, reconstructing the f0 vs. A0 plots. Each new
carrier frequency was given enough time to settle; i.e., we waited at least 2 minutes before switching
to the next biasing condition. The thermal time constant τTH = RTH⋅ CTH has not been figured out,
since the thermal capacitance is unknown (mass and specific heat are needed), but a few seconds are
intuitively sufficient for the package to absorb or irradiate heat. In fact, the shift in ω0 after touching
the package with a finger is almost instantaneous.
From outside the chip we force the junction temperature TJ, and assure that ITAIL keeps
unchanged by monitoring it with a tester. The temperatures were set at -10° C, +10°C, +18° C
(ambient) and +50° C. The results are reported in Fig. B-2.
Frequenza difrequency
oscillazione [GHz]
[GHz]
Oscillation
2.70
2.65
2.60
2.55
T = -10 °C
T = +10 °C
2.50
T = Tamb = +18 °C
T = +50 °C
2.45
0
2
4
6
8
10
12
Corrente
di coda
Tail current
I [mA]
[mA]
TAIL
Fig. B-2
Set of frequency shift measurements in the temperature-controlled environment. The range of
temperature has been chosen according to the typical testing conditions set forth in the wireless standards.
The frequency displacement comes out to be noticeable. Between –10°C and +10°C we can
estimate a temperature coefficient of about -340 ppm/°C, to be compared with the -430 ppm/°C of
234
Appendix B
Temperature influence on sensitivity
[59] and the -230 ppm/°C of [61]. Whether it is due to varactors (inductors are inert structures, much
less sensitive to heat-induced effects than the dopant into the semiconductor, [132]) or other
parasitic capacitances in the oscillator, the ω0 shift can be explained by recalling that, for a reversebiased unilateral abrupt junction (m = 0.5), it is:
Cvar =
qε Si N dop
(B.1)
2(φbi + VINV )
were Ndop is the doping concentration. By explicitly expressing the intrinsic concentration as a
function of temperature we have:
ni = N cond N val ⋅ e
−
E gap
2 kT
∝T
3/ 2
⋅e
−
E gap
2 kT
(B.2)
and, remembering that the built-in potential depends in turn from the temperature, we write:
φbi =
æN N ö
kT
⋅ lnç acc 2 don ÷
ç
÷
q
ni
è
ø
(B.3)
Finally, the global relation that links temperature → capacitance is (α and β indicate constant
parameters):
1
1
Cinc ∝
∝
φbi + VINV
E ö
æ
(B.4)
αT ⋅ ç ln β − 3lnT + gap ÷
2kT ø
è
Although difficult to manipulate, the formula shows that increasing temperatures make the
denominator decrease, or, the varactor augment its capacitance. More intuitively, by considering the
doped zones, p and n, like two carrier gases inside the lattice2 an increase in temperature causes a
gas expansion, that tends to shrink the depletion layer - hence rising the capacitance CVAR. The two
plates of the capacitor get closer, and the frequency decreases. This mechanism affects both the
varactors and the parasitics of the BJT of the transconductor, and the two effects concur in lowering
the oscillation frequency. A similar, though less regular, behavior has also been observed on a
varactor-tuned microwave oscillator [133].
B.2 Thermal adjustments on KTAIL
The double effect through which ITAIL interacts with f0 (the indirect stability due to the poles
of the transconductor cell, and the direct stability linked to the thermal variations following heat
2
In accordance with the original Drude gas theory of conduction in metals.
235
Appendix B
Temperature influence on sensitivity
dissipation) can be expressed in a unified analytical form by adopting partial derivatives. In fact, by
exploiting the dependence
f 0 = f 0 ω poli , Tj
(B.5)
(
)
the frequency variations can be expressed by the formula:

∂ω poli
∂f 0
∂f
∆f 0 =
∆I =  0 ⋅
 ∂ω poli ∂I
∂I

∂Tj
∂f
+ 0 Tj ⋅
∂Tj
∂I
( )
T j = cost

 ⋅ ∆I

ω poli = cost 
(B.6)
At first place in the relation it appears the term that was taken into account in the analysis of
Chapter 5, quantifying the indirect stability. The second addendum has been neglected up to now,
but we are able to figure it out thanks to the new measurements available. The open loop Eldo
simulations previously presented were performed at the steady temperature of 27° C, of course,
without encompassing the thermal dynamics; and, since they match almost precisely the frequency
behavior versus the tail bias changes, any other interaction could be ruled out without any additional
investigation. We already know the entity of the discrepancy between the experimental results, as
obtained at ambient temperature, and the corresponding predictions by simulation; the curves in Fig.
4-19 are a representation of the comparison. What is explained now is the crossing between the plots
of that figure, that was quantitatively small and consequently was ascribed to modeling inaccuracies.
The different curve behavior is compatible with the thermal mechanism under test: in fact, the
increase of current in the abscissa leads to increase in power consumption and dissipation, rising the
junction temperature on the die; and ultimately drives the central frequency to lower. The simulated
behavior will hence be corrected in the sense of diminishing f0, which is exactly what is needed in
order to achieve better correspondence between the two graphs.
The thermal effect analysis has found experimental support in the frequency
characterization. From the quantitative standpoint, the term
∂f 0
T
∂Tj j
( )
(B.7)
ω poli = cost
can be reasonably evaluated in the proximity of the ambient temperature by operating a numerical
differentiation that employs the central curves of Fig. B-2. They had been measured so close in
temperature just to improve the computation accuracy. At equal tail currents, the transconductor
poles are of course displaced of the same amount, and thus the constraint needed to obtain the
partial derivative is satisfied: we are actually computing only the second term of the (B.6).
The fact that the same temperature step causes different frequency effects, when the
temperature the probe step is issued around is varying in the aforementioned range, is clearly visible
in Fig. B-2. Between the upper curve and the one at +18 °C there is a temperature difference very
similar to the one existing between the +18 °C and the lower plot; thus, nearly identical frequency
jumps would have been expected, but this is only approximately true. It indicates anyway that the
estimation of the derivative in the equation preserves its validity, practically on the entire
temperature range scanned (the standard characterization usually goes from -20 °C to +50 °C, [2],
236
Appendix B
Temperature influence on sensitivity
not far from ours). After having performed calculations a monotonic curve is extracted, variable
between 700 kHz/°C at low currents and 1.6 MHz/°C at the peak biasing imparted to the VCO cell.
∂ Tj
The
factor deals with thermal resistances, hence with unknown parameters. By
∂I
assuming of being capable of estimating the power dissipated in the IC, it may be written:
∂Tj ∂ ( Pdissϑ J − A ) ∂ (Vcc I )
=
=
ϑ J − A = Vccϑ J − A
∂I
∂I
∂I
(B.8)
What is really interesting is the difference in the dissipation, and this greatly simplifies the
procedure. It can be reasonably hypothesized that the only block changing its power consumption is
the VCO, that is the best known element on the die. Other blocks such as the frequency divider or
the power amplifier are not varying their working regime when A0 is changing, at least before
saturation occurs. The expression for the second factor can hence be composed, by knowing the
thermal impedance of the junction-package interface (θJ-P) seen in series to the packageenvironment dissipation (θP-A). The first datum is known after [117]; in the ST datasheet we find:
θJ-C = 48 °C/W
The second coefficient is instead not known precisely. Fortunately, some universal
standardized tabulations exist (for example, manuals like [134]) that report the entire thermal
resistance between the semiconductor junctions and the climatically controlled external world. We
derived the information for our package (TQFP-32, or Thin Quad Flat Package-32 pins, with four
equal sides of 9 mm) by combining the data relative to two other plastic packages, namely QFP44
and SSOP24, that are similar in size, pin count, and outline, to the TQFP-32. Their data are
reproduced in Fig. B-3:
Fig. B-3 Thermal resistance values for two packages similar to the TQFP-32 (in shape and leads, and in
size, respectively).
237
Appendix B
Temperature influence on sensitivity
The Shrunk Small Outline Package (SSOP24) was chosen as reference to take into account
the “thin” thickness characteristic of our chip; 24 pins were the pin count closest to our one, found in
[134]. The first graph is the prominent one; with the shrinking area of the die internal to the
package, the thermal resistance rapidly grows. Moreover, the resistance does not increase much with
the diminishing number of pins; instead, it bursts suddenly when the external chip area is reduced
(see again [134], Chapter 7, pag. 7-7). In summary, starting from the data in Fig. B-3 we can
estimate, for our chip:
θP-A = 120 ÷ 150 °C/W
where we overestimate the final value, given that no heat dissipating elements (metal fins, mica
washers, etc.) have been predisposed on the board, and that the dimension and length of the traces
are quite limited (as discussed in the RF board design of Chapter 8). The power supply and ground
routing have been realized with full-sized metal planes, but they are encased between the top and
bottom layers, and cannot offer good characteristics of thermal dispersion.
After this rough physical analysis, the overall estimation is:
∂T j
∂I
= Vccϑ J − A = 3V ⋅ 200°C / W = 0.6°C / mA
(B.9)
Oscillation frequency [GHz]
By following the frequency vs. temperature curves in Fig. B-1 and multiplying by this coefficient, a
frequency correction as function of bias is derived. Fig. B-4 shows the curve comparison already
presented in Fig. 4-19, and the new behavior after thermal effects revisions have been applied:
Sperimentale
Experimental
Simulated
Simulata
Simulated
Simulata
conT°
correzione
T°
with
correction
Tail current ITAIL [mA]
Fig. B-4 Eventual correction, due to temperature effects inside the chip, made on the simulated
data. The fitting with the experimental curve is further perfected by this slight adjustment.
From a quantitative point of view, the frequency reduction is not striking (it does not exceed
15 MHz, against a total frequency decrease of about 100 MHz in the graph), nor the new effect
shifts the frequency peak, where we know the KTAIL sensitivity coefficient goes to zero. Anyway, the
same factor depends on the frequency vs. ITAIL slope rather then from the absolute values on the
ordinate, and the correction performed entails an increase in KTAIL of a factor as much as about 1.5,
or 3 dB. We can conclude that the error bar inherent to our measurement vs. prediction comparison,
238
Appendix B
Temperature influence on sensitivity
which experimentally was set to about ±1 dB by the spectrum analyzer resolution, is to be widened;
but this new effect is highly predictable, as demonstrated by this simple analysis.
Moreover, the orders of magnitude found from the evaluation of the derivatives can be
extended to almost every other LC-tank VCO case. Since the temperature variations will affect
chiefly the capacitive component of the reactive tank, whether they are varactors or parasitics, we
could always write:
∂f 0
(T j )
∂T j
ω
=
loop poles = cost
∂f 0 ∂C var ∂f 0 ∂Lvar
⋅
+
⋅
∂C var ∂T j ∂Lvar ∂T j
(B.10)
The first term can be computed as
∂f 0
f
=− 0
∂Cvar
2Cvar
(B.11)
given that
f0 =
1
2π LCvar
(B.12)
hence the factor is to be scaled only depending on the inductance/capacitance ratio adopted in the
tank. The second factor is fixed for every technology (HSB2 for example), provided that the same
kind of junction is adopted to realize varactors; and it is not markedly variable anyway, unless nonconventional devices (such as hyper-abrupt structures, for instance) are employed.
239
Appendix C
Some math behind the time-varying Syy(0)
Appendix C
Some math behind
the time-varying Syy(0)
Following is the mathematical derivation behind the fast noise estimation formulas presented
in Chapter 5.
C.1 Calculations and approximations for the spectral density noise level
L
et us briefly outline the procedure followed to determine the area of an impulse response
having the shape illustrated in Fig. C-1. For our convenience, we suppose the plot to start
during the "off" interval. The ordinate of the function for t = 0 is always 1/τOFF.
w(t0,t)
0
AOFF1
AON1
AOFF2
AON2
T+TOFF
TOFF
t
Fig. C-1 Weighing function for a noise impulse risen at t = 0, during an “off” interval of the peak detector
periodic switch. The filter under commutation progressively loses its memory with a time-modulated
exponential descent.
Provided the response begins at t0 = 0, it can be written:
∞
∞
∞
0
i =1
j =1
ò w(0, t )dt = AOFF + AON = å AOFFi + å AONj
(C.1)
240
Appendix C
Some math behind the time-varying Syy(0)
Then, for unity area impulse:
AOFF =
AON =
1
τ OFF
1
τ OFF
[τ (1−e
−TOFF τOFF
OFF
[τ (1−e
ON
−TON τON
)]⋅(1+e
)]⋅e
−
TOFF
τOFF
A converging geometric series with e −TOFF
−TOFF τOFF−TON τON
(1+e
−TOFF τOFF−TON τON
τ OFF −TON τ ON
(
)
)
+ e−2(TOFF τOFF−TON τON) +...
(C.2)
)
+ e−2(TOFF τOFF−TON τON) +...
(C.3)
ratio is recognized, then it is:
(
)
1 − e −TOFF τ OFF + τ ON 1 − e −TON τ ON e −TOFF
1 éτ
S yyOFF (0) = 2 ê OFF
τ OFF ëê
1 − e −TOFF τ OFF −TON τ ON
τ OFF
ù
ú
ûú
2
(C.4)
If the response starts at the beginning of an "on" interval, we must simply swap the position of the
exponential scaling term, now accounting for the initial "on" decay:
(
)
(
1 éτ OFF 1 − e −TOFF τ OFF e −TON τ ON + τ ON 1 − e −TON
S yyON (0) = 2 ê
τ OFF ëê
1 − e −TOFF τ OFF −TON τ ON
τ ON
)ùú
2
(C.5)
ûú
Of course, when displacing the impulse occurrence within the period, the exponential scaling
factor varies, and the two cases transform one into the other. The simplest technique to predict the
mean autocorrelation area in all the cases, is to take the arithmetic average of SyyOFF(0) and SyyON(0).
Performing little approximations, a more compact rule of thumb for estimating the noise power
density results:
S yy (0) =
1
2
2τ OFF
(
éτ OFF 1 − e −TOFF
ê
êë
τ OFF
)(1 + e
−TON τ ON
1 − e −TOFF
)+ τ (1 − e
ON
τ OFF −TON τ ON
−TON τ ON
)(1 + e
−TOFF τ OFF
)ùú
2
úû
(C.6)
After term redefinition, the (C.6) eventually becomes the (5.17) presented in Chapter 5 and shall be
scaled for the amount of input noise switched.
The shot noise 2qICP acts only during TON intervals (even if it decays inside the RPCP filter also
during TOFF). To a first order, it can be written:
(
)
(
T
1 − e −TOFF τ OFF e −TON τ ON + τ ON 1 − e −TON
d .c. éτ
S yy (0) = S yyON (0) ON = 2 ê OFF
T
τ OFF ë
1 − e −TOFF τ OFF −TON τ ON
that becomes the (5.18) in the previous text.
241
τ ON
)ù
ú
û
2
(C.7)
Appendix D
Component list for the RF boards
Appendix D
Component list for the RF boards
Here are reproduced the tables with the discrete components required to mount, in SMD, the two boards
designed in Chapter 8.
D.1 Discrete components for the DAB-FRAME6 board
H
ere is a list of the basic discrete components needed to fabricate the first RF board.
The part numbers can be found in Fig. 8-1 of Chapter 8.
Footprint
(package)
Part
Number
Component
type
U1
LM78L05ACH
DIP-Switch
Voltage regulator
Balun
LDB20C101A1500
Downconverter
TCXO Quartz
SMA-female plug
fc = 1.5 GHz
Murata
Rx/Tx with 3 VCO
16.384 MHz
50 Ohm
STMicroelectronics
Telequarz
Capacitor
100 nF
+/- 10%
EIA-1206
Capacitor
Capacitor
Capacitor
2.2 nF
47 nF
220 nF
+/- 5%
+/- 10%
+/- 10%
EIA-1206
EIA-1206
EIA-1206
Capacitor
1 nF
+/- 5%
EIA-1206
Resistor
Potentiometer
Potentiometer
Bridge-2
Bridge-3
5.6 kOhm
10 kOhm
50 kOhm
+/- 1%
+/- 10%
+/- 10%
EIA-1206
EIA-1206
EIA-1206
U2
U3
U4
U5
U6-U9
C3,C4,C12,
C18,C30
C5
C6
C13-C15
C16,C17,
C27-C29
R3
RV1
RV2
S1,S2
S3,S4
Nominal value
Manufacturer
Features
National Semiconductor
ERG
Bourns
Bourns
H03A
6 switches
2 positions
200 Ohms
diff. input
TDA 7425
Tol. +/- 1ppm
242
Appendix D
Component list for the RF boards
D.2 Discrete components for the RUN0799 board
The following is the list of the main discrete components needed to fabricate the second RF
board, for the test of the new chips. The part numbers are to be found in Fig. 8-14 of Chapter 8.
Part
Number
Component
type
Nominal value
Manufacturer
Features
U1
Ferrite bead
470 uH
Panasonic
Low current
for RF PCB
Footprint
(package)
Balun
LDB20C101A2400
LX8385-3.3CP
Voltage regulator
RF Giga3 socket
MSQFP48
SMA-female plug
50 Ohm
Capacitor
1 nF
EIA-1206
Capacitor
100 nF
EIA-1206
C6-C13,C16,C19,
C20,C21,C23-C25,
C28-C30
Capacitor
220 nF
EIA-1206
C37-C42
Capacitor
22 uF
Resistor
5.6 kOhm
Resistor (Short)
RF chokes
BLM11HB601SD
Jumper
0 Ohm
U3,U7,U8
U10-U12
U9
RF1-RF3
C1-C3,
C14,C18,C22
C31-C33
C4,C5,C15,
C17,C26,C27
R1-R4,R6-R13,
R15
R5,R14
L1-L6
JVp1,JVp2
243
Murata
Linfinity
Johnstech
International
Low drop-out (1.2 V)
(3 A typ. out)
Custom size
Manual chip load
SMT, tantalum,
low EDL, 16 Vcc
TO-220
D-size
EIA-1206
EIA-1206
Murata
Ztyp > 1200 Ohms
@ 1 GHz
EIA-0603
EIA-1206
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Acknowledgments
Acknowledgments
F
irst and foremost I want to acknowledge my co-advisor Dr. Carlo Samori, who did
everything in his power to help me in many ways, and always giving me proof of his
profound professionalism. I hope I’ll be able, sooner or later, to refund him at least the
1% of the telephone expenses he met to call me from places all around the globe and beyond.
Also my advisor, Prof. Andrea L. Lacaita, deserves major acknowledgments here. I am indebted
with Prof. Rinaldo Castello, who once again demonstrated his unbounded generosity and
competence, giving me lots of useful tips.
Other grateful mentions are dedicated to my strictest colleague at Politecnico di Milano: Dr.
Salvatore Levantino, who helped me enduring the weight of the Ph.D. effort, and who will surely
strive to further carry on this work. Special thanks to Prof. Alessandro S. Spinelli, who shared
with me both his office and his irresistible calembours for two years; to Prof. Massimo Ghioni,
always materializing when I was in need of a strong problem-solving spirit; and to Prof. Franco
Zappa, who as usual has been a precious presence to rely on, besides being a friend.
Finally, I wish to thank all of the people of HSB RF development group at STMicroelectronics in
Catania for their open-minded approach and friendliness when interfacing with me: namely, Ing.
Giovanni Calì, Ing. Felice Torrisi, Ing. Maurizio Bonaventura, Ing. Giuseppe Cantone and Ing.
Angelo Granata. Special thanks to Dr. Mario Paparo, Head of RF Design Dept., and Dr. Piero
Vita, Director of the HSB Group, who allowed me to participate to this very important time of
their industrial, and my professional, growth.
253
Tables a-d: The 4 new circuits
Tables a-d
The 4 new circuits
Tables a-d: The 4 new circuits
Table a
Phase-compensation zero
Decoupling
capacitors
Reduced bias noise
Low-noise peak detector (d.c. = 74%)
Widlar
Tables a-d: The 4 new circuits
Table b
VCATHODE
VANODE
Tables a-d: The 4 new circuits
Table c
Tank
coupling
Synthesized
inductor
Tables a-d: The 4 new circuits
Table d
Common-mode
quench resistors
1:9 Ratio
Output driver - open collector
Tables A-Q: The 17 VCO versions
Tables A-Q
The 17 VCO versions
Tables A-Q: The 17 VCO versions
Table A
Tables A-Q: The 17 VCO versions
Table B
Tables A-Q: The 17 VCO versions
Table C
Tables A-Q: The 17 VCO versions
Table D
Tables A-Q: The 17 VCO versions
Table E
Tables A-Q: The 17 VCO versions
Table F
Tables A-Q: The 17 VCO versions
Table G
Tables A-Q: The 17 VCO versions
Table H
Tables A-Q: The 17 VCO versions
Table I
Tables A-Q: The 17 VCO versions
Table J
Tables A-Q: The 17 VCO versions
Table K
Tables A-Q: The 17 VCO versions
Table L
Tables A-Q: The 17 VCO versions
Table M
Tables A-Q: The 17 VCO versions
Table N
Tables A-Q: The 17 VCO versions
Table O
Tables A-Q: The 17 VCO versions
Table P
Tables A-Q: The 17 VCO versions
Table Q
Tables I-VI: The 6 test chips
Tables I-VI
The 6 test chips
Tables I-VI: The 6 test chips
Table I
Tables I-VI: The 6 test chips
Table II
Tables I-VI: The 6 test chips
Table III
Tables I-VI: The 6 test chips
Table IV
Tables I-VI: The 6 test chips
Table V
Tables I-VI: The 6 test chips
Table VI