AN-B036
Chrontel
Application Notes
PCB Layout and Design Guide for CH7525
4 Lane DispalyPort to HDMI 1.4 Converter
1.0 INTRODUCTION
Chrontel’s CH7525 translates the DisplayPort signal to HDMI/DVI. This innovative DisplayPort receiver with an
integrated HDMI Transmitter is specially designed to target the notebook/ultrabook, tablet device and PC market
segments. Through the CH7525’s advanced decoding / encoding algorithm, the input DisplayPort high-speed
serialized multimedia data can be seamlessly converted to HDMI/DVI output.
The CH7525’s DP/eDP receiver is compliant with the DisplayPort Specification 1.2a and the Embedded DisplayPort
Specification version 1.3. With internal HDCP key Integrated, the device support HDCP 1.4 specifications. In the
device’s receiver block, which supports four DisplayPort Main Link Lanes input with data rate running at either
1.62Gb/s or 2.7Gb/s, can accept RGB digital formats in either 18 bit or 24-bit, and converted the input signal to
HDMI output up to 1920x1080@120Hz or 3840x2160@30Hz. And the CH7525 support color depth 6/8/10/12bits.
About audio the CH7525 can support up to 8-channel audio input from DP Rx and output from HDMI Tx with
sample rate up to 192 KHz.
This application note focuses only on the basic PCB layout and design guidelines for CH7525. Guidelines in
component placement, power supply decoupling, grounding, input /output signal interface are discussed in this
document.
The discussion and figures that follow reflect and describe connections based on the 48-pin QFN (6x6 mm) package
of the CH7525. Please refer to the CH7525 datasheet for the details of the pin assignments.
2.0 COMPONENT PLACEMENT AND DESIGN CONSIDERATIONS
Components associated with the CH7525 should be placed as close as possible to the respective pins. The following
discussion will describe guidelines on how to connect critical pins, as well as describe the guidelines for the
placement and layout of components associated with these pins.
2.1
Power Supply Decoupling
The optimum power supply decoupling is accomplished by placing a 0.1μF ceramic capacitor to each of the power
supply pins as shown in Figure 1. These capacitors should be connected as close as possible to their respective power
and ground pins using short and wide traces to minimize lead inductance. Whenever possible, a physical connecting
trace should connect the ground pins of the decoupling capacitors to the CH7525 ground pins, in addition to ground
vias.
2.1.1
Ground Pins
The CH7525 should be connected to a common ground plane to provide a low impedance return path for the supply
currents. Whenever possible, each of the CH7525 ground pins should be connected to its respective decoupling
capacitor ground lead directly, and then connected to the ground plane through a ground via. Short and wide traces
should be used to minimize the lead inductance. Refer to Table 1 for the Ground pins assignment.
2.1.2
Power Supply Pins
Refer to Table 1 for the Power supply pins assignment. Refer to Figure 1 for Power Supply Decoupling.
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Table 1: Power Supply Pins Assignment of the CH7525 (QFN48)
Pin Assignment
11,26
39,45
1
10,27
32
13
# of Pins
2
2
1
2
1
1
1
2
1
1
2
1
19
12,25
42
48
16,22
49
+3.3V
Type
Power
Power
Power
Power
Power
Power
Power
Ground
Ground
Ground
Ground
Ground
Symbol
DVDD
AVDD
VDD_PLL
VDDS
AVCC
AVCC_PLL
VDDH
DGND
AGND
GNDPLL
VSSH
Thermal Pad
Description
Digital Core/IO Power Supply (1.2V)
Analog Power Supply (1.2V)
PLL Power Supply (1.2V)
Digital Serializer Power Supply (1.2V)
Analog Power Supply (3.3V)
PLL Power Supply (3.3V)
Analog HDMI Tx Power Supply(3.3V)
Digital supply ground
Analog supply ground
PLL supply ground
Analog supply ground
Power supply ground
U1
L5
AVCCPLL3_31
+1.2V
L1
2
FB
13
C16
10uF
AVCCPLL
C15
0.1uF
DVDD
DGND
11, 26
12, 25
1
C1
0.1uF
C2
0.1uF
2
DVDD1_2
2
AVDD1_2
2
VDDPLL1_2
2
VDDS1_2
FB
C3
10uF
L2
L6
VDDH3_3 1
2
FB
32
C18
10uF
C17
0.1uF
49
AVDD
39,45
AVCC
AGND
42
1
C5
0.1uF
C7
0.1uF
FB
C6
10uF
Thermal Pad
L3
VDDPLL
1
1
L7
AVCC3_3 1
2
FB
19
C20
10uF
C19
0.1uF
16, 22
VDDH
GNDPLL
C8
0.1uF
48
FB
C9
10uF
L4
VSSH
VDDS
DGND
10, 27
1
C11
0.1uF
C12
0.1uF
C13
10uF
FB
CH7525
Figure 1: Power Supply Decoupling and Distribution
2.2
Internal Reference Pins
• RBIAS pin
This pin sets the Band-gap Bias Voltage. A 10 K-Ohm, 1% tolerance resistor should be connected between RBIAS
and GND as shown in Figure 2. A smaller resistance will create less Band-gap Bias voltage. This resistor should be
placed with short and wide traces as near as possible to CH7525. For optimum performance, this signal should not
overlay the analog power or analog output signals.
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R2
10K 1%
U1
C21 22pF
30
Y1
27MHz
R3
1M
31
XO
RBIAS
36
+3.3V
XI
C22 22pF
CH7525
RB
9
R1
1M
RESETB
C46
0.1uF
Figure 2: RBIAS Pin Connection and General Control
2.3
General Control Pins
• RSTB
This pin is the chip reset pin for CH7525. RSTB pin, which is internally pulled-up, places the device in the power on
reset condition when this pin is low.
There are two reset methods. One is RC reset. The power supply should be valid and stable for at least 9ms before
RSTB becomes invalid as shown in Figure 3. A 1 MΩ and 0.1uF RC reset circuit is recommended as shown in
Figure 2.
Power supply
(3.3V and 1.2V)
T1>9ms
RSTB
Figure 3: Power on and reset timing of RC
Another method is using an external reset signal. In this case, the power supply should be valid and stable for at least
9ms before the reset signal is valid. The pulse width of valid reset signal should be at least 100us. The timing is
shown in Figure 4.
Power supply
(3.3V and 1.2V)
T1>9ms
T2>100us
RSTB
Figure 4: Power on and reset timing of external reset
Note: 1. The power supply will be valid when it rises to 90% of standard level.
2. The rising threshold of RSTB is 2.4V.
3. The falling threshold of RSTB is 0.4V.
• XI, XO
27MHz crystal can be connected to these pins of XI, XO as the CH7525 optional reference clock input. In PCB
design, 27MHz crystal must be placed as close as possible to the XI and XO pins, with traces connected from point to
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point, overlaying the ground plane. Since the crystal generates timing reference for the CH7525, it is very important
that noise should not couple into these input pins.
The crystal load capacitance, CL, is usually specified in the crystal spec from the vendor. As an example to show the
load capacitors, Figure 2 shows a reference design for crystal circuit design.
2.4
Serial Port Control Pins
• SPC and SPD
SPC and SPD function as a serial interface where SPD is bi-directional data and SPC is an input only serial clock. In
the reference design, SPD and SPC pins are pulled up to AVCC (+3.3V) with 6.8k resistors as shown in Figure 5.
The 22pf capacitor can be used to decrease noise interference. Through these two pins, the firmware can be upgrade
into the internal flash memory. If not used in design, they can be either pulled high or pull low with the resistors.
R5
6.8K
6.8K
SPC
SPD
1
R4
1
U1
2
2
+3.3V
29
28
C23
C24
22p F
22p F
CH75 25
Figure 5: Serial Port Interface
2.5
Display Port Signal Pins
• DP0P/N, DP1P/N, DP2P/N, DP3P/N
These pins accept four AC-coupled differential pair signals from the DisplayPort transmitter.
Since the digital serial data of the CH7525 may be toggled at speeds up to 2.7 GHz, it is strongly recommended that
the connection of these video signals between the graphics controller and the CH7525 should be kept as short as
possible and be isolated as much as possible from the analog outputs and analog circuitry. For optimum performance,
these signals should not overlay the analog power or analog output signals. It is recommended that 5 mils traces
should be used in routing these signals. There should be 7 mils spacing between each intra pair. The length for a pair
of intra differential signals should be matched within 5 mils. The length for inter pairs should be matched within 2
inches. Bend which is smaller than 45 degrees should be avoided. The AC coupling capacitors for the serial video
inputs must be placed close to the source, as shown in Figure 6.
U1
D0N
D0P
D1N
D1P
D2N
D2P
D3N
D3P
CH7525
C25
0.1uF
37
C26
0.1uF
41
C27
0.1uF
40
C28
0.1uF
44
C29
0.1uF
43
C30
0.1uF
47
C31
0.1uF
46
C32
0.1uF
38
D0N
D0P
D1N
D1P
D2N
D2P
D3N
D3P
Souce
Figure 6: CH7525 DP Main Link Lane Inputs
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• AUXP and AUXN
These two pins are DisplayPort AUX channel control that accepts a half-duplex, bi-directional AC-coupled
differential signal.
They must have the AC-coupling capacitors, and 100nF capacitors are recommended in this document, as shown in
Figure 7.
• HPD
This output pin indicates whether this device is active or not. It also generates interrupt pulse as defined by
DisplayPort standard. Output voltage is 3.3V. A resistor more than 100K-Ohm should be connected between this pin
and GND, as shown in Figure 7.
U3
U9
AUXP
AUXN
HPD_DP
34
C35
0.1uF
33
C36
0.1uF
R14
100K
35
AUXP
AUXN
R18
100K
HPD_DP
CH7525
Souce eDP
U2
U1
AUXP
AUXN
34
C33
0.1uF
C37
0.1uF
33
C34
0.1uF
C38
0.1uF
R9
1M
HPD_DP
R8
1M
+3.3V
35
R13
1M
AUXP
AUXN
R15
1M
+3.3V
HPD_DP
CH7525
R10
100K
R11
100K
Souce DP
Figure 7: CH7525 AUX channel and HPD
2.6
HDMI Output Pins
TXC-/TXC+, TX0-/TX0+, TX1-/TX1+, TX2-/TX2+
The TXC-/TXC+, TX0-/TX0+, TX1-/TX1+, TX2-/TX2+ signals are high frequency differential signals that need to
be routed with special precautions. Since those signals are differential, they must be routed in pairs.
2.6.1
Differential Pair Impedance
To match the external cable impedance and maintain the maximal energy efficiency it is important to meet the
impedance target of 100-Ω ± 10% for the differential data/clock traces. The restriction of this impedance target is to
prevent any loss of signal strengths resulting from a reflection of unwanted signals. The impedance can be acquired
by proper design of trace length, trace width, signal layer thickness, board dielectric, etc. The HDMI differential pairs
should be routed on the top layer directly to the HDMI connector pads if possible.
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Trace Routing Length
To prevent from capacitive and impedance loading, trace lengths should be kept as minimal as possible. Vias and
bends should always be minimized; inductive effects may be introduced, causing spikes in the signals. Trace routing
lengths from CH7525 to the HDMI connector are limited to a maximum of 2 inches. The CH7525 should be as close
to the HDMI connector as possible.
2.6.3
Length Matching for Differential Pairs
The HDMI specifies the intra-pair skew and the inter-pair skew as in Table 2. The intra-pair skew is the maximum
allowable time difference on both low-to-high and high-to-low transitions between the true and complement signals.
The inter-pair skew is the maximum allowable time difference on both low-to-high and high-to-low transitions
between any two single-ended data signals that do not constitute a differential pair.
Table 2: Maximum Skews for the HDMI Transmitter
Skew Type
Maximum at Transmitter
Intra-Pair Skew
0.15 Tbit
Inter-Pair Skew
0.20 TPixel
Where Tbit is defined as the reciprocal of Data Transfer Rate and T Pixel is defined as the reciprocal of Clock Rate.
Therefore, TPixels is 10 times Tbit. In other words, the intra-pair length matching is much more stringent than the interpair length matching.
It is recommended that length matching of both signals of a differential pair be within 5 mils. Length matching should
occur on a segment-by-segment basis. Segments might include the path between vias, resistor pads, capacitor pads, a
pin, an edge-finger pad, or any combinations of them, etc. Length matching from one pair to any other should be
within 100 mils.
Note that lengths should only be counted to the pins or pad edge. Additional etch within the edge-finger pad, for
instance, is electrically considered part of the pad itself.
2.6.4
ESD Protection for HDMI Interface
In order to minimize the hazard of ESD, a set of protection diodes are highly recommended for each HDMI
output (data and clock).
International standard EN 55024:1998 establishes 4kV as the common immunity requirement for contact discharges
in electronic systems. 8kV is also established as the common immunity requirement for air discharges in electronic
systems. International standard EN 61000-4-2:1995 / IEC 1000-4-2:1995 establishes the immunity testing and
measurement techniques.
System level ESD testing to International standard EN 61000-4-2:1995 / IEC 1000-4-2:1995 has confirmed that the
proper implementation of Chrontel recommended diode protection circuitry, using BCD AT1140 diode array devices,
will protect the CH7525 device from HDMI transmitter discharges of greater than 19kV (contact) and 20kV (air). The
AT1140 have a typical capacitance of only 0.50pF between I/O pins. This low capacitance won’t bring too much bad
effect on HDMI eye diagram test.
Figure 8 show the connection of HDMI connectors, including the recommended design of AT1140 diode array
devices. HDMI connector is used to connect the CH7525 HDMI outputs.
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+5V
7
HMTX0-
9
11
15
17
GND3
TMDA Data0-
TMDA Clock+
TMDA Clock-
CEC
Reserv ed
SCL
SDA
20
Shield
HPDET
R12
47K
+5V Power
22
HPD_HMTX19
Shield
DDC/CEC Ground
Shield
GND
TMDA Data0+
GND4
13
SC_HMTX
TMDA Data1-
21
GND
GND2
4
HMTX1+
6
HMTX1-
8
GND
10
HMTXC+
R16
R17
12
HMTXC-
1.8K
1.8K
SC_HMTX
HDMI TX (TY PE A)
HDMI TX
14
SD_HMTX
16
SD_HMTX
VDD5_DDC
18
U6
HMTX2+
1
HMTX2-
2
GND
3
HMTX1+
4
HMTX1-
5
I/O 1 I/O 8
I/O 2 I/O 7
GND GND
I/O 3 I/O 6
I/O 4 I/O 5
1
HMTX0-
2
GND
3
HMTXC+
HMTXC-
4
5
10
HMTX2+
9
HMTX2-
8
GND
7
HMTX1+
6
HMTX1-
10
SC_HMTX
9
SD_HMTX
8
GND
7
HPD_HMTX
AT1140
U5
HMTX0+
D2
SM5817
VDD5_DDC
2
HMTX0+
TMDA Data1+
GND
1
5
GND
TMDA Data2-
2
2
3
GND1
1
HMTX2-
TMDA Data2+
Shield
1
23
HMTX2+
I/O 1 I/O 8
I/O 2 I/O 7
GND GND
I/O 3 I/O 6
I/O 4 I/O 5
10
HMTX0+
9
HMTX0-
8
GND
7
U7
SC_HMTX
1
SD_HMTX
2
GND
3
HMTXC+
HPD_HMTX
6
AT1140
4
HMTXC5
I/O 1 I/O 8
I/O 2 I/O 7
GND GND
I/O 3 I/O 6
I/O 4 I/O 5
6
AT1140
Figure 8: The connection of the HDMI outputs
• HPD_HMTX
This output pin connects to the GND through a 47KΩ resistor. Refer to Figure 8 for the design example.
2.7
Audio Output
The CH7525 supports up to 8-channel audio input from DP Rx and output from HDMI Tx with sample rate up to 192
KHz. Available audio bandwidth depends on the pixel clock frequency, the video format timing, and whether or not
content protection re-synchronization is needed.
2.8
Thermal Exposed Pad Package
The CH7525 is available in 48-pin QFN package with thermal exposed pad package. The advantage of the thermal
exposed pad package is that the heat can be dissipated through the ground layer of the PCB more efficiently. When
properly implemented, the exposed pad package provides a means of reducing the thermal resistance of the CH7525.
Careful attention to the design of the PCB layout is required for good thermal performance. For maximum heat
dissipation, the exposed pad of the package should be soldered to the PCB as shown in Figure 9.
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Die
Exposed Pad
Solder
Pin
PCB
Figure 9: Cross-section of exposed pad package
Thermal pad dimension is from 4.35mm to 4.65mm (min to max), 4.35mm x 4.35mm is the minimum size
recommended for the thermal pad, and 4.65mm x 4.65mm is the maximum size. As shown in Figure 10, the thermal
land pattern should have a 4x4 grid array of 0.9 mm pitch thermal vias connected to the ground layer of the PCB.
These vias should be 0.3mm in diameter with 1 oz copper via barrel plating.
Figure 10: Thermal Land Pattern
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REFERENCE DESIGN EXAMPLE
3.0
The following schematics are to be used as a CH7525 PCB design example only. It is not a complete design. Those
who are seriously doing an application design with the CH7525 and would like to have a complete reference design
schematic, which should contact Applications within Chrontel, Inc.
3.1
Schematics of Reference Design Example
+1 .2V
1
L1
FB
2
DVDD_ 1V2
+3 .3V
C3
C1
C2
0.1uF 0.1uF 10 uF
+3.3V
4
4
C-
EN
3
SW
L3
5
FB
1
2.2uH
R1
C11
IAT A T 7151
C15
10 uF
2
S HDN
B CD A P36 02A
1
C10
10 uF
1
V out
V IN
2
6
3
C+
V in
GND
U2
5
C12
10 uF
U1
1u F
GND
C6
1
L2
FB
2
A VCCP LL
+1 .2V
VDD5_DDC +3.3V
L4
FB
C5
10 uF
2
C8
0.1uF
30 0K
18 pF
R2
30 0K
1
L6
FB
C9
10 uF
L5
FB
2
V DDH
C13
C14
10 uF 0.1uF
A VDD_ 1V2
C19
10 uF
C17
C18
0.1uF 0.1uF
L8
1
2
C16
10 uF
1
C7
0.1uF
V DDPL L_1V 2
FB
2
L7
1
FB
2
A VCC
C21
10 uF
V DDS_ 1V2
C22
0.1uF
C25
10 uF
C23
C24
0.1uF 0.1uF
2
2
R14
6.8K
HMT X2 +
U4
1
HMT X2 -
3
GND
5
HMT X0 +
7
HMT X0 -
9
1
S PC
S PD
C41
22 pF
T PA D
JP 1
C42
1
2
3
4
22 pF
HEA DE R 4
GND
11
13
S C_HMTX
GND
15
17
HPD_HMT X19
R8
47 K
T MDA Da ta 2+
GND1
T MDA Da ta 2-
T MDA Da ta 1+
GND2
T MDA Da ta 1-
T MDA Da ta 0+
GND3
T MDA Da ta 0-
T MDA Cl oc k+
GND4
T MDA Cl oc k-
CEC
Reserved
S CL
S DA
DDC/CEC Groun d
HPDET
HDMI TX
+5 V Po wer
2
R3
10 K 1 %
36
35
34
33
32
31
30
29
28
27
26
25
HPD_DPRX
A UX P_ DP RX
A UX N_ DP RX
A VCC
R6 1M
S PC
S PD
V DDS_ 1V2
DVDD_ 1V2
HMT X2 +
U9
1
HMT X2 -
2
GND
3
HMT X1 +
4
HMT X1 -
5
HMT X1 +
6
HMT X1 -
R11
R12
8
GND
1.8K
1.8K
S C_HMTX
HMT X0 -
2
S D_HMTX
GND
3
HMT XC+
12
HMT XC-
U6
HMT X0 + 1
HMT XC+ 4
14
V DD5_DDC
HMT XC-
16
5
S D_HMTX
18
HDMI TX(OUT)
S C_HMTX
U10
1
S D_HMTX
2
GND
3
HPD_HMT X
4
5
NC
C40
22 pF
I/O 1
I/O 2
NC
V SS
V SS
I/O 3
NC
NC
4
C39
22 pF
4
10
3
27MH z 30ppm
V DD5_DDC
GND
Y1
1
2
49
CH75 25
DP RX(IN)
IIC
1
0.1uF
10 uF
+3 .3V
6.8K
RES ET B
V DDS_ 1V2
DVDD_ 1V2
C38
GND
R13
C37
+3 .3V
2
1
1M R102 A UX N_ SD
DP_s in k
R4 10 0K
2
FB
GND
1M R9 2 A UX P_ SC
GND
1
GND
0R
2
1
1
L9
2
HPD_DPRX 1
20
GNDPLL
D3N
D3P
A VDD
D2N
D2P
A GND
D1N
D1P
A VDD
D0N
D0P
GND
18
1
RTN_DPP WR DPP WR
16
A VCCP LL
TX CB
TX C
V SS H
TX 0B
TX 0
V DDH
TX 1B
TX 1
V SS H
TX 2B
TX 2
HPDET
RBIAS
HDP _DP
A UX P
A UX N
A VCC
XI
XO
S PC
S PD
V DDS
DVDD
DGND
A VCCP LL 13
14
HMTXC15
HMTXC+
16
17
HMTX018
HMTX0+
V DDH 19
20
HMTX121
HMTX1+
22
23
HMTX224
HMTX2+
GND
A UX _CHn
R5
1M
V DDPL L
DDC_S CL
DDC_S DA
HPD_HM
GPIO0
GPIO1
GPIO2
GPIO3
RB
V DDS
DVDD
DGND
25
R7
19
GND
A UX _CHp
14
12
S hie ld
0.1uF
GND
GND
C36
A UX P_ SC 15
0.1uF
A UX N_ SD 17
ML_La ne0p
RX_DP 0N# RX_DP 0N
0.1uF
C33
RX_DP 0P# RX_DP 0P
C34 0.1uF
GND
S hie ld
13
GND
10
U5
1
2
3
4
5
6
7
8
9
10
11
12
V DDPL L_1V 2
+3 .3V S C_HMTX
S D_HMTX
HPD_HMT X
S hie ld
GND
ML_La ne1p ML_La ne0n
8
23
11
GND
22
0.1uF GND
A UX P_ DP RX
C35
A UX N_ DP RX
+3 .3V
9
ML_La ne1n
RX_DP 2N# RX_DP 2N
C29 0.1uF
RX_DP 2P# RX_DP 2P
C30 0.1uF
GND
6
S hie ld
7
ML_La ne2p
GND
4
21
RX_DP 1N#
0.1uF
RX_DP 1P#
GND
2
20
5
GND
ML_La ne3p ML_La ne2n
24
C32
0.1uF GND
3
ML_La ne3n
23
RX_DP 1N
C31
RX_DP 1P
1
22
C28
RX_DP 3N#
0.1uF
RX_DP 3P#
48
47
46
45
44
43
42
41
40
39
38
37
U3
RX_DP 3N
C27
RX_DP 3P
RX_DP1 N
RX_DP1 P
A VDD_1 V2
RX_DP0 N
RX_DP0 P
RX_DP3 N
RX_DP3 P
A VDD_1 V2
RX_DP2 N
RX_DP2 P
POWER OF CH7525
I/O 4
10
HMT X2 +
9
HMT X2 -
8
GND
7
6
B CD A T1 140
10
I/O 1
9
I/O2
NC
8
V SS V SS
7
I/O 3
NC
6
NC
I/O 4
NC
B CD A T1 140
10
NC
I/O 1
9
I/O 2
NC
8
V SS V SS
7
I/O 3
NC
6
NC
I/O 4
HMT X1 +
HMT X1 HMT X0 +
HMT X0 GND
HMT XC+
HMT XCS C_HMTX
S D_HMTX
GND
HPD_HMT X
B CD A T1 140
Figure 10: CH7525 Reference schematic
206-1000-036
Rev. 0.3
2014-5-30
9
CHRONTEL
3.2
AN-B036
Reference Board Preliminary BOM
Table 2: CH7517 Reference Design BOM List
Item Quantity
1
21
Reference
Part
C1,C2,C7,C8,C14,C17,C18,
0.1uF
C22,C23,C24,C27,C28,C29,
C30,C31,C32,C33,C34,C35,
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
10
12
C36,C37
C3,C5,C9,C10,C12,C13,C15,
10uF
1
1
4
8
1
2
1
1
4
1
1
2
2
1
1
1
1
1
3
1
C16,C19,C21,C25,C38
C6
C11
C39,C40,C41,C42
L1,L2,L4,L5,L6,L7,L8,L9
L3
R1,R2
R3
R4
R5,R6,R9,R10
R7
R8
R11,R12
R13,R14
U1
U2
U3
U4
U5
U6,U9,U10
Y1
1uF
18pF
22pF
FB
2.2uH
300K
10K 1%
100K
1M
0
47K
1.8K
6.8K
IAT AT7151
BCD AP3602A
DP_sink
HDMI TX
CH7525A
BCD AT1140
27MHz
206-1000-036
Rev. 0.3
2014-5-30
CHRONTEL
AN-B036
4.0 REVISION HISTORY
Table 3: Revisions
Rev.
#
0.1
0.2
Date
Section
Description
Internal Use only(rev)
2014/05/27
2014/05/29
2014/05/30
Create
Modify Aux reference schematic
Update reference schematic
Modify HDMI reference schematic
Add the thermal land pattern
0.1
0.2
0.3
all
2.5
3.0
2.6
2.8
206-1000-036
Rev. 0.3
2014-5-30
0.3
11
CHRONTEL
AN-B036
Disclaimer
This document provides technical information for the user. Chrontel reserves the right to make changes at any time
without notice to improve and supply the best possible product and is not responsible and does not assume any
liability for misapplication or use outside the limits specified in this document. We provide no warranty for the use of
our products and assume no liability for errors contained in this document. The customer should make sure that they
have the most recent data sheet version. Customers should take appropriate action to ensure their use of the products
does not infringe upon any patents. Chrontel, Inc. respects valid patent rights of third parties and does not infringe
upon or assist others to infringe upon such rights.
Chrontel PRODUCTS ARE NOT AUTHORIZED FOR AND SHOULD NOT BE USED WITHIN LIFE SUPPORT
SYSTEMS OR NUCLEAR FACILITY APPLICATIONS WITHOUT THE SPECIFIC WRITTEN CONSENT OF
Chrontel. Life support systems are those intended to support or sustain life and whose failure to perform when used
as directed can reasonably expect to result in personal injury or death.
Chrontel
Chrontel International Limited
129 Front Street, 5th floor,
Hamilton, Bermuda HM12
www.chrontel.com
E-mail: sales@chrontel.com
2014 Chrontel - All Rights Reserved.
12
206-1000-036
Rev. 0.3
2014-5-30