www.ietdl.org
Published in IET Power Electronics
Received on 12th May 2013
Revised on 6th December 2013
Accepted on 22nd January 2014
doi: 10.1049/iet-pel.2013.0373
ISSN 1755-4535
Active neutral point clamped converter for equal loss
distribution
Ayoub Taallah, Saad Mekhilef
Department of Electrical Engineering, Faculty of Engineering, University of Malaya, 50603 Kuala Lumpur, Malaysia
E-mail: saad@um.edu.my
Abstract: Active neutral point is the most attractive inverter topology in many applications such as a photovoltaic system because
of the equal loss distribution among switches. This study presents a new single-phase five-level active neutral-point clamped
converter topology. It can be applied to achieve optimal total harmonic distortion. In addition, this topology helps to obtain
voltage balancing among the capacitors. An analysis of the switching state and commutation of the converter are also
presented here in order to balance the power losses among the semiconductor devices. The simulation has been carried out in
MATLAB SIMULINK to investigate the effectiveness of the proposed topology. Experimental results are presented to
validate the proposed topology. Moreover, a comparative study has been made to show the cost-effectiveness of the proposed
topology.
1
Introduction
Neutral-point clamped (NPC) is the most well-known
multilevel configuration [1]. It was introduced in 1981 by
Nabae. It is widely used in photovoltaic and wind turbine
applications because of the following advantages it offers.
† It has lower dv/dt.
† Less voltage stress on the switches.
† Reduction of total harmonic distortion (THD) of output
and common mode current is possible.
However, the most common disadvantage of NPC
topology is voltage imbalance among the series capacitors
[2]. In many studies the balancing problem of multilevel
three phases diode-clamped was the main focus. However,
until now, the only solution that has been implemented is
for high modulation indices. Balancing is not possible
unless additional hardware is used for balancing the voltage
as the number of levels increases in the converter [3–9].
Another drawback is unequal distribution of losses among
semiconductor devices. This characteristic reduces the
maximum output power and reduces the converter
efficiency [10–14]. To maintain equal distribution of losses
among switches devices the three-level active neutral-point
clamped (3 L-ANPC) converter is considered the best
choice [15]. Since the introduction of the 3L_ANPC great
deal of attention has been given to multilevel converters
topologies [16, 17]. To achieve optimal THD active
neutral-point clamped five-level (ANPC-5 L) has been
proposed [18–21]. However, the capacitors voltage
balancing is a crucial task in ANPC and the control is also
more complex. To maintain the voltage of the capacitors in
the dc link, numerous redundancies are used to control the
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doi: 10.1049/iet-pel.2013.0373
capacitors voltage. Such topology contributes to increasing
the inverter output voltage levels and enhances the power
quality [22, 23].
This paper presents a novel single-phase 5 L-ANPC for
low-voltage applications. The waveform profile of the
inverter output is close to a pure sine wave. A technique to
make the voltage in dc-link capacitors balanced has been
proposed. To ensure the equal distribution of switching
losses two pulse-width modulation (PWM) strategies are
used and compared with each other. A brief comparison
between the proposed inverter and other counterparts is
carried out. Finally, simulation and experimentation results
are provided to ensure the feasibility of the proposed
inverter and the employed modulation techniques.
2
Proposed ANPC-5 L converters
Fig. 1 shows a single phase of the 5L_ANPC, which is a
derivative of the 3 L-ANPC inverter. The 5 L-ANPC
consists of four capacitors on the dc bus and ten
insulated-gate bipolar transistor (IGBT) switches on the dc
side of the inverter. The voltage across each capacitor is
Vdc/4. Hence, the five different voltage levels are −Vdc/2
−Vdc/4, 0, Vdc/4 and Vdc/2. The performance of ANPC
topology is prolonged by distribution losses in switches.
The proposed topology has fewer components compared
with other 5 L-ANPC circuits.
It has been mentioned above that the balancing the dc-link
capacitor voltages for a three-phase diode-clamped circuit
with more than three levels is not possible to guarantee.
The new topology 5 L-ANPC is based on single phase with
four capacitors. Fig. 2a shows that as the middle capacitor
C2, C3 decreases in voltage, C1, C4 increases to the value
of ±Vdc/2 because of the neutral point potential. Therefore,
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3
3.1
Analysis of the proposed topology
Switching state
To improve the balancing losses of the topology, the
switching states are selected so that the distribution losses
become better among the switches. Table 1 is listed with all
the probability of switching zero states.
3.2
Fig. 1 Proposed single-phase five-level inverter
after a time period, the output voltage will be three levels
instead of five levels. In this case the addition of circuitry is
inevitable, see Fig. 2b.
The proposed balancing method is based on closed-loop
voltage control. The circuit consists of four sensed dc-link
capacitors whose voltages are used to figure out the
imbalance values of each inner dc-link points. Then, these
values are sent to the balancing algorithm control block to
adjust the four switches T1, T1′ and T2, T2′ and ensure that
the capacitors remain balanced. R1 and L1 ensure that the
current is kept low. The operation of the algorithm is as follows
†
†
†
†
U2 > U1
U2 < U1
U3 > U4
U3 < U4
T1 = 0;
T1 = 1;
T2 = 0;
T2 = 1;
T1′ = 1.
T1′ = 1.
T2′ = 1.
T2′ = 0.
Commutation
At zero state, the control of conduction losses distribution can
be acquired by the proper allocation of different NPC paths.
Different commutations states have been also used to
control the switching losses. Assume that in all
commutations, the phase current and output voltages are
positive and the dc-bus capacitors are large enough such
that the voltage is kept at V/4 across each capacitor, finally
all the switches are ideal. The commutation process is
illustrated in Fig. 3.
(U1-to-0U4): The phase current commutates from upper
path one level dc rail to the upper path of neutral tap. S4c
is turned off after S2 is turned off, then S4 is turned on
after dead time, consequently the switch S2 and S4c will
experience switching turn off losses, whereas S4 experience
turn on losses. The voltages across the on-state switches S4
and S3, S5, S2c, S5c are given by VS3 = VS4 = S5 = S2c =
S5c = 0, and the voltage on each of the off-state switches
S2, S3c and S4c is equal to E, while S1 and S1c equal to 2E.
(0U4-to-U1): The reciprocal case phase current
commutates from upper path of neutral tap to upper path
one level dc rail. First S4 is turned off then S2 is turned on,
finally S4c is turned on. Hence, the switching losses occur
in S2 and S4. The voltages across the on-state switches S2,
S5, S4c and S5c are given by VS2 = VS5 = VS4c = VS5c = 0,
The voltage on each of the off-state switches S1, S3, S4,
S3c and S2c is equal to E whereas the voltage S1c is equal
to 3E. In a similar way, Table 2 summarise the distribution
of switching losses for several of the commutations.
Fig. 2 New topology 5 L-ANPC based on single phase with four capacitors
a Voltage across the capacitors C1, C2, C3 and C4
b Proposed topology including the balancing capacitors circuit
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IET Power Electron., 2014, Vol. 7, Iss. 7, pp. 1859–1867
doi: 10.1049/iet-pel.2013.0373
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Table 1 Switching states of the proposed topology
U2
U1
0U4
0U3
0U2
0U1
0U
0
0L
0L1
0L2
0L3
0L4
L1
L2
S1
S2
S3
S4
S5
S4c
S3c
S2c
S1c
S5c
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON
ON
OFF
ON
OFF
ON
OFF
OFF
OFF
ON
OFF
ON
OFF
OFF
OFF
ON
ON
ON
ON
ON
ON
OFF
ON
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON
ON
ON
ON
ON
ON
OFF
OFF
OFF
OFF
ON
OFF
ON
OFF
ON
ON
OFF
OFF
OFF
OFF
OFF
ON
OFF
OFF
ON
ON
OFF
OFF
ON
ON
OFF
OFF
OFF
OFF
ON
ON
OFF
ON
ON
ON
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON
ON
ON
ON
ON
ON
ON
ON
OFF
OFF
OFF
OFF
OFF
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON
OFF
Fig. 3 Commutation process for 5 L-ANPC
Table 2 Switching losses during the commutations
Switches
Commutation
S1
U2 ↔ U1
†*
0
E
U1 ↔ 0U4
U1 ↔ 0U31
U1 ↔ 0L2
U1 ↔ 0L1
S2
S3
S4
S5
S4c
S3c
S2c
S1c
S5c
0
0
†*
0
E
0
E
E
0
0
0
†
0
E
2E
E
E
E
4E
3E
0
0
E
E
E
0
3E
2E
0
0
E
E
†*
E
0
†*
E
0
0
0
E
0
3E
E/2
0
0
0
E
0
0
†*
0
0
†*
0
0
3E
2E
E
2E
E
0
†*
E
E/2
*
E
E/2
E
E
E
E
0
E
†*
0
0
2E
E
†
E
0
†*
E
0
E
E
3E
2E
0
0
E
2E
E
2E
E
0
E
E
E
0
0
0
†*
0
0
†*
0
0
†*
0
0
(†) Switch will experience switching losses or diode experience recovery losses for the present commutation (*) for its reverse.
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PWM strategies. Two known PWM strategies for ANPC
are presented in this section. For the ANPC topology there
are two famous classical carrier-based PWM modulation
strategies, named PWM-1 and PWM-2. A comparison
between these modulation techniques leads to our novel
power loss distribution topology. The new control method
for 3 L-ANPC was made by Floricau et al. [24], thus
reduction of the total power loss and thus to an increase in
efficiency.
(U1-to-0/0U/0 L): the commutation from the positive dc
rail to the states 0U or 0 or 0 L. The current distributes
through the upper and lower path, however only the active
switch and one diode encounter essential switching losses.
3.3
Modulation strategies
From the previous description it is clear that the new ANPC
has more flexibility because it is controlled by different
Fig. 4 Switching signals for PWM-1 and PWM-2 modulation strategies
a Switching signals for PWM-1 modulation strategy
b Switching signals for 0050WM-2 modulation strategy
Table 3 Switching sequences for the PWM-1 strategy
U2
U1
0U
0L
L1
L2
S1
S2
S3
S4
S5
S4c
S3c
S2c
S1c
S5c
ON
OFF
OFF
OFF
OFF
OFF
ON
ON
OFF
OFF
OFF
OFF
ON
ON
ON
OFF
OFF
OFF
OFF
OFF
ON
OFF
OFF
OFF
OFF
ON
ON
ON
ON
ON
OFF
OFF
OFF
ON
OFF
OFF
OFF
OFF
OFF
ON
ON
ON
OFF
OFF
OFF
OFF
ON
ON
OFF
OFF
OFF
OFF
OFF
ON
ON
ON
ON
ON
ON
OFF
Table 4 Switching sequences for the PWM-2 strategy
U2
U1
0U
0L
L1
L2
S1
S2
S3
S4
S5
S4c
S3c
S2c
S1c
S5c
ON
OFF
ON
OFF
OFF
OFF
ON
ON
ON
OFF
OFF
OFF
ON
ON
OFF
OFF
OFF
OFF
OFF
OFF
ON
ON
OFF
OFF
ON
ON
ON
OFF
OFF
ON
OFF
ON
ON
OFF
OFF
OFF
OFF
OFF
ON
OFF
ON
ON
OFF
OFF
OFF
ON
ON
ON
OFF
OFF
OFF
ON
OFF
ON
ON
ON
ON
OFF
ON
OFF
Fig. 5 Distribution losses for PWM-1 and PWM-2
a Simulated distribution of losses for PWM-1
b Simulated distribution of losses for PWM-2
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3.3.1 Strategy PWM-1: In the PWM-1 technique, control
of the S1, S1c, S5, S5c, S3 and S3c signals are at high
frequency ( fsw/2), whereas S2, S4, S2c and S4c signals are
switched at low frequency. Fig. 4a shows the switching
signals for the six switches, which are obtained by
comparing the reference signal with the four carrier waves.
Through the comparison process, six switching states are
achieved: U2 (2Vdc), L2 (−2Vdc), 0U and 0 L, see Table 3.
frequency, whereas the rest of the switching signals occur
switch at a high frequency. The signals for the six switches
are illustrated in Fig. 4b, which are obtained by comparing
the reference signal with three carrier waves. The six
switching states are achieved: U2 (2Vdc), L2 (−2Vdc), 0U
and 0 L according to Table 4.
3.3.2 Strategy PWM-2: PWM-2 strategy differs from
PWM-1 in that switching signals S3 and S3c are at low
All the modulation strategies which have been presented in
the previous section have been simulated with a carrier
4
Calculation of the losses
Fig. 6 Simulation results for switch currents and voltages of the proposed topology
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Fig. 7 Simulation results for output voltage
Table 5 Parameters simulation of proposed topology
Parameters
dc-link voltage
switching frequency
dc-link capacitors
load
resistance
inductance
Value
Vdc
fsw
EC
RL
R1
L1
200 V
5000 Hz
2200 μF
20 Ω – 50 mH
0.5 Ω
1 mH
wave frequency equal to 5 kHz, and a unity modulation index
(M = 0.99) and (PF = 1). To distribute losses equally between
the IGBTs, different commutations and zero states in the
topology can be used. The different commutation processes
which are addressed in Section 3 enable to improve the
unequal loss. To calculate the power losses analytically, a
MATLAB SIMULINK simulation model has been
developed. The semiconductor devices which have been
implemented in the simulation models are IGBTs with
anti-parallel diode incorporated in the circuit. This is
achieved by using the information provided in the datasheet
of the (HGTG20N60NB3D) device [25]. The turn-on (Eon)
and turn-off (Eoff ) switching loss values of the voltage and
current across the device, along with their junction
temperature are used to determine the energy losses with
the help of a lookup tables. By adding a heat sink to the
simulation model, the conduction and switching losses of
the semiconductor devices can be improved. Also, a
thermal description has been to be added to the
semiconductor components model. This decision was made
in order to determine the behaviour of the semiconductor
switches in the simulations similar to the behaviour of
semiconductor switches that have been used in the
implementation.
Another method is to use the fitting tool Modelling
Toolbox in MATLAB SIMULINK. From the datasheet of
Fig. 8 Voltage differences from four dc capacitors due to voltage drop
a Output voltage and current with lagging power factor PF = 0.8286 (s/A)
b Balancing capacitors with PF = 0.8286 (s/A)
c Output voltage for (R1 = 0.5 Ω and L1 = 1 mH)(s/V)
d Output voltage for (R1 = 0.5 Ω and L1 = 6 mH)(s/V)
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Fig. 9 Voltage harmonic spectrum of the proposed topology
the utilised semiconductor components, the approximate
curves of voltage drop (Von) and Eon, Eoff can be
determined from the equation in the Appendix. The
equations are given by
Eon
Von = 1.418e0.016i(t)
= 201.6e0.04418i(t) − 291.6e−0.1265i(t) × 10−6
Eoff = 323.9e0.005125i(t) × 10−6
(1)
(2)
5.1
Results and discussion
Simulation result
The simulation results which have been obtained for a
resistive load using the PWM-2 modulation strategy are
presented in Fig. 7 and the parameters of the simulation are
illustrated in Table 5.
The new balanced circuit includes two IGBTs and some
resistance. The IGBTs are complementarily turned on or off
to control the power flow among the capacitors. To achieve
voltage balancing of the dc capacitors, a feedback control
has been introduced in Section 2. However, a small voltage
differences would remain from four dc capacitors because of
voltage drop that occurs in the two IGBTs and the
resistance. Fig. 8b shows the two outer capacitors C1–C4 are
always charged so as to have the higher voltage, whereas the
two inner capacitors C2–C3 are always discharged to have
lower voltages from 0 to 0.6 s. The inner capacitor voltage
decay to zero after some period of time; thus, the ANPC_5 L
acting as a three-level inverter. To improve the performance
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doi: 10.1049/iet-pel.2013.0373
h = 100 × pload /pload + ploss or
h = 100 × pOUT /pIN
(3)
The simulation result shows that the total power losses by
PWM-1 are unequally distributed among the inverter’s
switches, which limits the output power of the converter.
Figs. 5a and b illustrate the distribution of losses for the
proposed topology. It can be seen that the switches S1, S5
and S3 suffer higher losses than others. The power
difference is created because of the frequency rate
difference among the different switches. Here, S1, S5 and
S3 switch at a higher frequency compared to S2. The
switch S4 does not have any power losses, because a
resistive load connected across it through which there is no
current passing. The distribution of the total power losses
between the switches in PWM-2 seemed more balanced
compared with the PWM-1. Fig. 6 shows the switch
currents and voltages of the proposed topology with a filter.
5
of the proposed circuit and the control technique, an
inductive load has been included. Initially, during the first
0.6 s, the dc-voltage balancing technique is not activated.
After 0.6 s, the dc-bus voltage balancing technique is
switched on. It can be seen that after 0.6 s, when voltage
balancing is achieved, the dc-bus voltage is regulated and in
steady state. After 0.6 s, Fig. 8a shows the output voltage
and current with a lagging power factor of ∼0.83. The
optimised value of the capacitor and inductor in the low-pass
filter are 5 μF and 2 mH, respectively.
The capacitor voltages and dc-bus voltage are shown in
Figs. 8c and d, respectively. The capacitor voltages remain
stable and balanced with a maximum deviation of < 5%, in
the case where R1 = 0.5 Ω and L1 = 1 mH. In the case
where R1 = 0.5 Ω and L1 = 6 mH, the maximum deviation
is < 3% and the voltage is about 50 V which means less
ripple but the costs are higher.
Fig. 9 shows the output voltage harmonic spectrum of the
proposed inverter. It can be noted that the proposed topology
records an acceptable harmonic content with a low THD
value equal to 1.95%.
The intention is not to save total converter losses, but to
distribute them equally. The efficiency of the proposed
topology has been calculated based on one of these
equations and takes a value approximately η = 96 at
low-power conditions
5.2
(4)
Hardware result
A prototype has been manufactured in order to prove the new
structure operation of 5-ANPC. IGBTs are employed as
switching devices. To produce the switching signals for the
proposed inverter, a digital signal processor (DSP)
(TMS320F28335) was used. Simulation and hardware
results clearly show the reliability of sinusoidal PWM
technique in the control of the 5-ANPC inverter. During the
hardware implementation, the inverter has been tested under
dc-link
voltage
Vdc = 50.
For
high
frequency
implementation, the modulation index is chosen as 0.9 with
a switching frequency equal to 5 kH. The experimental
result shown here does not vary that much from the
simulation results seen in Fig. 10a, for output voltage.
Fig. 10b shows experimental results for the output voltage
(Vo) and the load current (io). The archetype of the
proposed inverter that includes the following: four
high-voltage dc power supplies, multiple switching devices
and a DSP as shown in Fig. 10c
5.3
Comparison of ANPC topologies
The proposed topology provides high performance with the
lowest number of components. Therefore the propose
topology has more flexibility for power losses distribution
balance perspective on degrees of freedom. Table 6 shows
the main characteristics of the four different ANPC
topologies including the five levels of NPC as a reference.
For the ANPC [19], the cost is much higher than the
proposed topology from a three-phase point of view. From
the given topology, it can be seen that the (total
components over the output voltage) ratio in the proposed
topology is substantially lower than the other four
topologies. Furthermore, in the NPC topology, the
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Fig. 10 Experimental results for the output voltage and the load current
a Output voltage using PWM-2,
b Output voltage and current load of the proposed topology
c Prototype of the proposed topology
Table 6 Characteristics of the four different ANPC topologies
switches
IGBT
diode
number of levels
efficiency
number of capacitors
distribution of losses
additional balancing
circuit
NPC [26]
ANPC [27]
ANPC [30]
ANPC [28]
Proposed topology
8
6
5
low
4
unbalance
yes
8
0
4
high
4
balance
no
10
0
4
high
3
balance
no
8
0
5
high
9 in the three-phase operation
balance
—
10
0
5
high
4
balance
yes
distribution of losses among the switching is unbalanced
compared with others because of the active switches used
with ANPC topologies in general. ANPC topology can be
extended to three phase using only one side of series
capacitors, while the topology presented in [19] has to
duplicate for each of the three phases. Another advantage is
the balancing of capacitors voltage can be achieved for both
ANPC topologies and the proposed topology. However, the
additional circuit of the proposed topology provides more
reliability and robustness in the over load or unbalanced
load comparing other methods using the selection of
switching state sequences.
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Conclusion
A new 5 L-ANPC converter topology has been described in
this paper. The topology showed performance in both the
simulation and the experimental tests. The topology has
more degree of freedom which makes it easy to distribute
the losses among the switches and it has been confirmed by
implementing two different PWM strategies. Moreover, the
structure of the propose topology required fewer
components compared with other topologies. Furthermore, a
new strategy for balancing capacitors voltages has been
proposed, which effectively balances the dc link. Finally,
IET Power Electron., 2014, Vol. 7, Iss. 7, pp. 1859–1867
doi: 10.1049/iet-pel.2013.0373
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the experimental results were compared with MATLAB
simulation and are found to be in very close agreement. As
an extension of this work, this topology will be a good
choice for three-phase 5 L-ANPC implementation.
21
22
7
Acknowledgment
23
The authors would like to thank the Ministry of Higher
Education of Malaysia and University of Malaya for
providing financial support under the research grant No.
UM.C/HIR/MOHE/ENG/16001-00-D000017.
8
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Appendix
In any power-switching device the power losses constitute in
three main groups:
1. IGBT conduction losses
Pcond = VCE0 · ICav + rc · IC2rms
(5)
where VCE0 representing the IGBT on-state zero-current
collector–emitter voltage and rc representing the collector–
emitter on-state resistance, Tsw = (1/fsw) is the switching
period, ICav is the average current and ICrms is the rms value
of the current through the IGBT [29, 30].
2. IGBT switching losses
During the switching transient, on (off) to off (on) occur
energy losses named switching losses. It depends on the
voltage across the switch, the current through it and
switching time [27].
Pcond = fsw
t1 +tswon
t1
is · vs dt +
t2 +tsw
off
is · vs dt
(6)
t2
where fsw is the switching frequency, t1 represents the moment
when the IGBT states to turn on, t1 + tswon represents the time
needed to turn on, whereas for the turn off, t2 and t2 + tswoff . is
and vs is the instantaneous current and voltage.
3. Diode losses
Pcond = VD0 · IDav + rD · ID2 rms
(7)
where IDav is the average current and IDrms is the rms value of
the current through the diode [27].
1867
& The Institution of Engineering and Technology 2014