International Journal of Emerging Technology and Advanced Engineering
Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 3, Issue 2, February 2013)
An Improved Device Consideration for Ultra-Low Power
Applications in Junction Field Effect Transistor
Mayank Kumar1, Mukesh Kumar2, Anil Kumar3, Ashish Das4, A.K.Jaiswal5, Gaurav Nigam6,
Kamal Prakash Pandey7
1
Student,2,3,4Assistant Professor,5Professor,6Student Dept .of Electronics & Comm. Engineering SHIATS Allahabad, Uttar
Pradesh State, India
7
Assistant Professor, Dept .of Electronics & Comm. Engineering SIET Allahabad, Uttar Pradesh State, India
JFET a unipolar-transistor, which acts as a voltage
controlled current device and is a device in which current at
two electrodes is controlled by the action of an electric
field at a p-n junction.
The JFET consists semiconductor material (usually Si)
which constitutes a channel for the majority carrier flow
and gates. In a conducting semiconductor there are two
ohmic contacts between channels i.e. source and drain. The
figure II shows the device of JFET. The major
disadvantage of JFETs are large input capacitance and gate
leakage [1] [7]. To overcome these disadvantages we have
used Silicon–on-Insulator (SOI) and thus improve the
better performance of JFETs.
Silicon-on-insulator (SOI) technology has long been
used in many special applications, such as radiationhardened or high-voltage integrated circuits. It is only in
recent years that SOI has emerged as a serious contender
for low-power high-performance applications. The figure I
shows the device symbol of SOI.
Abstract -- This paper presents an improved device
consideration for low power applications in junction field
effect transistor. The need for low power applications and
scaling of JFET is beyond 30nm. The enhancement mode dual
gate n- channel JFET devices offer a grid potential for low
power applications. In the designing of low power circuits,
there are several limitations in case of C-MOS and MOSFET
devices. Here the Junction field effect transistor (JFET) device
which is easily designed and offers great applications. Over
conventional JFET architecture and performance of 45nm
silicon on insulator (SOI) and a N-channel JFET [8]. The
simulation results shown the enhancement mode n channel
JFET offer low threshold voltage 0.23V at a power supply
voltage of 0.5V i.e. very good for low voltage integrated
circuits.
Keywords - Junction field effect transistor (JEFT), nchannel JEFTs, Silicon on -insulator JFETs.
I. INTRODUCTION
In today’s driven world, numbers of integrated circuits
(ICs) are increases every year. The increasing chip capacity
or the density along with the field communications we need
the ultra low power analog integrated circuits(IC’s) due to
this used C-MOS and MOSFET. In the field (mobile)
communication increases the components which increase
the power dissipation and it has limited the maximum
supply voltage in complementary MOSFET (CMOS) ICs
[1-3]. In the case of analog integrated circuits the CMOS
ICs at ultra low voltage which down to 0.5V [4-5] . Thus
there are a several limitations in scaled CMOS for ultra low
voltage applications and in the designing. To improve this
limitations study the silicon-on-insulator (SOI) and the
enhancement N-channel Junction Field Effect Transistor
for designing the ultra-low voltage analog integrated
circuits. The enhancement JFET is reducing the voltage
supply limitation for ultra-low voltage.
Figure I SOI device symbol
Objective of this paper is to analyze the potential
performance of characteristics to designed N-channel
junction field effect transistors (JFETs) by using of
simulation tools.
292
International Journal of Emerging Technology and Advanced Engineering
Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 3, Issue 2, February 2013)
JFET CharacteristicsCut-off regionWhen Vgs<Vp and drain current goes to zero (Id=0).
Triode regionWhen Vp<Vgs<0 and Vds<Vgs-Vp thus
Id=Idss[2(1-Vgs/Vp)(Vds/-Vp)-(Vds/-Vp)2]
(I)
Saturation RegionWhen Vp<Vgs<0 and Vds>Vgs-Vp.
In the simulation process we analyze this in N type
JFETs i.e.
Ids=(q*µ*Nd*w*t)(Vds-2/3))(Vds+Vbi-Vg)3/2-((VbiVg)3/2/Vp1/2)
(II)
Using this equation we simulate the device
characteristics for the N-JFET devices study in this paper.
The Pinch Off voltage is occur when the gate to source
voltage is made more negative
(-Vgs).Vp=q*Nd*A2/(2*Ɛ)
(III)
Built in voltage
Vbi=Vt-Vp
(IV)
II. T HEORY AND METHDOLOGY
The Junction field effect transistor in N channel (nJFET)
the cross-sectional diagram is shown in figure II which
generates its structures and its characteristics i.e.(Ids Vs Vgs
& Ids Vs Vds) and characterize their performance at ultra
low voltage i.e. Vdd = 0.5V. The structures simulation was
generated by some parameters in the using of simulation
tools. In the N-JFET structures shown in figure II as N type
channel are heavily doped. N-type semiconductor channel
with a P-type region called the Gate diffused into the Ntype channel forming a reverse biased PN-junction and it is
this junction which forms the depletion region around the
gate area when no external voltages are applied. JFETs are
therefore known as depletion mode devices. With no
external Gate voltage (VG = 0), and a small voltage (VDS)
applied between the Drain and the Source, maximum
saturation current (IDSS) will flow through the channel from
the Drain to the Source restricted only by the small
depletion region around the junctions. If a small negative
voltage (-VGS) is now applied to the gate the size of the
depletion region begins to increase reducing the overall
effective area of the channel and thus reducing the current
flowing through. So by applying a reverse bias voltage
increases the width of the depletion region which in turn
reduces the conduction of the channel. The Gate voltage is
made more negative and the width of the channel decreases
until no more current flows between the Drain and the
Source and the FET is said to be "pinched-off". The voltage
at which the channel closes is called the "pinch-off voltage"
(VP ).
III. RESULTS AND D ISCUSSIONS
Characterize the N channel JFETs device and the
analytical study which the device was performed to
generate the Ids vs Vds characteristics when Vgs is constant
for some values and the next characteristics between Ids Vs
Vgs characteristics when Vds is constant for some values
and form the simulation data from the equation (II) and the
values are extracted.
VDS
Source
Electron drift velocity
V=µ*f
(V)
Ids vs Vds Characteristics n-JFETs figure III shows Ids
Vs Vds. Characteristics of n-channel JFET at various gate
to source voltage values and the threshold voltages
Vth=0.23v.The devices simulation results shows that NJFETs devices offers low threshold voltages as compared
to MOSFETS.
Drain
P-type
VGS
N-type Channel
P-type
Gate
Depletion
Layer
Figure.II N channel JFET structure
293
International Journal of Emerging Technology and Advanced Engineering
Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 3, Issue 2, February 2013)
Figure.III shows the values at constants values of
Vgs=0.1,0.2,0.3,0.4V
Figure.IV shows the values at constants values of Vds=0.2,0.3,0.4,0.5V
It observed from figure IV that V gs increases at
Vth=0.23V, increasing the cross-section of the channel and
as a result Ids increases with increases in V gs≥Vth.
Ids vs Vgs Characteristics n-JFETs- Figure.IV shows
Ids vs Vgs Characteristics of n-channel JFET at various
drain to source voltage values and the threshold voltages
Vth=0.23V. The devices simulation results shows that NJFETs devices offers low threshold voltages as compared
to MOSFETS.
Table I
Major Parameters are used in DG-JFETs
294
DEVICE
PARAMETERS
UNITS VALUES
Threshold Voltages
V
0.23
CHANNEL LENGTH
Nm
16
CHANNEL WIDTH
Nm
45
International Journal of Emerging Technology and Advanced Engineering
Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 3, Issue 2, February 2013)
Mayank Kumar obtained B.Tech. in ECE and
presently pursuing M.Tech. (Communication
System engg.) from SHIATS-Allahabad. He
guided various projects at engineering level.
His area of interest includes communication
systems and solid state electronics.
IV. CONCLUSION
In this paper, some important parameters are defined i.e.
threshold voltage, length, width and charge. Simulation
based study on the device architecture and performance of
enhancement type JFETs. The device simulation shows
better results in V-I characteristics at 0.5V. The graph
obtained between the gate to source voltage (Vgs) and drain
to source current (Ids) and the another graph shows between
the drain to source voltage (Vds) and drain to source
current (Ids) and a slight linear graph found. We have seen
the advantage of CMOS and MOSFET technology over
enhancement JFETs. Thus, the nJFETs, presented in this
paper are highly valuable device for the ultra low-voltage
analog application.
Mukesh Kumar is Asst. Prof. at SHIATSAllahabad. He obtained B.Tech. in ECE &
M.Tech. in Advanced Communication System
Engineering. He guided various projects at
engineering level. His area of interest includes
Signal processing & communication system
Anil Kumar is Asst. Prof. at SHIATSAllahabad. He obtained B.E (MMMEC,
Gorkhpur) in ECE & M.Tech. (IIT B.H.U
Formerely IT B.H.U.) in Microwave
Commun--ication Engg. and presently
pursuing Ph.D (Elect.). He guided various
projects & research He guided various projects & research
at undergraduate & years postgraduate level. He has more
than 10 teaching experience and actively involved in
research and publications. His area of interest includes
Antenna, microwave, artificial neural network and VLSI.
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Ashish Xavier Das is Asst. Prof. at SHIATSAllahabad. He obtained B.Tech. in ECE &
M.Tech. in Advanced Communication System
Engineering. He guided various projects at
engineering level. His area of interest includes
Signal processing and communication system.
A.K. Jaiswal is Prof. and Head of ECE-Dept at
SHIATS-Allahabad. He Obtained M.Sc. in
Tech. Electronic & Radio Engg. from
Allhabad University in1967. He guided
various projects & research at undergraduate &
postgraduate level. He has more than 40 years
Industrial,
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