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Jameco Part Number 1719404
Data Sheet
26182.126C
6812
DABiC-IV, 20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
A6812xLW (SOIC)
28
LOGIC
SUPPLY
2
27
SERIAL
DATA IN
OUT 20
3
26
OUT 1
OUT 19
4
25
OUT 2
OUT 18
5
24
OUT 3
OUT 17
6
23
OUT 4
OUT 16
7
22
OUT 5
OUT 15
8
21
OUT 6
OUT 14
9
20
OUT 7
LATCHES
VDD
REGISTER
VBB
LATCHES
1
SERIAL
DATA OUT
REGISTER
LOAD
SUPPLY
OUT 13
10
19
OUT 8
OUT 12
11
18
OUT 9
OUT 11
12
17
OUT 10
BLANKING
13
ST
28
16
STROBE
GROUND
14
CLK
27
15
CLOCK
BLNK
Dwg. PP-029-7
ABSOLUTE MAXIMUM RATINGS
at TA = 25°C
Logic Supply Voltage, VDD .................. 7.0 V
Driver Supply Voltage, VBB ................... 60 V
Continuous Output Current Range,
IOUT ........................ -40 mA to +15 mA
Input Voltage Range,
VIN ....................... -0.3 V to VDD + 0.3 V
Package Power Dissipation,
PD ....................................... See Graph
Operating Temperature Range, TA
(Suffix ‘E–’) ................... -40°C to +85°C
(Suffix ‘K–’) ................. -40°C to +125°C
(Suffix ‘S–’) ................... -20°C to +85°C
Storage Temperature Range,
TS ............................... -55°C to +125°C
Caution: These CMOS devices have input static
protection (Class 2) but are still susceptible to
damage if exposed to extremely high static electrical charges.
The A6812– devices combine a 20-bit CMOS shift register, accompanying data latches and control circuitry with bipolar sourcing outputs
and pnp active pull downs. Designed primarily to drive vacuum-fluorescent displays, the 60 V and -40 mA output ratings also allow these
devices to be used in many other peripheral power driver applications.
The A6812– features an increased data input rate (compared with the
older UCN/UCQ5812-F) and a controlled output slew rate.
The CMOS shift register and latches allow direct interfacing with
microprocessor-based systems. With a 3.3 V or 5 V logic supply, they
will operate to at least 10 MHz.
A CMOS serial data output permits cascade connections in applications requiring additional drive lines. Similar devices are available as
the A6810– (10 bits) and A6818– (32 bits).
The A6812– output source drivers are npn Darlingtons, capable of
sourcing up to 40 mA. The controlled output slew rate reduces electromagnetic noise, which is an important consideration in systems that include telecommunications and/or microprocessors and to meet government emissions regulations. For inter-digit blanking, all output drivers
can be disabled and all sink drivers turned on with a BLANKING input
high. The pnp active pull-downs will sink at least 2.5 mA.
Three temperature ranges are available for optimum performance
in commercial (suffix S-), industrial (suffix E-), or automotive (suffix
K-) applications. Package styles are provided for surface-mount SOIC
(suffix -LW), or minimum-area surface-mount PLCC (suffix -EP). Copper lead frames, low logic-power dissipation, and low output-saturation
voltages allow these drivers to source 25 mA from all outputs continuously to more than +43°C (suffix -LW) or +61°C (suffix -EP).
Each package is available in a lead (Pb) free version, with 100%
matte tin leadframe plating.
FEATURES
■
■
■
■
■
■
■
■
Controlled Output Slew Rate
High-Speed Data Storage
60 V Minimum Output Breakdown
High Data Input Rate
PNP Active Pull-Downs
Low Output-Saturation Voltages
Low-Power CMOS Logic and Latches
Improved Replacements for TL5812–, UCN5812–,
and UCQ5812–
6812
20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
PRODUCT SELECTION GUIDE
Part Number
A6812EEP
Pb-free
–
A6812EEP-T
Yes
A6812EEPTR
–
A6812EEPTR-T
A6812ELW
Yes
–
A6812ELW-T
Yes
A6812ELWTR
–
A6812ELWTR-T
A6812KEP
Yes
–
A6812KEP-T
Yes
A6812KEPTR
–
A6812KEPTR-T
A6812KLW
Yes
–
A6812KLW-T
Yes
A6812KLWTR
–
A6812KLWTR-T
A6812SEP
Yes
–
A6812SEP-T
Yes
A6812SEPTR
–
A6812SEPTR-T
A6812SLW
Yes
–
A6812SLW-T
Yes
A6812SLWTR
–
A6812SLWTR-T
Yes
Packing
Package
Ambient Temperature, TA
(°C)
38 pieces/tube
PLCC
800 pieces/13-in. reel
–40 to 85
27 pieces/tube
SOIC-W
1000 pieces/13-in. reel
38 pieces/tube
PLCC
800 pieces/13-in. reel
–40 to 125
27 pieces/tube
SOIC-W
1000 pieces/13-in. reel
38 pieces/tube
PLCC
800 pieces/13-in. reel
–20 to 85
27 pieces/tube
SOIC-W
1000 pieces/13-in. reel
Copyright © 2000, 2003, 2006 Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
6812
20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
SERIAL
DATA OUT
LOAD
SUPPLY
LOGIC
SUPPLY
SERIAL
DATA IN
OUT 1
2
1
V DD 28
27
26
24
7
23
18
OUT 8
OUT9
17
OUT10
ST
STROBE
CLOCK
GROUND
16
19
CLK
11
15
20
14
10
13
21
OUT11
OUT 2
22
9
12
OUT12
REGISTER
8
LATCHES
6
REGISTER
25
LATCHES
5
BLANKING
OUT18
Dwg. PP-059-1
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
OUT20
3
VBB
OUT19
4
A6812xEP (PLCC)
2.5
SU
FF
IX
2.0
'E
P'
,R
QJ
A
SU
FF
IX
1.5
=
55
oC
/W
'LW
', R
QJ
A
1.0
=
66
oC
/W
0.5
0
25
50
75
100
125
AMBIENT TEMPERATURE IN oC
150
Dwg. GP-024-2
TYPICAL INPUT CIRCUIT
TYPICAL OUTPUT DRIVER
V DD
V BB
IN
OUTN
Dwg. EP-021-19
Dwg. EP-010-5
www.allegromicro.com
6812
20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
FUNCTIONAL BLOCK DIAGRAM
LOGIC
SUPPLY
V DD
CLOCK
SERIAL
DATA IN
SERIAL-PARALLEL SHIFT REGISTER
STROBE
LATCHES
SERIAL
DATA OUT
BLANKING
MOS
BIPOLAR
LOAD
SUPPLY
VBB
GROUND
OUT 1 OUT 2 OUT 3
OUT N
Dwg. FP-013-1
TRUTH TABLE
Serial
Shift Register Contents
Data Clock
Input Input I1 I2 I3 ... IN-1 IN
IN
Serial
Data Strobe
Output Input
Latch Contents
I1
I2
I3
...
IN-1
Output Contents
IN Blanklng
I1 I2 I3 ... IN-1
H
H
R1 R2 ...
RN-2 RN-1
RN-1
L
L
R1 R2 ...
RN-2 RN-1
RN-1
X
R1 R2 R3 ...
RN-1 RN
RN
X
X
X
L
R1 R2 R3 ...
RN-1 RN
PN
H
P1 P2 P3 ...
PN-1 PN
L
P1 P2 P3 ... PN-1 PN
X
X
H
L
X
X
...
P1 P2 P3 ...
L = Low Logic Level
X
PN-1 PN
H = High Logic Level
X = Irrelevant
X
P = Present State
X
...
X
R = Previous State
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
L
L
... L
L
6812
20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
ELECTRICAL CHARACTERISTICS at TA = +25°C (A6812S-) or over operating temperature
range (A6812E- or A6812K-), VBB = 60 V unless otherwise noted.
Characteristic
Output Leakage Current
Output Voltage
Symbol
ICEX
Test Conditions
VOUT = 0 V
Limits @ VDD = 3.3 V
Limits @ VDD = 5 V
Mln.
Typ.
Max.
Min.
Typ.
Max.
Units
—
<-0.1
-15
—
<-0.1
-15
μA
57.5
58.3
—
57.5
58.3
—
V
VOUT(1)
IOUT = -25 mA
VOUT(0)
IOUT = 1 mA
—
1.0
1.5
—
1.0
1.5
V
Output Pull-Down Current
IOUT(0)
VOUT = 5 V to VBB
2.5
5.0
—
2.5
5.0
—
mA
Input Voltage
VIN(1)
2.2
—
—
3.3
—
—
V
VIN(0)
—
—
1.1
—
—
1.7
V
Input Current
Input Clamp Voltage
Serial Data Output Voltage
Maximum Clock Frequency
Logic Supply Current
IIN(1)
VIN = VDD
—
<0.01
1.0
—
<0.01
1.0
μA
IIN(0)
VIN = 0 V
—
<-0.01
-1.0
—
<-0.01
-1.0
μA
IIN = -200 μA
—
-0.8
-1.5
—
-0.8
-1.5
V
VOUT(1)
IOUT = -200 μA
2.8
3.05
—
4.5
4.75
—
V
VOUT(0)
IOUT = 200 μA
—
0.15
0.3
—
0.15
0.3
V
10*
—
—
10*
—
—
MHz
VIK
fc
IDD(1)
All Outputs High
—
0.25
0.75
—
0.3
1.0
mA
IDD(0)
All Outputs Low
—
0.25
0.75
—
0.3
1.0
mA
IBB(1)
All Outputs High, No Load
—
3.0
6.0
—
3.0
6.0
mA
IBB(0)
All Outputs Low
—
0.2
20
—
0.2
20
μA
tdis(BQ)
CL = 30 pF, 50% to 50%
—
0.7
2.0
—
0.7
2.0
μs
ten(BQ)
CL = 30 pF, 50% to 50%
—
1.8
3.0
—
1.8
3.0
μs
tp(STH-QL)
RL = 2.3 kΩ, CL 30 pF
—
0.7
2.0
—
0.7
2.0
μs
tp(STH-QH)
RL = 2.3 kΩ, CL 30 pF
—
1.8
3.0
—
1.8
3.0
μs
Output Fall Time
tf
RL = 2.3 kΩ, CL 30 pF
2.4
—
12
2.4
—
12
μs
Output Rise Time
tr
RL = 2.3 kΩ, CL 30 pF
2.4
—
12
2.4
—
12
μs
Output Slew Rate
dV/dt
RL = 2.3 kΩ, CL 30 pF
4.0
—
20
4.0
—
20
V/μs
IOUT = ±200 μA
—
50
—
—
50
—
ns
Load Supply Current
Blanking-to-Output Delay
Strobe-to-Output Delay
Clock-to-Serial Data Out Delay tp(CH-SQX)
Negative current is defined as coming out of (sourcing) the specified device terminal.
Typical data is is for design information only and is at TA = +25°C.
* Operation at a clock frequency greater than the specified minimum is possible but not warranteed.
www.allegromicro.com
6812
20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
TIMING REQUIREMENTS and SPECIFICATIONS
(Logic Levels are VDD and Ground)
C
50%
CLOCK
A
SERIAL
DATA IN
B
DATA
50%
t p(CH-SQX)
SERIAL
DATA OUT
DATA
50%
D
50%
STROBE
BLANKING
E
LOW = ALL OUTPUTS ENABLED
t p(STH-QH)
t p(STH-QL)
90%
OUT N
DATA
10%
Dwg. WP-029
HIGH = ALL OUTPUTS BLANKED (DISABLED)
BLANKING
50%
t dis(BQ)
tr
t en(BQ)
OUT N
10%
DATA
tf
90%
50%
Dwg. WP-030A
A. Data Active Time Before Clock Pulse
(Data Set-Up Time), tsu(D) ........................................ 25 ns
B. Data Active Time After Clock Pulse
(Data Hold Time), th(D) ............................................. 25 ns
C. Clock Pulse Width, tw(CH) .............................................. 50 ns
D. Time Between Clock Activation and Strobe, tsu(C) ...... 100 ns
E. Strobe Pulse Width, tw(STH) ........................................... 50 ns
NOTE – Timing is representative of a 10 MHz clock. Higher
speeds may be attainable with increased supply voltage; operation at high temperatures will reduce the specified maximum
clock frequency.
Serial Data present at the input is transferred to the shift
register on the logic “0” to logic “1” transition of the CLOCK
input pulse. On succeeding CLOCK pulses, the registers shift
data information towards the SERIAL DATA OUTPUT. The
SERIAL DATA must appear at the input prior to the rising edge
of the CLOCK input waveform.
Information present at any register is transferred to the respective latch when the STROBE is high (serial-to-parallel conversion). The latches will continue to accept new data as long
as the STROBE is held high. Applications where the latches are
bypassed (STROBE tied high) will require that the BLANKING
input be high during serial data entry.
When the BLANKING input is high, the output source drivers are disabled (OFF); the pnp active pull-down sink drivers are
ON. The information stored in the latches is not affected by the
BLANKING input. With the BLANKING input low, the outputs
are controlled by the state of their respective latches.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
6812
20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
EP Package
Dimensions in Inches
(controlling dimensions)
18
0.013
0.021
12
19
0.219
0.191
11
0.026
0.032
0.456
0.450
INDEX AREA
0.495
0.485
0.050
BSC
0.219
0.191
25
5
26
0.020
28
1
4
0.456
0.450
0.495
0.485
MIN
0.165
0.180
Dwg. MA-005-28A in
Dimensions in Millimeters
(for reference only))
18
0.331
0.533
12
19
5.56
4.85
11
0.812
0.661
11.58
11.43
12.57
12.32
1.27
BSC
5.56
4.85
INDEX AREA
25
5
26
0.51
MIN
4.57
4.20
28
1
4
11.582
11.430
12.57
12.32
Dwg. MA-005-28A mm
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
6812
20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
LW Package
Dimensions in Inches
(for reference only)
28
15
0.0125
0.0091
0.419
0.394
0.2992
0.2914
0.050
0.016
0.020
0.013
2
1
3
0.050
0.7125
0.6969
0o TO 8o
BSC
0.0926
0.1043
0.0040 MIN.
Dwg. MA-008-28A in
Dimensions in Millimeters
(controlling dimensions)
28
15
0.32
0.23
10.65
10.00
7.60
7.40
1.27
0.40
0.51
0.33
1
2
3
18.10
17.70
1.27
BSC
0o TO 8o
2.65
2.35
0.10 MIN.
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
www.allegromicro.com
Dwg. MA-008-28A mm
6812
20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
The products described here are manufactured under one or more
U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be required
to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to
verify that the information being relied upon is current.
Allegro products are not authorized for use as critical components in
life-support devices or systems without express written approval.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility
for its use; nor for any infringement of patents or other rights of third
parties which may result from its use.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000