Data Sheet
26182.14D
5895
BiMOS II 8-BIT SERIAL INPUT,
LATCHED SOURCE DRIVERS
UCN5895A
GROUND
1
CLOCK
2
SERIAL
DATA IN
3
16
CLK
SHIFT
REGISTER
VDD 15
SERIAL
DATA OUT
LOGIC
SUPPLY
14
OUTPUT
ENABLE
VBB 13
LOAD
SUPPLY
OE
STROBE
4
OUT 1
5
12
OUT 8
OUT 2
6
11
OUT 7
OUT 3
7
10
OUT 6
OUT 4
8
9
OUT 5
ST
LATCHES
Dwg. PP-026-2A
Note the UCN5895A (DIP) and the A5895SLW
(SOIC) are electrically identical and share a common
terminal number assignment.
The UCN5895A, UCN5895EP, and A5895SLW BiMOS II serialinput, latched source drivers are designed for applications emphasizing
low output saturation voltages and currents to -250 mA per output.
These smart high-side octal, driver ICs merge an 8-bit CMOS shift
register, associated CMOS latches, and CMOS control logic (strobe
and output enable) with medium current emitter-follower (sourcing)
outputs. Typical applications include incandescent or LED displays
(both directly driven and multiplexed), non-impact (i.e., thermal)
printers, relays, and solenoids.
T
C
U
D
Each device is suitable for high-side applications to -250 mA per
channel. The maximum supply voltage is 50 V and a minimum output
sustaining voltage rating of 35 V for inductive load applications. Under
normal operating conditions, the UCN5895A and UCN5895EP are
capable of providing -120 mA (8 outputs continuous and simultaneous)
at +65°C with a logic supply of 5 V. Similar devices, with higher output
current ratings, are the UCN5890A and UCN5891A.
O
y
R
l
P n
BiMOS II devices can operate at greatly improved data-input rates.
With a 5 V supply, they will typically operate at better than 5 MHz.
At 12 V, significantly higher speeds are obtained.
O
D
E ce
The CMOS inputs provide for minimum loading and are compatible
with standard CMOS, PMOS, and NMOS circuits. TTL or DTL circuits
may require the use of appropriate pull-up resistors to ensure a proper
input-logic high. A CMOS serial data output allows cascading these
devices in multiple drive-line applications required by many dot matrix,
alphanumeric, and bar graph displays.
U
n
IN re
ABSOLUTE MAXIMUM RATINGS
at TA = +25°C
e
T
f
N Re
Output Voltage, VOUT . . . . . . . . . . . . . . 50 V
Logic Supply Voltage Range,
VDD . . . . . . . . . . . . . . . . . . 4.5 V to 12 V
Driver Supply Voltage Range,
VBB . . . . . . . . . . . . . . . . . . 5.0 V to 50 V
Input Voltage Range,
VIN . . . . . . . . . . . -0.3 V to VDD + 0.3 V
Continuous Output Current,
IOUT . . . . . . . . . . . . . . . . . . . . . -250 mA
Allowable Package Power Dissipation,
PD . . . . . . . . . . . . . . . . . . . . See Graph
Operating Temperature Range,
TA . . . . . . . . . . . . . . . . . -20°C to +85°C
Storage Temperature Range,
TS . . . . . . . . . . . . . . . . -55°C to +150°C
O
C or
S
I
D
F
Caution: CMOS devices have input-static
protection, but are susceptible to damage when
exposed to extremely high static electrical
charges.
These devices are rated for continuous operation over the temperature range of -20°C to +85°C. Because of limitations on package
power dissipation, the simultaneous operation of all output drivers may
require a reduction in duty cycle. The UCN5895A is supplied in a
standard 16-pin dual in-line plastic package with a copper lead frame
for increased allowable package power dissipation. The UCN5895EP
is supplied in a 20-lead plastic leaded chip carrier for minimum area,
surface-mount applications. The A5895SLW is supplied in a 16-lead
wide-body plastic SOIC.
FEATURES
■
■
■
■
■
Low Output-Saturation Voltage
Source Outputs to 50 V
Output Current to -250 mA
To 3.3 MHz Data-lnput Rate
Low-Power CMOS Logic & Latches
Always order by complete part number, e.g., UCN5895A .
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
5895
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
FUNCTIONAL BLOCK DIAGRAM
2.5
SUFFIX 'EP', R θJA = 59°C/W
2.0
CLOCK
SUFFIX 'A', R θJA = 60°C/W
1.5
SERIAL
DATA IN
8-BIT SERIAL-PARALLEL SHIFT REGISTER
STROBE
LATCHES
GROUND
1.0
SERIAL
DATA OUT
VDD
OUTPUT
ENABLE
MOS
BIPOLAR
0.5
VBB
SUFFIX 'LW', R θJA = 80°C/W
0
25
50
75
100
125
AMBIENT TEMPERATURE IN °C
150
OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8
Dwg. No. A-12,654
Dwg. GP-024-4
TYPICAL INPUT CIRCUIT
VDD
UCN5895EP
IN
Dwg. EP-010-4A
TYPICAL OUTPUT DRIVER
Dwg. No. A-14,368
Dwg. No. A-12,655
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 1985, 2004 Allegro MicroSystems, Inc.
5895
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 50 V, VDD = 5 V and 12 V
(unless otherwise noted).
Characteristic
Output Leakage Current
Output Saturation Voltage
Output Sustaining Voltage
Input Voltage
Input Current
Input lmpedance
Min.
Limits
Max.
Units
TA = +25°C
—
-50
µA
TA = +70°C
—
-100
µA
IOUT = -60 mA
—
1.1
V
IOUT = -120 mA
—
1.2
V
IOUT = -120 mA, L = 2 mH
35
—
V
VDD = 5.0 V
3.5
5.3
V
VDD = 12 V
10.5
12.3
V
VIN(0)
VDD = 5 V to 12 V
-0.3
+0.8
V
IIN(1)
VDD = VIN = 5.0 V
—
50
µA
VDD = VIN = 12 V
—
240
µA
VDD = 5.0 V
100
—
kΩ
VDD = 12 V
50
—
kΩ
3.3
—
MHz
VDD = 5.0 V
—
20
kΩ
VDD = 12 V
—
6.0
kΩ
Symbol
IOUT
VCE(SAT)
VCE(sus)
VIN(1)
zIN
Test Conditions
Max. Clock Frequency
fCLK
Serial Data-Output
Resistance
rOUT
Turn-ON Delay
tPLH
Output Enable to Output, IOUT = -120 mA
—
2.0
µs
Turn-OFF Delay
tPHL
Output Enable to Output, IOUT = -120 mA
—
10
µs
Supply Current
IBB
All outputs ON, All outputs open
—
10
mA
All outputs OFF
—
200
µA
VDD = 5 V, All outputs OFF, Inputs = 0 V
—
100
µA
VDD = 12 V, All outputs OFF, Inputs = 0 V
—
200
µA
VDD = 5 V, One output ON, All inputs = 0 V
—
1.0
mA
VDD = 12 V, One output ON, All inputs = 0 V
—
3.0
mA
VR = 25 V, TA = +25°C
—
50
µA
VR = 25 V, TA = +70°C
—
100
µA
IF = 120 mA
—
2.0
V
IDD
Diode Leakage Current
Diode Forward Voltage
IR
VF
5895
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
CLOCK
A
B
DATA IN
D
E
F
C
STROBE
BLANKING
G
OUTN
Dwg. No. A-12,649A
TIMING CONDITIONS
(VDD = 5.0 V, Logic Levels are VDD and Ground)
A.
Minimum Data Active Time Before Clock Pulse
(Data Set-Up Time) ................................................................. 75 ns
B.
Minimum Data Active Time After Clock Pulse
(Data Hold Time) ..................................................................... 75 ns
C.
Minimum Data Pulse Width ........................................................ 150 ns
D.
Minimum Clock Pulse Width ...................................................... 150 ns
E.
Minimum Time Between Clock Activation and Strobe ............... 300 ns
F.
Minimum Strobe Pulse Width ..................................................... 100 ns
G.
Typical Time Between Strobe Activation and
Output Transition .................................................................... 1.0 µs
Serial Data present at the input is transferred to the shift register
on the logic “0” to logic “1” transition of the CLOCK input pulse. On
succeeding CLOCK pulses, the registers shift data information towards
the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the
input prior to the rising edge of the CLOCK input waveform.
Information present at any register is transferred to its respective
latch when the STROBE is high (serial-to-parallel conversion). The
latches will continue to accept new data as long as the STROBE is
held high. Applications where the latches are bypassed (STROBE tied
high) will require that the OUTPUT ENABLE input be high during serial
data entry.
When the OUTPUT ENABLE input is high, all of the output buffers
are disabled (OFF) without affecting the information stored in the
latches or shift register. With the OUTPUT ENABLE input low, the
outputs are controlled by the state of their respective latches.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
5895
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
TYPICAL APPLICATION
+ 12 V
UCN5895A
1
CLOCK
2
DATA IN
3
SHIFT
REGISTER
LATCHES
4
STROBE
VDD
15
OE
14
VBB
13
5
12
6
11
7
10
8
9
1 C
16
DATA IN
2
15
3
14
5
STROBE
6
OUTPUT
ENABLE
TO
OTHER
DIGITS
13
LATCHES
DATA OUT
SHIFT REGISTER
CLOCK
4
OUTPUT ENABLE
(ACTIVE LOW)
TO OTHER SEGMENTS
UCN5821A
+ 12 V
DATA OUT
FOR > 8 SEGMENTS
PER DIGIT
16
12
11
7
10
8
99
Dwg. No. B-1541
TRUTH TABLE
Serial
Shift Register Contents
Data Clock
Input Input I1 I2 I3 ... IN-1 IN
H
Serial
Data Strobe
Output Input
Latch Contents
I1
I2
I3
...
IN-1
Output Contents
IN
Output
Enable
I1 I2 I3 ... IN-1 IN
H
R1 R2 ...
RN-2 RN-1
RN-1
L
L
R1 R2 ...
RN-2 RN-1
RN-1
X
R1 R2 R3 ...
RN-1 RN
RN
X
X
X
L
R1 R2 R3 ...
PN
H
P1 P2 P3 ...
PN-1 PN
L
P1 P2 P3 ... PN-1 PN
X
X
H
L
X
X
...
P1 P2 P3 ...
L = Low Logic Level
X
PN-1 PN
H = High Logic Level
X = Irrelevant
X
P = Present State
X
...
RN-1 RN
X
R = Previous State
L
L
... L
L
5895
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
UCN5895A
Dimensions in Inches
(controlling dimensions)
0.014
0.008
9
16
0.430
MAX
0.280
0.240
0.300
BSC
1
0.070
0.045
0.100
0.775
0.735
8
0.005
BSC
MIN
0.210
MAX
0.015
0.150
0.115
MIN
0.022
0.014
Dwg. MA-001-16A in
Dimensions in Millimeters
(for reference only)
0.355
0.204
9
16
10.92
MAX
7.11
6.10
7.62
BSC
1
1.77
1.15
2.54
19.68
18.67
BSC
8
0.13
MIN
5.33
MAX
0.39
3.81
2.93
MIN
0.558
0.356
Dwg. MA-001-16A mm
NOTES: 1. Lead thickness is measured at seating plane or below.
2. Lead spacing tolerance is non-cumulative.
3. Exact body and lead configuration at vendor’s option within limits shown.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
5895
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
UCN5895EP
Dimensions in Inches
(controlling dimensions)
13
9
0.021
0.013
8
14
0.169
0.141
0.032
0.026
0.395
0.385
INDEX AREA
0.356
0.350
0.050
0.169
0.141
BSC
18
4
19
20
1
2
3
0.356
0.350
0.020
MIN
0.395
0.385
0.180
0.165
Dwg. MA-005-20A in
Dimensions in Millimeters
(for reference only)
13
9
0.533
0.331
10.03
9.78
0.812
0.661
INDEX AREA
9.042
8.890
1.27
4.29
3.58
8
14
4.29
3.58
BSC
18
4
19
0.51
MIN
4.57
4.20
20
1
2
3
9.042
8.890
10.03
9.78
Dwg. MA-005-20A mm
NOTES: 1. Lead spacing tolerance is non-cumulative.
2. Exact body and lead configuration at vendor’s option within limits shown.
5895
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
A5895SLW
Dimensions in Inches
(for reference only)
16
9
0.0125
0.0091
0.419
0.394
0.2992
0.2914
0.050
0.016
0.020
0.013
1
2
0.050
3
0° TO 8°
BSC
0.4133
0.3977
0.0926
0.1043
Dwg. MA-008-16A in
0.0040 MIN.
Dimensions in Millimeters
(controlling dimensions)
16
9
0.32
0.23
10.65
10.00
7.60
7.40
1.27
0.40
0.51
0.33
1
2
1.27
3
BSC
10.50
10.10
2.65
2.35
0.10 MIN.
NOTES: 1. Lead spacing tolerance is non-cumulative.
2. Exact body and lead configuration at vendor’s option
within limits shown.
0° TO 8°
Allegro MicroSystems, Inc. reserves the right to make, from time to time,
such departures from the detail specifications as may be required to permit
improvements in the design
of its products.
Dwg. MA-008-16A
mm
The information included herein is believed to be accurate and reliable.
However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor
for any infringements of patents or other rights of third parties which may result
from its use.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000