Clock and Timing ICs
Analog Devices offers innovative clock and timing
solutions designed to improve system performance, enable
new architectures, and lower development and manufacturing
costs. Products feature low jitter and low phase noise for clock
cleanup, synchronization, generation, delay, and distribution.
www.analog.com/clock-timing
High Speed Comparators
Voltage
Input
Supply (V) Range (V)
Part Number
ADCMP565/ADCMP566/
ADCMP567
ADCMP561/ADCMP562/
ADCMP563/ADCMP564
ADCMP572/ADCMP573
ADCMP580/ADCMP581/
ADCMP582
ADCMP600/ADCMP601/
ADCMP602/ADCMP603
ADCMP604/ADCMP605/
ADCMP606/ADCMP607
ADCMP608/ADCMP609
Random
Jitter
(ps rms)
Features: Latch
Hysteresis,
Shutdown
Package
20-lead PLCC/
32-lead LFCSP
16-lead QSOP/
20-lead QSOP
0.3
2
PECL and ECL
0.5
L
+5, –5.2
–2 to +3
0.75
2
PECL and ECL
1
L, H
3.3 to 5.2
–0.2 to
+3
0.15
1
SiGe CML and PECL
0.2
L, H
16-lead LFCSP
+5, –5.2
–2 to +3
0.15
1
SiGe CML, PECL,
and ECL
0.2
L, H
16-lead LFCSP
2.5 to 5.5
Rail-to-rail
3
1
Low glitch TTL/CMOS
—
L, H, S
5-lead SC70/6-lead SC70/
8-lead MSOP/12-lead LFCSP
2.5 to 5.5
Rail-to-rail
0.75
1
LVDS and CML
<1.5
L, H, S
6-lead SC70/12-lead LFCSP
2.5 to 5.5
Rail-to-rail
–VS to VS
–2
0 to 3
40
1
Low glitch TTL/CMOS
—
L, H, S
6-lead SC70/12-lead LFCSP
45
1
Low glitch TTL/CMOS
—
L, H
8-lead DIP/8-lead SOIC
5.5
1, 2
TTL/CMOS
—
L
8-lead SOIC/14-lead TSSOP
1, 4
TTL/CMOS
—
L
8-lead SOIC/16-lead SOIC
+5, –5.2
–5 to +3
–2.5 to
+5
7
6
1, 4
ECL
—
L
16-lead SOIC/16-lead DIP/
20-lead PLCC
3, ±5
–5 to +4
23 and 65
4
TTL/CMOS
—
—
16-lead SOIC/16-lead TSSOP
AD8611/AD8612
3 to 5
CMP401/CMP402
Output Logic
–2 to +3
5, ±15
AD96685/AD96687
Number
Per
Package
+5, –5.2
AD790
AD8561/AD8564
Prop Delay
(ns)
+5, –5
Direct Digital Synthesizers for Clock/Timing Applications
AD9831
AD9832
Master Clock
(MHz)
25
25
AD9833
25
10
28
2.3 to 5.5
AD9830
50
10
32
5
AD9834
50
10
28
2.3 to 5.5
AD9835
AD9850
50
125
10
10
32
32
5
3.3, 5.0
AD9851
180
10
32
3.3, 5.0
AD9852/AD9854
300
12
48
3.3
AD9859
400
10
32
1.8, 3.3
AD9956
400
14
48
1.8, 3.3
AD9951/ AD9952/
AD9953/AD9954
400
14
32
1.8, 3.3
AD9911
500
10
32
1.8, 3.3
AD9958/AD9959
500
10
32
1.8, 3.3
AD9858
1000
10
32
3.3, 5.0
AD9910
1000
14
32
1.8, 3.3
RAM, polar modulation, phase/
frequency/amp ramp, clock multiplier
Serial or
16-bit
parallel
100-lead TQFP/EP
AD9912
1000
14
48
1.8, 3.3
Spur reduction, 1 GHz PLL,
comparator, clock multiplier
Serial
64-lead LFCSP
Part Number
DAC Resolution Tuning Word Nominal Supply
(Bits)
Width (Bits)
(V)
10
32
3.3, 5.0
10
32
3.3, 5.0
Additional Features
Low power, low cost
Small package size
Low power, programmable
waveform generator
Low cost
Low power, low cost with
integrated comparator
Low cost, small package size
Integrated comparator
Integrated comparator,
clock multiplier
Integrated comparator,
clock multiplier;
chirp mode, quadrature outputs
Low power with integrated
clock multiplier
Integrated 2.7 GHz PLL
Low power family offering RAM,
linear sweep, comparator, clock
multiplier
Integrated clock multiplier,
spur reduction
Low power, low phase noise,
multichannel (dual, quad) DDS
with clock multiplier
Integrated charge pump, phase
frequency detector, mixer
I/O
Interface
Parallel
Serial
48-lead TQFP
16-lead TSSOP
Serial
10-lead MSOP
Parallel
48-lead TQFP
Serial
20-lead TSSOP
Serial
Both
16-lead TSSOP
28-lead SSOP
Both
28-lead SSOP
Both
80-lead LQFP/TQFP
Serial
48-lead TQFP/EP
Serial
48-lead MLF
Serial
48-lead TQFP/EP
Serial
56-lead LFCSP
Serial
56-lead LFCSP
Both
100-lead TQFP/EP
Package
14-Channel Clock Generator Improves System Performance
High performance converters are key components in today’s wireless
communication systems. To take full advantage of these high speed and
high accuracy ADCs and DACs, a reliable and low jitter clock source is
required.
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The AD9516 offers an integrated clock generation and 14-channel
distribution solution for a 4-channel Rx/Tx digital IF stage in a typical
base station, as shown in the example. The AD9516 features a
complete on-chip PLL with VCO, and its buffer stage’s additive rms
jitter is less than 300 femtoseconds (fs). This allows the device to
perform jitter cleanup and reproduces all required clocks for two
dual 14-bit, 150 MSPS ADCs, AD6655, and four 14-bit, 1 GSPS DACs,
AD9779, as well as FPGAs for a complete system clock solution.
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AD9516’s on-chip VCO features very low phase noise, and along with
extremely low jitter dividers and buffers, it is capable of 3G base station
applications, such as W-CDMA, CDMA2000, and TD-SCDMA. AD9516
provides multiple output logic, small footprint, and a feature-rich core in
a small 64-lead LFCSP package.
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Clock Generation, Synchronization, and Distribution:
Complete Timing Solution for Networking and
Communications Systems
The importance of clock management in networks is vital to
maintaining a high level of system reliability and stability. In
synchronous optical networks (SONET/SDH), the AD9549 clock
generator IC provides an output synchronized to one of two
reference inputs. A programmable digital loop filter capable of
bandwidths < 1 Hz enables the device to perform jitter cleanup, so
that the output, which is synchronized to the network reference,
meets demanding system jitter requirements. This output is
programmable over a wide tuning range of 8 kHz to 725 MHz.
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The AD9549 provides automatic reference switchover and extended
holdover so that an output will be maintained even if the primary
reference is lost. This holdover functionality improves stability, which
is key to minimizing network downtime.
The example shows a complete timing solution in which the AD9549
is paired with the AD9514 clock divider, which offers high integration
and easy pin-programmability with only 225 fs rms additive jitter and
superb output channel isolation.
DDS-Based Clocking
High speed, high performance digital-to-analog converters (DACs) require
clean, low jitter, low phase noise clocks, especially when the DAC is generating a high intermediate frequency, “IF,” output. Time jitter on the DAC
clock translates to noise in the output spectrum and can limit the overall
performance of the transmit path.
Fortunately, new low phase noise, direct digital synthesis (DDS) products
are now available to build flexible converter clocks. Combined with clock
distribution chips, a DDS-based clock gener­ator offers ultrafine frequency
resolution: a 32-bit DDS tuning word results in millihertz resolution on the
output clock. Frequency outputs up to 400 MHz are supported using new
1 GSPS DDS devices, such as the AD9910, which features a 14-bit DAC.
In this example, the DDS is followed by an AD9515, which generates
an LVPECL clock for the transmit DAC and an LVDS/CMOS clock for the
digital upconverter, DUC. More information on DDS-based clocking can
be found in application notes AN-823 and AN-837.
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Clock Generation, Cleanup, Synchronization, and Distribution
Part
Number
Number
of Inputs
Max
Clock
Input
(GHz)
AD9510
2
1.6
250
8
AD9511
2
1.6
250
5
AD9512
2
1.6
—
5
AD9513
1
1.6
—
3
AD9514
1
1.6
—
3
AD9515
1
1.6
—
2
AD9516-x
2
1.6, 2.95
250
14
1600 (LVPECL), 800
(LVDS), 250 (CMOS)
0.4 total
PLL/VCO
AD9517-x
2
1.6, 2.95
250
12
1600 (LVPECL), 800
(LVDS), 250 (CMOS)
0.4 total
PLL/VCO
AD9518-x
2
1.6, 2.95
250
6
1600 (LVPECL)
0.4 total
PLL/VCO
2.7
655
2
655 (CML),
655 (analog)
0.7 total
PLL core
750 (HSTL),
50 (CMOS)
1 total
Digital PLL
<0.1
—
On-chip terminations at both input pins
16-lead LFCSP
<0.1
—
On-chip terminations at both input pins
16-lead LFCSP
<0.1
—
On-chip terminations at both input pins
16-lead LFCSP
<0.1
—
On-chip terminations at both input pins
16-lead LFCSP
AD9540
Max PLL
Number
Reference
of
Input
Outputs
(MHz)
AD9549
2
—
750
2
ADCLK905
1
6
—
1
ADCLK907
2
6
—
2
ADCLK914
1
2.5
—
1
ADCLK925
1
6
—
2
Max Clock Output
(MHz)
1200 (LVPECL), 800
(LVDS), 250 (CMOS)
1200 (LVPECL), 800
(LVDS), 250 (CMOS)
1200 (LVPECL), 800
(LVDS), 250 (CMOS)
800 (LVDS),
250 (CMOS)
1600 (LVPECL), 800
(LVDS), 250 (CMOS)
1600 (LVPECL), 800
(LVDS), 250 (CMOS)
6000 (ECL, PECL,
LVPECL)
6000 (ECL, PECL,
LVPECL)
2500 (HVDS)
6000 (ECL, PECL,
LVPECL)
Wideband
Random Multiplier,
Jitter
Divider
(ps rms)
0.25
PLL core
additive
0.25
PLL core
additive
0.25
—
additive
0.3 additive
Divider
0.225
additive
0.225
additive
Divider
Divider
Package
(RoHS)
Additional Features
Two programmable delay lines, serial port
for control, excellent channel isolation
One programmable delay line, serial port
for control, excellent channel isolation
One programmable delay line,
serial port for control
Pin-programmable divides 1 to 32,
one programmable delay line
Pin-programmable divides 1 to 32,
one programmable delay line
Pin-programmable divides 1 to 32,
one programmable delay line
Four programmable delay lines,
A and B reference inputs,
serial port for control, low skew outputs
Four programmable delay lines,
A and B reference inputs,
serial port for control, low skew outputs
A and B reference inputs, serial port for control,
low skew outputs
48-bit frequency resolution, 14-bit phase
resolution, PLL/DDS for clock generation
A and B reference inputs, automatic reference
switching, frequency holdover, programmable
digital loop filter to <1 Hz
64-lead LFCSP
48-lead LFCSP
48-lead LFCSP
32-lead LFCSP
32-lead LFCSP
32-lead LFCSP
64-lead LFCSP
48-lead LFCSP
48-lead LFCSP
48-lead LFCSP
64-lead LFCSP
Programmable Delay Generator
Part Number
Voltage Supply (V) Max Input (MHz)
ADF4026
2.7 to 3.6
6000
Max Output
(MHz)
40
Number of
Outputs
4
Additive Jitter (ps rms)
Interface
Package
1
3-wire serial
24-lead LFCSP
Quad CMOS Timing Vernier
Part
Number
ADATE207
Edge
Refire
Rate (ns)
Input
Data Rate
(MHz)
2.5
100
Number of
Channels/
Edges Per
Channel
4/4
Output Resolution
Type
(ps)
LVCMOS
40
Peakto-Peak
DNL/INL
(ps)
300/300
Overall
Timing
Accuracy
(ps)
500
Average
Jitter
Power Per
(ps rms)
Edge (W)
20
1.5
Minimum
Drive Pulse
Width (ns)
Mux Mode
Supported
Package
1
Yes
256-lead BGA
Clock and Data Recovery/Retiming
Jitter
Generation
(rms/p-p)
0.003/0.026
max
0.003/0.026
max
0.002/0.037
max
0.003/0.026
max
0.003/0.026
max
0.003/0.026
max
0.003/0.026
max
Jitter
Transfer BW
(kHz)
Jitter
Tolerance1
(UI p-p)
Package
130 max
1.0 @ 250 kHz
32-lead LFCSP
130 max
1.0 @ 250 kHz
32-lead LFCSP
670 max
1.0 @ 1 MHz
32-lead LFCSP
130 max
0.75 @ 637
kHz
32-lead LFCSP
130 max
1.0 @ 250 kHz
32-lead LFCSP
130 max
1.0 @ 250 kHz
32-lead LFCSP
130 max
1.0 @ 250 kHz
32-lead LFCSP
6
0.002/0.037
670
1.0 @ 1 MHz
32-lead LFCSP
650
50
0.002/0.037
670
1.0 @ 1 MHz
32-lead LFCSP
540
6
0.003/0.09 max
880 max
1.0 @ 1 MHz
48-lead LFCSP
1200
6
0.002/0.33
2000
1.0 @ 1 MHz
56-lead LFCSP
375
375
750
10
50
10
0.004/0.032
0.004/0.032
0.004/0.032
1200
1200
1200
0.6 @ 10 MHz
0.6 @ 10 MHz
0.6 @ 10 MHz
24-lead LFCSP
24-lead LFCSP
49-ball CSPBGA
Part
Number
Data Rates Supported
Description
Power
(mW)
Sensitivity
(mV)
ADN2804
622 Mbps
Single rate PA and CDR
423
3.3
ADN2806
622 Mbps
Single rate CDR
359
50
ADN2812
12.3 Mbps to 2.7 Gbps
Continuous rate PA and CDR
750
6
ADN2813
10 Mbps to 1.25 Gbps
Continuous rate PA and CDR
450
3.3
ADN2814
10 Mbps to 675 Mbps
Continuous rate PA and CDR
435
3.3
ADN2815
10 Mbps to 1.25 Gbps
Continuous rate CDR
390
50
ADN2816
10 Mbps to 675 Mbps
Continuous rate CDR
366
50
ADN2817
10 Mbps to 2.7 Gbps
600
ADN2818
10 Mbps to 2.7 Gbps
ADN2819
10 Mbps to 2.7 Gbps
ADN2865
10 Mbps to 2.7 Gbps
ADN2926
ADN2927
ADN2928
9.9 Gbps to 11.3 Gbps
9.9 Gbps to 11.3 Gbps
9.9 Gbps to 11.3 Gbps
Continuous rate PA and CDR
with LVDS outputs
Continuous rate PA and CDR
with LVDS outputs
Multirate PA and CDR
Continuous rate CDR
with loop timed SERDES
Single 10G/PA and CDR
Single 10G/EQ and CDR
Dual 10G/PA, EQ, and CDR
Single RF PLLs for Clock/Timing Applications2
Part
Number
PLL Type
Min RF Input
(MHz)
Max RF Input
(MHz)
ADF4001
ADF4002
ADF4112
ADF4106
ADF4153
ADF4193
Int-N
Int-N
Int-N
Int-N
Frac-N
Frac-N
5
5
100
500
500
400
200
400
3000
6000
4000
3500
Normalized
Phase Noise
(dBc/Hz)
–214
–222
–215
–219
–213
–216
Current Typ
(mA)
Application Recommendations
Package
4.5
4.0
6.5
13
12
68
High speed clocking applications
High speed clocking applications
General-purpose operation
Best integer-N PLL phase noise
General-purpose fractional-N PLL
Ultrafast settling PLL
16-lead TSSOP/20-lead CSP
16-lead TSSOP/20-lead CSP
16-lead TSSOP/20-lead CSP
16-lead TSSOP/20-lead CSP
16-lead TSSOP/20-lead CSP
32-lead CSP
Single RF Synthesizers with VCO for Clock/Timing Applications2
Part
Number
PLL Type
Frequency Jitter Typ
Range (MHz) (deg rms)
Programmable
Power
Consumption (mA)
Output
Power
(dBm)
ADF4360-7
Int-N
350 to 1800
0.6
–89
20 to 40
–13 to –4
ADF4360-8
Int-N
65 to 400
0.2
–103
20 to 40
–13 to –4
AD809
Int-N
155.52
1.6
—
17
0.8 V p-p
Jitter tolerance measurements are equipment limited.
1
For a complete listing of ADI PLL products, please visit www.analog.com/pll.
2
Phase Noise @ 1 kHz Offset,
200 kHz Channel Spacing
(dBc/Hz)
Application
Recommendations
High frequency clock
generation/cleanup
High frequency clock
generation/cleanup
SONET/SDH/fiber systems
Package
24-lead CSP
24-lead CSP
24-lead CSP
Product Highlights
Clock Generator with Integrated VCO
AD9516
•Two reference inputs
•Programmable dividers, up to 1024
•Integer-N PLL frequency synthesizer
•Four adjustable delay lines
•Selectable VCO frequencies up
to 2.8 GHz
•Selectable LVPECL, LVDS/CMOS logic
•Space-saving, 64-lead LFCSP package
•14 outputs with total jitter
< 0.5 ps rms
•Channel-to-channel phase offset
1 GSPS Direct Digital Synthesizers (DDS)
AD9910, AD9912
•Integrated 14-bit DAC
•Outputs up to 400 MHz
•Up to 3.5 μHz frequency tuning resolution
•0.022° phase tuning resolution
•Reduced power consumption: <800 mW
•AD9910: 16-bit parallel port, 1024-element RAM
•AD9912: two SpurKiller channels, integrated comparator
Single, Low Cost Clocking PLL
ADF4002
• Up to 400 MHz bandwidth
• Programmable charge pump currents
• Ultralow phase noise
• 3-wire serial interface
• Analog and digital lock detect
• Hardware and software power-down mode
• Maximum PFD frequency:
200 MHz
• 20-lead CSP, 16-lead TSSOP
Network Clock Generator/Synchronizer
AD9549
•Dual, flexible reference inputs
•Automatic or manual holdover/switchover modes
•Digital PLL core
•Programmable loop bandwidth: <1 Hz
•Programmable output frequencies from 8 kHz to
750 MHz
•Differential HSTL clock output
•Space-saving, 64-lead LFCSP package
Rail-to-Rail Comparators
ADCMP600 to ADCMP609 Family
• Industry’s first LVDS comparator
• Power dissipation as low as 1 mW
• LVDS, CML, and TTL/CMOS
outputs
• Ideal for level translation and
clock/data distribution
• Fully specified rail-to-rail at
Vcc = 2.5 V to 5.5 V
• Tiny SC70 and LFCSP packages
• Input voltage range 0.5 V beyond
the rails
Continuous Rate CDR IC with Loop-Timed SERDES
ADN2865
• Optimized for PON ONT
• Serial data input:
10.0 Mbps to 2.7 Gbps
• Exceeds ITU-T jitter requirements in all categories
• Integrated limiting amp:
6 mV sensitivity
• Patented dual-loop clock recovery architecture
• Programmable LOS detect and slice level
• Low power: 1.0 W
Online Virtual Simulation, Evaluation, and Optimization Design Tools
ADIsimPLL™: PLL Synthesizer Circuit Design, Simulation, and Evaluation Tool
Analog Devices ADIsimPLL development tool continues to be the industry-standard in PLL circuit design and
evaluation software. Since its introduction in early 2002, the patented and award-winning ADIsimPLL has been
used by more than 15,000 RF design engineers worldwide. The tool is frequently utilized by design engineers
in selecting and optimizing
circuits for clock recovery and
clock cleanup applications. With
this tool, PLL circuits can be
quickly designed and optimized
for clocking applications, thereby
reducing design iterations and time
to market.
For a free download of the
complete software package, please
visit www.analog.com/adisimpll.
ADIsimCLK: Clock Circuit Simulation and Evaluation Tool
ADIsimCLK is the design tool developed specifically for Analog Devices’ range of ultralow jitter clock distribution
and clock generation products. Whether your application is in wireless infrastructure, instrumentation,
broadband, ATE, or other areas demanding subpicosecond jitter performance, ADIsimCLK will enable you to
rapidly develop your design, evaluate, and optimize performance.
Analog Devices, Inc.
Worldwide Headquarters
Analog Devices, Inc.
One Technology Way
P.O. Box 9106
Norwood, MA 02062-9106
U.S.A.
Tel: 781.329.4700
(800.262.5643,
U.S.A. only)
Fax: 781.461.3113
Analog Devices, Inc.
Europe Headquarters
Analog Devices, Inc.
Wilhelm-Wagenfeld-Str. 6
80807 Munich
Germany
Tel: 49.89.76903.0
Fax: 49.89.76903.157
Based on the highly successful ADIsimPLL tool,
ADIsimCLK models the ultralow jitter clock products
by using an extremely easy to use graphical user
interface (GUI). The ADIsimCLK wizard enables the
designer to observe detailed performance data for a
“simulated” clock distribution design within minutes.
Optimization of the clock circuit can be accomplished
in this interactive environment with spreadsheet-like
simplicity and interactivity. Contrary to traditional
methods where designing, building, and measuring
parameters take days, ADIsimCLK enables the user
to change the circuit design and observe immediate
performance changes.
Analog Devices, Inc.
Japan Headquarters
Analog Devices, KK
New Pier Takeshiba
South Tower Building
1-16-1 Kaigan, Minato-ku,
Tokyo, 105-6891
Japan
Tel: 813.5402.8200
Fax: 813.5402.1064
For a free download of the complete software
package, please visit www.analog.com/adisimclk.
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Southeast Asia
Headquarters
Analog Devices
22/F One Corporate Avenue
222 Hu Bin Road
Shanghai, 200021
China
Tel: 86.21.5150.3000
Fax: 86.21.5150.3222
©2007 Analog Devices, Inc. All rights reserved.
Trademarks and registered trademarks are the property
of their respective owners.
Printed in the U.S.A.
BR06072-.16-6/07(A)
www.analog.com/clock-timing