POWER ELECTRONICS
Laboratory Manual
Department of Electrical and Electronics Engineering
Gokaraju Rangaraju Institute of Engineering & Technology
BACHUPALLY, MIYAPUR, HYDERABAD-500072
1
POWER ELECTRONICS
LABORATORY
Name:______________________________
Roll No:_________________ Section:____
Branch:____
Academic year:___________
Gokaraju Rangaraju Institute of
Engineering & Technology
BACHUPALLY, MIYAPUR, HYDERABAD-500072
2
CONTENTS
Name of the experiment
PAGE NO
1) Generation of Cosine Waveform
4
2) Design of DC power supply circuit
7
3) Inverse Cosine control Scheme
10
SIMULATION CIRCUITS
4) 1-Phase Half Wave controlled converter with R-load
16
5) 1-Phase Half Wave controlled converter with RL-load
20
6) 1-Phase Full controlled converter with R-load
24
7) 1-Phase Full controlled converter with RL-load
28
8) 1-Phase semi converter with RL-load
33
9) 1-Phase AC Voltage controller with R-Load
37
10) 1-Phase AC voltage controller using RL-load
41
11) 1-Phase Cyclo converter using R-Load
45
12) 555- Timer Triggering circuit
49
HARDWARE DESIGN CIRCUITS USING THE TRIGGERING CIRCUITS
PROJECT WORK
13) AC voltage controller Using UJT triggering circuit
54
14) Semi converter using UJT triggering circuit
57
15) Full controlled converter Using UJT Triggering circuit
60
16) Basic Step Down chopper using 555 –Timer
63
17) Basic Step up chopper using 555-Timer
66
18) Semi Converter using Inverse Cosine Control scheme
69
19) Half wave controlled converter using Inverse Cosine control scheme
72
20) Full controlled converter using Inverse Cosine control scheme
75
3
EXPERIMENT-1
GENERATION OF COSINE WAVEFORM
AIM: To Generate cosine waveform
APPARATUS:
230V AC supply
230/8-0-8 Center tapped Transformer
10k resistor
0.22uF, 63V capacitor
47uF, 63V capacitor
GPCB
BURGER STICKS
CRO
CRO probes -2
CIRCUIT DIAGRAM:
4
THEORY:
Generation of the cosine wave form is required for the inverse cosine control scheme. Usually adopted in line
commutated thyristor control circuits.
WAVEFORMS:
5
Waveforms:
Result:
6
EXPERIMENT-2
DESIGN OF DC-POWER SUPPLY
AIM: Design of DC- power supply circuit
APPARATUS:
PCB
Center tapped transformer 230/15-0-15
230V AC power supply
7812, 7912 voltage regulators
1N4007 Diodes
1000uF, 35V capacitors
2
220uF, 35V capacitors
2
0.1uf capacitors
4
CRO
CRO probes
JUMPERS
CIRCUIT DIAGRAM:
7
THEORY:
The circuit Diagram for generation of 12V DC power supply is shown. It consists of AC
supply, center tapped transformer, diode bridge rectifier, voltage regulators, capacitors.
230V, 50Hz AC supply is given to primary side of center tapped transformer. This voltage is stepped
down to a voltage of 15VAC, 50Hz which is available at the secondary side of the transformer. This
15VAC voltage is converted to DC voltage by using a diode bridge rectifier as shown. The capacitors
are used to eliminate the filters and Harmonics. The output voltage (15V) of bridge rectifier is
regulated to 12DC by using voltage regulators 7812 and 7912.
We can observe the +12V DC at the output terminal of regulator 7812 and -12V DC at the output
terminal of regulator 7912.
WAVEFORMS:
8
Waveforms:
Result:
9
EXPERIMENT-3
INVERSE COSINE CONTROL SCHEME
AIM: Design of Firing Circuit to Trigger a Thyristor using Inverse cosine method
APPARATUS:
Transformers
230/12-0-12
2
CRO probes, CRO
Connecting wires, multimeter
Soldering Rod, lead
Resistors:
2.2k
4
0.5w
10k
4
0.5w
47k
4
0.5w
4.7k
3
820k
2
27k
2
22k
4
3.3 ohms
2
220 ohms
2
1k
6
100 ohms
4
10K
1
0.022pf
2
0.1uf
2
47uf
2
1N4148
14
Z10
2
LM741
2
Potentiometer
1w
Capacitors:
DIODES:
IC’S
10
LM339
1
LM555N
2
2222A
2
2218
2
Transistors:
Pulse Transformer
1:1:1
2
16 pin
1
8 pin
4
IC bases:
Burg sticks
4 strips
11
CIRCUIT DIAGRAM:
12
THEORY:
The circuit diagram of firing pulse generation is as shown in above figure. Firing
pulses are generated by using inverse cosine control scheme. Cosine wave is given as
input to this firing circuit .This is compared with the DC voltage to generate firing
pulses. The pulses in the positive half cycle are generated by comparing the Inverse
cosine wave with the DC voltage and pulses in the negative half cycle are generated by
comparing the cosine wave with the DC voltage. By varying the DC voltage value
from +12v to -12v the firing angle is varied accordingly. These pulses are given as
triggering pulses to the Thyristors.
WAVEFORMS:
Case1: Firing angle (α) <
Case2: Firing angle (α) =
13
Case3: Firing angle (α) >
14
Waveforms:
Result:
15
Experiment No 4
1-PHASE HALF WAVE CONTROLLED CONVERTER
WITH R-LOAD
Aim:
To study the performance of a single phase half wave controlled converter
with R-load.
Apparatus: 1. Power Electronics Trainer Kit
2. Firing Circuit
3. CRO
Circuit Diagram:
Theory:
In the period 0 < t π/ω; the SCR is forward biased. Then
current through the load and voltage drop across the load are zero, and all the
supply voltage appears between the anode and cathode of the SCR. Let the SCR be
triggered at an angle of α (0<α<π).Then the supply terminals are connected to the
load through the SCR and the current starts flowing through the load via SCR.
Therefore the supply appears across the load with a drop of R and the voltage drop
across the SCR is zero (SCR is assumed ideal).
In the period π<t<2π; the SCR is Reversed biased and the SCR cannot conduct. The
voltage drop across the load is zero and the total supply voltage appears the SCR.
Again during the third positive Half cycle supply is positive again SCR is forward
biased and if we give triggering SCR starts conducting and this cycle repeats.
16
Procedure:
1. Connect the circuit as shown in the circuit diagram.
2. Give the firing pulses accordingly at a suitable firing angle from the firing circuit.
3. Observe the load voltage on the CRO and note down the firing angle.
4. Draw the waveforms and calculate the Average and RMS value of output voltage.
Calculations:
17
WAVEFORMS:
18
Waveforms:
Result:
19
Experiment No 5
1-PHASE HALF WAVE CONTROLLED CONVERTER
WITH RL-LOAD
Aim: To study the performance of a single phase half wave controlled converter
with
RL-load.
Apparatus:
1. Power Electronics Trainer Kit
2. Firing Circuit
3. CRO
4. CRO probes
Circuit Diagram: Vs = 1-Phase 50Hz, 230V supply
Theory:
In the period 0 < t π/ω; the SCR is forward biased. Then current through the load
and voltage drop across the load are zero, and all the supply voltage appears
between the anode and cathode of the SCR. Let the SCR be triggered at an angle of
α (0<α<π/ω).Then the supply terminals are connected to the load through the SCR
and the current starts flowing through the load via SCR. Therefore the supply
appears across the load and the voltage drop across the SCR is zero (SCR is
assumed ideal).
In the period π/ω<t<2π/ω; the SCR is Reversed biased but due to the presence
20
of Inductor, energy is stored during the positive Half cycle and this stored energy is
supplied to the SCR to remain in conducting mode even if the supply is negative.
This amount of energy stored depends on the value of inductor. That is more the
value of inductor more is the energy stored and SCR will remain in conducting state
up to the angle β. The load current continues to flow until the energy stored in the
Inductor becomes zero.
After the current becomes zero SCR is reverse biased and load voltage is Zero
hence, total supply voltage appears across the SCR up to 2π.
Again during the third positive Half cycle supply is positive, SCR is forward biased
and if we give triggering SCR starts conducting and this cycle repeats.
Here β is called Extinction Angle.
Procedure:
1. Connect the circuit as shown in the circuit diagram.
2. Give the firing pulses accordingly at a suitable firing angle from the firing circuit.
3. Observe the load voltage on the CRO and note down the firing angle and Extinction
angle.
4. Draw the waveforms and calculate the Average and RMS value of output voltage.
Calculations:
21
WAVEFORMS:
22
Waveforms:
Result:
23
Experiment No 6
1-PHASE FULL CONTROLLED CONVERTER WITH RLOAD
Aim: To study the performance of a single phase Full wave controlled converter
with R-load.
Apparatus:
1. Power Electronics Trainer Kit
2. Firing Circuit
3. CRO
Circuit Diagram:
Theory:
In the period 0 < t π/ω; the SCRs T1 and T2 are forward
biased and the SCRs T3 and T4 are reverse biased. Then current through the load
and voltage drop across the load are zero. Let the SCRs T1 and T2 be triggered at
24
an angle of α (0<α<π/ω).Then the supply terminals are connected to the load
through the SCRs and the current starts flowing through the load via SCRs T1 and
T2. Therefore the supply voltage appears across the load with a drop of R and the
voltage drop across the SCRs is zero when they are conducting (SCR is assumed
ideal).
In the period (π/ω<t<2π/ω); the SCRs T1 and T2 are Reversed biased hence cannot
conduct and T3 and T4 are forward biased. When they are triggered at an angle of
(π+α)/ ω
[0< (π+α)/ ω <2π/ ω]. Then the supply terminals are connected to the load through
the SCRs and the current starts flowing through the load via SCRs T3 and T4.
Therefore the supply voltage appears across the load with a drop R and the voltage
drop across the SCRs is zero when they are conducting (SCR is assumed
ideal).These SCRs continue to conduct up to 2π/ ω.
Again during the third positive Half cycle supply is positive and SCRs T1 and T2
are forward biased, if we give triggering SCRs start conducting and this cycle
repeats.
Procedure:
1. Connect the circuit as shown in the circuit diagram.
2. Give the firing pulses accordingly at a suitable firing angle from the firing circuit.
3. Observe the load voltage on the CRO and note down the firing angle.
4. Draw the waveforms and calculate the Average and RMS value of output voltage.
Calculations:
25
WAVEFORMS:
26
Waveforms:
Result:
27
Experiment No 7
1-PHASE FULL CONTROLLED CONVERTER WITH RLLOAD
Aim:
with
To study the performance of a single phase Full wave controlled converter
RL-load.
Apparatus:
1. Power Electronics Trainer Kit
2. Firing Circuit
3. CRO
Circuit Diagram:
Theory:
In the period 0 < t π/ω; the SCRs T1 and T2 are forward
biased and the SCRs T3 and T4 are reverse biased. Then current through the load
and voltage drop across the load are zero. Let the SCRs T1 and T2 be triggered at
an angle of α (0<α<π/ω).Then the supply terminals are connected to the load
through the SCRs and the current starts flowing through the load via SCRs T1 and
T2. Therefore the supply voltage appears across the load and the voltage drop
28
across the SCRs is zero when they are conducting (SCR is assumed ideal).
In the period ( π/ω<t<2π/ω); the SCRs T1 and T2 are Reversed biased ;the SCRs
are Reversed biased, but due to the presence of Inductor, energy is stored during the
positive Half cycle and this stored energy is supplied to the SCRs to remain in
conducting mode even if the supply is negative.
This amount of energy stored depends on the value of inductor. That is, more the
value of inductor more is the energy stored and SCRs will remain in conducting
state up to the angle β for Discontinuous conduction mode (β<π+α). T3 and T4 are
forward biased. When they are triggered at an angle of (π+α)/ω [0< (π+α)/ω <2π/ω].
Then the supply terminals are connected to the load through the SCRs and the
current starts flowing through the load via SCRs T3 and T4. Therefore the supply
voltage appears across the load and the voltage drop across the SCRs is zero when
they are conducting (SCR is assumed ideal).These SCRs continue to conduct up to
(π+β)/ ω.
Again during the third positive Half cycle supply is positive and SCRs T1 and T2
are forward biased, if we give triggering SCRs start conducting and this cycle
repeats.
For continuous conduction a high value of Inductor is chosen and before the load
current reaches zero value the next pair of Thyristors are triggered and hence the
current flows continuously ( β>π+α)
Procedure:
1. Connect the circuit as shown in the circuit diagram.
2. Give the firing pulses accordingly at a suitable firing angle from the firing circuit.
3. Observe the load voltage on the CRO and note down the firing angle and Extinction
angle.
4. Draw the waveforms and calculate the Average and RMS value of output voltage.
29
Calculations:
30
WAVEFORMS:
31
Waveforms:
Result:
32
Experiment No 8
1-PHASE SEMI CONVERTER WITH RL-LOAD
Aim: To study the performance of a single phase Semi converter with RL-load.
Apparatus: 1. Power Electronics Trainer Kit
2. Firing Circuit
3. CRO
Circuit Diagram:
Theory:
In the period 0 < t π/ω; the SCRs T1 and Diode D1 are forward biased and the
SCR T2 and Diode D2 are reverse biased. Then current through the load and
voltage drop across the load are zero. Let the SCR T1 be triggered at an angle of α
(0<α<π/ω).As the Diode D1 is already conducting the supply terminals are
connected to the load through the SCR and Diode, the current starts flowing
through the load via SCR T1 and Diode D1. Therefore the supply voltage appears
across the load, the voltage drop across the SCR and the Diode is zero when they
are conducting (SCR, Diode are assumed ideal).
Soon after π/ω load voltage tends to reverse, Free wheeling Diode gets forward
biased and starts conducting. The load, or output current is transferred from T1, D1
to FWD. As SCR T1 is reverse biased at t = π/ω+ current flows through FWD and
T1 is turned off. The load terminals are short circuited through FWD therefore load
voltage is zero during [π/ω<t< (π+α) /ω]. During the period (π/ω<t<2π/ω); T2 and
Diode D2 are forward biased. When T2 is triggered at an angle of (π+α) /ω, [0<
33
(π+α)/ω <2π/ω], then the FWD is reverse biased and is turned off. During this
period supply terminals are connected to the load through the SCR and the Diode
D2, the load current shifts from FWD to T2 and D2. Therefore the supply voltage
appears across the load. The voltage drop across the SCR and Diode is zero when
they are conducting (SCR, Diode are assumed ideal). SCR T2 and Diode D2
continue to conduct up to 2π/ ω. For the next half cycle the load current is
transferred from T2 and D2 to the FWD and SCR T1 and Diode D1 are forward
biased, if we give triggering SCR starts conducting and this cycle repeats.
Procedure:
1. Connect the circuit as shown in the circuit diagram.
2. Give the firing pulses accordingly at a suitable firing angle from the firing circuit.
3. Observe the load voltage on the CRO and note down the firing angle.
4. Draw the waveforms and calculate the Average and RMS value of output voltage.
Calculations:
34
WAVEFORMS:
35
Waveforms:
Result:
36
Experiment No 9
1-PHASE AC VOLTAGE CONTROLLER WITH R-LOAD
Aim:
To study the performance of a single phase AC Voltage controller with R-
load.
Apparatus: 1. Power Electronics Trainer Kit
2. Firing Circuit
3. CRO
Circuit Diagram:
Theory:
In the period 0 < t π/ω; The SCR T1 is forward biased and SCR T2 is reverse
biased. Let the T1 be triggered at an angle of α (0<α<π/ ω).Then the supply
terminals are connected to the load through T1 and the current starts flowing
through the load via SCR. Therefore the supply appears across the load. During the
period (π/ω<t<2π/ω) T1 is reverse biased and T2 is forward biased and when we
give trigger pulse at an angle of (π+α) /ω, [0< (π+α)/ω <2π/ω] T2 starts conducting
and the load terminals are connected to supply through T2 hence the output voltage
is the supply voltage from the instant of triggering. This repeats for the every half
cycle.
37
Procedure:
1. Connect the circuit as shown in the circuit diagram.
2. Give the firing pulses accordingly at a suitable firing angle from the firing circuit.
3. Observe the load voltage on the CRO and note down the firing angle.
4. Draw the waveforms and calculate the RMS value of output voltage.
Calculations:
38
WAVEFORMS:
39
Waveforms:
Result:
40
Experiment No 10
1-PHASE AC VOLTAGE CONTROLLER WITH RLLOAD
Aim:
To study the performance of a single phase AC Voltage controller with
RL-load.
Apparatus: 1. Power Electronics Trainer Kit
2. Firing Circuit
3. CRO
Circuit Diagram:
Theory:
In the period 0 < t π/ω; the SCRs T1 is forward biased and the SCR T2 is reverse
biased. Then current through the load and voltage drop across the load are zero. Let
the SCR T1 be triggered at an angle of α (0<α<π/ω).Then the supply terminals are
connected to the load through the SCR T1 and the current starts flowing through the
load via SCR T1. Therefore the supply voltage appears across the load and the
voltage drop across the SCRs is zero when they are conducting (SCR is assumed
ideal).
In the period ( π/ω<t<2π/ω); the SCR T1 is Reversed biased and T2 is forward
biased, but due to the presence of Inductor, energy is stored during the positive Half
cycle and this stored energy is supplied to the SCR to remain in conducting mode
even if the supply is negative.This amount of energy stored depends on the value of
inductor. That is, more the value of inductor more is the energy stored and SCR will
41
remain in conducting state up to the angle β for Discontinuous conduction mode
(β<π+α). T2 is forward biased. When it is triggered at an angle of (π+α)/ω [0<
(π+α)/ω <2π/ω]. Then the supply terminals are connected to the load through the
SCR T2 and the current starts flowing through the load via SCR T2. Therefore the
supply voltage appears across the load and the voltage drop across the SCRs is zero
when they are conducting (SCR is assumed ideal).This SCR will continue to
conduct up to (π+β)/ ω.
Again during the third positive Half cycle supply is positive and SCR T1 is forward
biased and T2 is reverse biased, if we give triggering the forward biased SCR, it
starts conducting and this cycle repeats.
For continuous conduction a high value of Inductor is chosen and before the load
current reaches zero value the next Thyristor is triggered and hence the current
flows continuously ( β>π+α)
Procedure:
1. Connect the circuit as shown in the circuit diagram.
2. Give the firing pulses accordingly at a suitable firing angle from the firing circuit.
3. Observe the load voltage on the CRO and note down the firing angle.
4. Draw the waveforms and calculate the RMS value of output voltage.
Calculations:
42
WAVEFORMS:
43
Waveforms:
Result:
44
Experiment No 11
1-PHASE STEP DOWN CYCLO CONVERTER WITH RLOAD
Aim: To study the performance of a single phase Cyclo converter with R-load.
Apparatus: 1. Power Electronics Trainer Kit
2. Firing Circuit
3. CRO
Circuit Diagram:
Theory:
Cyclo converter is a circuit which converts the input voltage at one frequency to the
output vtage at different frequecy.
During the positive half cycle Thyristors P1, N2 are forward biased and Thyristors
P2 and N1 are reverse biased. The circuit is designed for step down cyclo converter
for a output frequency of
=
.To get the desired frequency the Thyristors are
triggered accordingly.
During the first positive half cycle P1 and N2 are forward biased and to get the
positive output voltage, P1 is triggered at an angle of (π+α). During the next
positive half cycle P2 and N1 are forward biased, to get required output voltage
thyristor P2 is triggered. In the next half cycle P1 is triggered next N1,N2 and again
45
N1 are triggered accordingly. This process repeats.
Procedure:
1. Connect the circuit as shown in the circuit diagram.
2. Give the firing pulses accordingly at a suitable firing angle from the firing circuit.
3. Observe the load voltage on the CRO and note down the firing angle.
46
WAVEFORMS:
47
Waveforms:
Result:
48
Experiment No 12
555- TIMER TRIGGERING CIRCUIT
Aim: To generate pulses using 555 Timer Circuit
Apparatus: 1. Power Electronics Trainer Kit
2. Firing Circuit
3. CRO
Circuit Diagram:
Output
49
Theory:
The 555 has three main operating modes, Monostable, Astable, and Bistable. Each mode represents a
different type of circuit that has a particular output.
Astable mode :
An Astable Circuit has no stable state - hence the name "astable". The output continually switches
state between high and low without without any intervention from the user, called a 'square' wave.
This type of circuit could be used to give a mechanism intermittent motion by switching a motor on
and off at regular intervals. It can also be used to flash lamps and LEDs, and is useful as a 'clock'
pulse for other digital ICs and circuits.
Output Waveforms in Astable Mode:
Monostable mode
A Monostable Circuit produces one pulse of a set length in response to a trigger input such as a push
button. The output of the circuit stays in the low state until there is a trigger input, hence the name
"monostable" meaning "one stable state". his type of circuit is ideal for use in a "push to operate"
system for a model displayed at exhibitions. A visitor can push a button to start a model's mechanism
moving, and the mechanism will automatically switch off after a set time.
Output Waveforms in Monostable Mode:
50
Procedure:
1.
2.
3.
4.
Connect the firing circuit as shown in the circuit diagram
Simulate it using Multisim
Observe the pulses at the output
Vary the circuit parameters to observe the changes.
51
Waveforms:
Results:
52
HARDWARE CIRCUIT DESIGNS
53
Experiment No 13
AC VOLTAGE CONTROLLER USING UJT TRIGGERING
CIRCUIT
Aim:
Circuit Diagram:
54
55
56
Experiment No 14
SEMI CONVERTER USING UJT TRIGGERING
CIRCUIT
Aim:
Circuit Diagram:
57
58
59
Experiment No 15
FULL CONTROLLED CONVERTER USING UJT
TRIGGERING CIRCUIT
Aim:
Circuit Diagram:
60
61
62
Experiment No 16
BASIC STEP DOWN CHOPPER USING 555 –TIMER
Aim:
Circuit Diagram:
63
64
65
Experiment No 17
BASIC STEP UP CHOPPER USING 555-TIMER
Aim:
Circuit Diagram:
66
67
68
Experiment No 18
SEMI CONVERTER USING INVERSE COSINE
CONTROL SCHEME
Aim:
Circuit Diagram:
69
70
71
Experiment No 19
HALF WAVE CONTROLLED CONVERTER USING
INVERSE COSINE CONTROL SCHEME
Aim:
Circuit Diagram:
72
73
74
Experiment No 20
FULL CONTROLLED CONVERTER USING INVERSE
COSINE CONTROL SCHEME
Aim:
Circuit Diagram:
75
76
77
DATA SHEETS
 2N2222
 MUR 110
 1N4148
 IRFZ44
 LM 7815
 TL 494C
 LM339
 LM555
 TYN612
 TL3843
78
NPN switching transistors
2N2222; 2N2222A
FEATURES
PINNING
High current (max. 800 mA)
PIN
Low voltage (max. 40 V).
APPLICATIONS
DESCRIPTION
1
emitter
2
base
3
collector, connected to case
Linear amplification and switching.
DESCRIPTION
3
1
2
PNP complement: 2N2907A.
3
MAM264
1
Fig.1 Simplified outline (TO-18) and symbol.
QUICK REFERENCE DATA
SYMBOL
VCBO
VCEO
PARAMETER
collector-base voltage
CONDITIONS
MAX.
UNIT
open emitter
2N2222
60
V
2N2222A
75
V
2N2222
30
V
2N2222A
40
V
800
mA
500
mW
collector-emitter voltage
open base
IC
collector current (DC)
Ptot
total power dissipation
hFE
fT
DC current gain
IC = 10 mA; V CE = 10 V
transition frequency
IC = 20 mA; VCE = 20 V; f = 100 MHz
Tamb
25 C
2N2222
turn-off time
75
250
2N2222A
toff
MIN.
MHz
300
ICon = 150 mA; IBon = 15 mA; IBoff = 15 mA
MHz
250
ns
NPN switching transistors
2N2222; 2N2222A
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
VCBO
VCEO
VEBO
PARAMETER
collector-base voltage
CONDITIONS
MIN.
MAX.
UNIT
open emitter
2N2222
60
V
2N2222A
75
V
2N2222
30
V
2N2222A
40
V
2N2222
5
V
2N2222A
6
V
collector-emitter voltage
emitter-base voltage
open base
open collector
IC
collector current (DC)
800
mA
ICM
peak collector current
800
mA
IBM
peak base current
200
mA
Ptot
total power dissipation
25 C
500
mW
25 C
1.2
W
Tamb
Tcase
Tstg
storage temperature
Tj
junction temperature
Tamb
operating ambient temperature
65
65
+150
C
200
C
+150
C
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
Rth j-a
thermal resistance from junction to ambient
Rth j-c
thermal resistance from junction to case
CONDITIONS
in free air
VALUE
UNIT
350
K/W
146
K/W
NPN switching transistors
2N2222; 2N2222A
CHARACTERISTICS
Tj = 25 C unless otherwise specified.
SYMBOL
ICBO
PARAMETER
MIN.
IE = 0; VCB = 50 V
10
nA
IE = 0; VCB = 50 V; Tamb = 150 C
10
A
IE = 0; VCB = 60 V
10
nA
IE = 0; VCB = 60 V; Tamb = 150 C
10
A
10
nA
IEBO
emitter cut-off current
IC = 0; VEB = 3 V
hFE
DC current gain
IC = 0.1 mA; VCE = 10 V
35
IC = 1 mA; V CE = 10 V
50
IC = 10 mA; V CE = 10 V
75
IC = 150 mA; VCE = 1 V; note 1
50
IC = 150 mA; VCE = 10 V; note 1
100
hFE
DC current gain
hFE
DC current gain
30
2N2222A
40
collector-emitter saturation voltage
IC = 150 mA; IB = 15 mA; note 1
400
mV
IC = 500 mA; IB = 50 mA; note 1
1.6
V
IC = 150 mA; IB = 15 mA; note 1
300
mV
IC = 500 mA; IB = 50 mA; note 1
1
V
IC = 150 mA; IB = 15 mA; note 1
1.3
V
IC = 500 mA; IB = 50 mA; note 1
2.6
V
1.2
V
IC = 500 mA; IB = 50 mA; note 1
2
V
8
pF
25
pF
collector-emitter saturation voltage
2N2222A
base-emitter saturation voltage
2N2222
VBEsat
35
IC = 500 mA; VCE = 10 V; note 1
2N2222
2N2222
VBEsat
base-emitter saturation voltage
2N2222A
IC = 150 mA; IB = 15 mA; note 1
Cc
collector capacitance
IE = ie = 0; VCB = 10 V; f = 1 MHz
Ce
emitter capacitance
IC = ic = 0; VEB = 500 mV; f = 1 MHz
0.6
2N2222A
fT
F
300
IC = 10 mA; VCE = 10 V; Tamb = 55 C
2N2222A
VCEsat
UNIT
collector cut-off current
2N2222A
VCEsat
MAX.
collector cut-off current
2N2222
ICBO
CONDITIONS
transition frequency
IC = 20 mA; VCE = 20 V; f = 100 MHz
2N2222
250
MHz
2N2222A
300
MHz
noise figure
2N2222A
IC = 200 A; VCE = 5 V; RS = 2 k ;
f = 1 kHz; B = 200 Hz
4
dB
NPN switching transistors
SYMBOL
2N2222; 2N2222A
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
Switching times (between 10% and 90% levels); see Fig.2
ton
Td
turn-on time
35
ns
delay time
10
ns
Tr
rise time
25
ns
toff
turn-off time
250
ns
Ts
storage time
200
ns
Tf
fall time
60
ns
ICon = 150 mA; IBon = 15 mA; IBoff = 15 mA
Note
1. Pulse test: tp
300 s;
0.02.
VBB
RB
oscilloscope
VCC
RC
Vo
(probe)
450
(probe)
450
R2
Vi
DUT
R1
MLB826
Vi = 9.5 V; T = 500 s; tp = 10 s; tr = tf
R1 = 68 ; R2 = 325 ; RB = 325
; RC = 160 . VBB = 3.5 V; VCC = 29.5 V.
Oscilloscope input impedance Zi = 50
3 ns.
.
Fig.2 Test circuit for switching times.
oscilloscope
NPN switching transistors
2N2222; 2N2222A
PACKAGE OUTLINE
Metal-can cylindrical single-ended package; 3 leads
SOT18/13
seating plane
j
B
w
M
A
M
1
B
M
b
k
D1
2
3
a
A
D
A
0
5
L
10 mm
scale
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions)
UNIT
A
a
b
D
D1
j
k
L
w
mm
5.31
4.74
2.54
0.47
0.41
5.45
5.30
4.70
4.55
1.03
0.94
1.1
0.9
15.0
12.7
0.40
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT18/13
B11/C7 type 3
TO-18
EIAJ
45
EUROPEAN
PROJECTION
ISSUE DATE
97-04-18
MCC
MUR105
THRU
MUR1100
Features
High Surge Capability
Low Forward Voltage Drop
High Current Capability
Super Fast Switching Speed For High Efficiency
1 Amp Super Fast
Recovery Rectifier
50 to 1000 Volts
Maximum Ratings
Operating Temperature: -50 C to +150 C
Storage Temperature: -50 C to +150 C
MCC
Part Number
MUR105
MUR110
MUR115
MUR120
MUR140
MUR160
MUR180
MUR1100
Maximum
Recurrent
Peak Reverse
Voltage
50V
100V
150V
200V
400V
600V
800V
1000V
Maximum
RMS Voltage
35V
70V
105V
140V
280V
420V
560V
700V
DO-41
Maximum DC
Blocking
Voltage
50V
100V
150V
200V
400V
600V
800V
1000V
D
Electrical Characteristics @ 25 C Unless Otherwise Specified
Average Forward
1A
IF(AV)
Current
Peak Forward Surge
35A
IFSM
Current
Maximum
Instantaneous
Forward Voltage
MUR105-115
.975V
VF
MUR120-160
1.35V
MUR180-1100
1.75V
Max imum DC
5 A
Reverse Current At
IR
Rated DC Blocking
50 A
Voltage
Maximum Reverse
Recovery Time
MUR105-120
Trr
45ns
MUR140-160
60ns
MUR180-1100
75ns
Typical Junction
20pF
CJ
Capacitance
*Pulse Test: Pulse Width 300 sec, Duty Cycle
A
Cathode
Mark
TA = 55 C
B
8.3ms, half sine
D
C
IFM = 1.0A;
TA = 25 C
TA = 25 C
TA = 150 C
IF=0.5A, IR=1.0A,
Irr =0.25A
Measured at
1.0MHz, VR=4.0V
1%
DIMENSIONS
DIM
A
B
C
D
INCHES
MIN
.166
.080
.028
1.000
MAX
.205
.107
.034
---
MM
MIN
4.10
2.00
.70
25.40
MAX
5.20
2.70
.90
---
NOTE
MCC
MUR105 thru MUR1100
Figure 1
Typical Forward Characteristics
20
Figure 2
Forward Derating Curve
10
1.5
6
4
1.25
2
25 C
Amps
1.0
1
.6
.75
MUR180-1100
.4
Amps
MUR105-115
.5
.2
MUR120-160
Single Phase, Half Wave
60Hz Resistive or Inductive Load
.06
0
.04
25
50
75
100
125
150
175
C
.02
.01
.5
.7
.9
1.1
1.3
Average Forward Rectified Current - Amperes versus
Ambient Temperature - C
1.5
Volts
Instantaneous Forward Current - Amperes versus
Instantaneous Forward Voltage - Volts
Figure 3
Junction Capacitance
100
60
40
20
pF
TJ=25 C
10
6
4
2
1
.1
.2
.4
1
Volts
2
4
10
20
40
100 200
400
Junction Capacitance - pF versus
Reverse Voltage - Volts
www.mccsemi.com
1000
MCC
MUR105 thru MUR110
Figure 4
Typical Reverse Characteristics
Figure 5
Peak Forward Surge Current
100
60
60
40
50
TA =150 C
20
40
10
30
6
Amps
20
4
10
2 TA=100 C
0
Amps 1
1
4
2
6 8 10 20
40
60 80 100
.6
Cycles
.4
Peak Forward Surge Current - Amperes versus
Number Of Cycles At 60Hz - Cycles
.2
.1
TA 25 C
=
.06
.04
.02
.01
20
40
60
80
100
120
140
Volts
Instantaneous Reverse Leakage Current - MicroAmperes
versus
Figure 6
Reverse Recovery Time Characteristic And Test Circuit Diagram
50
10
trr
+0.5A
0
Pulse
Generator
Note 2
25Vdc
1
Notes:
1. Rise Time = 7ns max.
Input impedance = 1 megohm, 22pF
2. Rise Time = 10ns max.
Source impedance = 50 ohms
3. Resistors are non-inductive
Oscilloscope
Note 1
-0.25
-1.0
1cm
Set Time Base for 20/100ns/cm
www.mccsemi.com
High-speed diodes
1N4148; 1N4448
FEATURES
• Hermetically sealed leaded glass SOD27 (DO-35)
package
• H ig h switching speed: max. 4 ns
k
a
• General application
MAM246
• C ont i nu ou s reverse voltage: max. 100 V
• R e pe t it ive peak reverse voltage: max. 100 V
• R e pe t it i ve peak forward current: max. 450 mA.
The diodes are type branded.
Fig.1
APPLICATIONS
Simplified outline (SOD27; DO-35) and
symbol.
• High-speed switching.
DESCRIPTION
MARKING
The 1N4148 and 1N4448 are high-speed switching diodes
fabricated in planar technology, and encapsulated in
hermetically sealed leaded glass SOD27 (DO-35)
packages.
TYPE NUMBER
MARKING CODE
1N4148
1N4148PH or 4148PH
1N4448
1N4448
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
1N4148
1N4448
NAME
DESCRIPTION
VERSION
−
hermetically sealed glass package; axial leaded; 2 leads
SOD27
High-speed diodes
1N4148; 1N4448
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VRRM
VR
repetitive peak reverse voltage
−
100
V
continuous reverse voltage
−
100
V
IF
continuous forward current
−
200
mA
IFRM
repetitive peak forward current
−
450
mA
IFSM
non-repetitive peak forward current
−
4
A
−
1
A
−
0.5
A
see Fig.2; note 1
square wave; Tj = 25 °C prior to
surge; see Fig.4
t = 1 µs
t = 1 ms
t=1s
Ptot
total power dissipation
−
500
mW
Tstg
Tj
storage temperature
Tamb = 25 °C; note 1
−65
+200
°C
junction temperature
−
200
°C
Note
1. Device mounted on an FR4 printed-circuit board; lead length 10 mm.
ELECTRICAL CHARACTERISTICS
Tj = 25 °C unless otherwise specified.
SYMBOL
VF
IR
PARAMETER
forward voltage
CONDITIONS
MIN.
MAX.
UNIT
see Fig.3
1N4148
IF = 10 mA
−
1
1N4448
IF = 5 mA
0.62
0.72
V
V
IF = 100 mA
−
1
V
25
nA
reverse current
VR = 20 V; see Fig.5
VR = 20 V; Tj = 150 °C; see Fig.5
−
50
µA
IR
reverse current; 1N4448
VR = 20 V; Tj = 100 °C; see Fig.5
−
3
Cd
diode capacitance
f = 1 MHz; VR = 0 V; see Fig.6
−
4
µA
pF
Trr
reverse recovery time
when switched from IF = 10 mA to −
IR = 60 mA; RL = 100 Ω;
measured at IR = 1 mA; see Fig.7
4
ns
Vfr
forward recovery voltage
when switched from IF = 50 mA;
tr = 20 ns; see Fig.8
2.5
V
−
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
VALUE
UNIT
Rth(j-tp)
thermal resistance from junction to tie-point
lead length 10 mm
240
K/W
Rth(j-a)
thermal resistance from junction to ambient
lead length 10 mm; note 1
350
K/W
Note
1. Device mounted on a printed-circuit board without metallization pad.
High-speed diodes
1N4148; 1N4448
GRAPHICAL DATA
mbg451
300
MBG464
600
IF
(mA)
IF
(mA)
200
400
(1)
100
(2)
(3)
200
0
0
100
T amb (°C)
0
200
0
1
Device mounted on an FR4 printed-circuit board; lead length 10 mm.
(1)
°C;typical
typicalvalues.
values.
(2) T
T jj =
= 175
25 °C;
(3) T j = 25 °C; maximum values.
Fig.2
Fig.3
Maximum permissible continuous forward
current as a function of ambient
temperature.
2
VF (V)
Forward current as a function of forward
voltage.
MBG704
102
IFSM
(A)
10
1
10−1
1
10
102
103
tp (µs)
Based on square wave currents.
T j = 25 °C prior to surge.
Fig.4 Maximum permissible non-repetitive peak forward current as a function of pulse duration.
104
High-speed diodes
1N4148; 1N4448
mgd290
103
IR
(µA)
MGD004
1.2
Cd
(pF)
102
1.0
(1)
(2)
10
0.8
1
0.6
10−1
10−2
0.4
0
100
Tj (°C)
0
200
10
VR (V)
20
(1) VR = 75 V; typical values.
(2) VR = 20 V; typical values.
f = 1 MHz; T j = 25 °C.
Fig.5
Fig.6
Reverse current as a function of junction
temperature.
Diode capacitance as a function of reverse
voltage; typical values.
High-speed diodes
1N4148; 1N4448
tr
tp
t
D.U.T.
IF
R = 50 Ω
S
V = VR
10%
IF
SAMPLING
OSCILLOSCOPE
t rr
t
R = 50 Ω
i
IF x R S
(1)
90%
VR
MGA881
input signal
output signal
(1) IR = 1 mA.
Fig.7 Reverse recovery voltage test circuit and waveforms.
I
1 kΩ
450 Ω
I
V
90%
R = 50 Ω
S
OSCILLOSCOPE
D.U.T.
V fr
R i = 50 Ω
10%
MGA882
t
tr
t
tp
input
signal
Fig.8 Forward recovery voltage test circuit and waveforms.
output
signal
High-speed diodes
1N4148; 1N4448
PACKAGE OUTLINE
Hermetically sealed glass package; axial leaded; 2 leads
SOD27
(1)
b
D
L
G1
L
DIMENSIONS (mm are the original dimensions)
UNIT
b
max.
D
max.
G1
max.
L
min.
mm
0.56
1.85
4.25
25.4
0
1
2 mm
scale
Note
1. The marking band indicates the cathode.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOD27
A24
DO-35
SC-40
EUROPEAN
PROJECTION
ISSUE DATE
97-06-09
05-12-22
N-channel enhancement mode
TrenchMOSTM transistor
GENERAL DESCRIPTION
N-channel enhancement mode
standard level field-effect power
transistor in a plastic envelope using
’trench’ technology. The device
features very low on-state resistance
and has integral zener diodes giving
ESD protection up to 2kV. It is
intended for use in switched mode
power supplies and general purpose
switching applications.
PINNING - TO220AB
PIN
IRFZ44N
QUICK REFERENCE DATA
SYMBOL
PARAMETER
VDS
ID
Ptot
Tj
RDS(ON)
Drain-source voltage
Drain current (DC)
Total power dissipation
Junction temperature
Drain-source on-state
resistance
VGS = 10 V
PIN CONFIGURATION
MAX.
UNIT
55
49
110
175
22
V
A
W
˚C
m
SYMBOL
DESCRIPTION
d
tab
1
gate
2
drain
3
source
tab
g
drain
s
1 23
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDS
VDGR
VGS
ID
ID
IDM Ptot
Tstg, Tj
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Storage & operating temperature
RGS = 20 k
Tmb = 25 ˚C
Tmb = 100 ˚C
Tmb = 25 ˚C
Tmb = 25 ˚C
-
- 55
55
55
20
49
35
160
110
175
V
V
V
A
A
A
W
˚C
MIN.
MAX.
UNIT
-
2
kV
TYP.
MAX.
UNIT
-
1.4
K/W
60
-
K/W
ESD LIMITING VALUE
SYMBOL
PARAMETER
CONDITIONS
VC
Electrostatic discharge capacitor
voltage, all pins
Human body model
(100 pF, 1.5 k )
THERMAL RESISTANCES
SYMBOL
PARAMETER
CONDITIONS
Rth j-mb
Thermal resistance junction to
mounting base
Thermal resistance junction to
ambient
-
Rth j-a
in free air
N-channel enhancement mode
TrenchMOSTM transistor
IRFZ44N
STATIC CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
V(BR)DSS
VGS = 0 V; ID = 0.25 mA;
VGS(TO)
Drain-source breakdown
voltage
Gate threshold voltage
IDSS IGSS
Zero gate voltage drain current
V(BR)GSS
RDS(ON)
Gate source leakage current
Tj = -55˚C
VDS = VGS; ID = 1 mA
VDS = 55 V; VGS = 0 V;
VGS = 10 V; VDS = 0 V
Gate source breakdown voltage IG = 1 mA;
Drain-source on-state
VGS = 10 V; ID = 25 A
resistance
Tj = 175˚C
Tj = -55˚C
Tj = 175˚C
Tj = 175˚C
Tj = 175˚C
MIN.
TYP.
MAX.
UNIT
55
50
2.0
1.0
16
-
3.0
0.05
0.04
15
-
4.0
4.4
10
500
1
20
22
42
V
V
V
V
A
A
A
A
V
m
m
MIN.
TYP.
MAX.
UNIT
DYNAMIC CHARACTERISTICS
Tmb = 25˚C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
gfs
Forward transconductance
VDS = 25 V; ID = 25 A
6
-
-
S
Ciss
Coss
Crss
Input capacitance
Output capacitance
Feedback capacitance
VGS = 0 V; VDS = 25 V; f = 1 MHz
-
1350
330
155
1800
400
215
pF
pF
pF
Qg
Qgs
Qgd
Total gate charge
Gate-cource charge
Gate-drain (miller) charge
VDD = 44 V; ID = 50 A; VGS = 10 V
-
-
62
15
26
nC
nC
nC
td on
tr
td off
tf
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 30 V; ID = 25 A;
VGS = 10 V; RG = 10
Resistive load
-
18
50
40
30
26
75
50
40
ns
ns
ns
ns
Ld
Internal drain inductance
-
3.5
-
nH
Ld
Internal drain inductance
-
4.5
-
nH
Ls
Internal source inductance
Measured from contact screw on
tab to centre of die
Measured from drain lead 6 mm
from package to centre of die
Measured from source lead 6 mm
from package to source bond pad
-
7.5
-
nH
MIN.
TYP.
MAX.
UNIT
-
-
49
A
IF = 25 A; VGS = 0 V
IF = 40 A; VGS = 0 V
-
0.95
1.0
160
1.2
-
A
V
IF = 40 A; -dIF/dt = 100 A/ s;
VGS = -10 V; VR = 30 V
-
47
0.15
-
ns
C
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C unless otherwise specified
SYMBOL
PARAMETER
IDR
IDRM
VSD
Continuous reverse drain
current
Pulsed reverse drain current
Diode forward voltage
trr
Qrr
Reverse recovery time
Reverse recovery charge
CONDITIONS
N-channel enhancement mode
TrenchMOSTM transistor
IRFZ44N
AVALANCHE LIMITING VALUE
SYMBOL
PARAMETER
CONDITIONS
W DSS
Drain-source non-repetitive
unclamped inductive turn-off
energy
ID = 45 A; VDD 25 V;
VGS = 10 V; RGS = 50 ; Tmb = 25 ˚C
120
Normalised Power Derating
PD%
110
MIN.
TYP.
MAX.
UNIT
-
-
110
mJ
1000
ID/A
100
90
tp =
RDS(ON) =VDS/ID
80
1 us
100
10us
70
60
100 us
50
DC
40
10
1 ms
30
20
10ms
100ms
10
0
0
20
40
60
80
100
Tmb / C
120
140
160
180
Normalised Current Derating
ID%
1
10
100
VDS/V
Fig.3. Safe operating area. Tmb = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
Fig.1. Normalised power dissipation.
PD% = 100 PD/PD 25 ˚C = f(Tmb)
120
1
10
Zth/(K/W)
110
100
1
90
0.5
80
0.2
70
60
0.1
50
0.1
0.05
PD
0.02
40
30
0.01
0
tp
D=
tp
T
t
T
20
10
0
0
20
40
60
80
100
Tmb / C
120
140
160
180
Fig.2. Normalised continuous drain current.
ID% = 100 ID/ID 25 ˚C = f(Tmb); conditions: VGS 10 V
0.001
1E-06
0.0001
0.01
t/s
1
Fig.4. Transient thermal impedance.
Zth j-mb = f(t); parameter D = t p/T
100
N-channel enhancement mode
TrenchMOSTM transistor
100
16
IRFZ44N
30
9
VGS/V =
ID/A
8.0
8.5
10
gfs/S
25
80
7.5
20
60
7.0
15
6.5
40
6.0
20
0
0
2
4
VDS/V
6
8
5.5
5
5.0
4.5
10 4.0
0
Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VGS
40
10
0
35
40
ID/A
60
80
100
Fig.8. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID); conditions: VDS = 25 V
RDS(ON)/mOhm
2.5
VGS/V =
20
BUK959-60
a
Rds(on) normlised to 25degC
6
2
30
6.5
7
1.5
25
8
9
20
10
1
15
10
0
10
20
30
40
ID/A
50
60
70
80
90
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(ID); parameter VGS
0.5
-100
-50
0
50
Tmb / degC
100
150
200
Fig.9. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 25 A; VGS = 10 V
100
5
BUK759-60
VGS(TO) / V
ID/A
max.
80
4
typ.
60
3
40
2
min.
1
20
Tj/C =
0
0
2
175
4
25
6
VGS/V
8
10
12
Fig.7. Typical transfer characteristics.
ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj
0
-100
-50
0
50
Tj / C
100
150
200
Fig.10. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
N-channel enhancement mode
TrenchMOSTM transistor
IRFZ44N
100
Sub-Threshold Conduction
1E-01
IF/A
80
1E-02
2%
1E-03
typ
60
98%
Tj/C =
175
25
40
1E-04
20
1E-05
0
1E-06
0
1
2
3
4
0
0.2
0.4
0.6
0.8
VSDS/V
5
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
1
1.2
1.4
Fig.14. Typical reverse diode current.
IF = f(VSDS ); conditions: VGS = 0 V; parameter Tj
2.5
120
WDSS%
110
100
2
Thousands pF
90
80
1.5
70
Ciss
60
50
1
40
30
20
.5
10
Coss
Crss
0
0.01
0.1
1
VDS/V
10
0
20
40
100
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
60
80
100
120
Tmb / C
140
160
180
Fig.15. Normalised avalanche energy rating.
W DSS% = f(Tmb); conditions: I D = 49 A
12
VGS/V
+
10
VDD
L
VDS = 14V
8
VDS
VDS = 4 4V
-
VGS
6
-ID/100
0
4
RGS
2
0
T.U.T.
0
10
20
QG/nC
30
40
R 01
shunt
50
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG); conditions: ID = 50 A; parameter VDS
Fig.16. Avalanche energy test circuit.
WDSS 0.5 LID2 BVDSS BVDSS VDD
N-channel enhancement mode
TrenchMOSTM transistor
+
RD
VDS
-
VGS
0
RG
T.U.T.
Fig.17. Switching test circuit.
IRFZ44N
VDD
N-channel enhancement mode
TrenchMOSTM transistor
IRFZ44N
MECHANICAL DATA
Dimensions in mm
4,5
max
Net Mass: 2 g
10,3
max
1,3
3,7
2,8
5,9
min
15,8
max
3,0 max
not tinned
3,0
13,5
min
1,3
max 1 2 3
(2x)
0,9 max (3x)
2,54 2,54
0,6
2,4
Fig.18. SOT78 (TO220AB); pin 2 connected to mounting base.
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Refer to mounting instructions for SOT78 (TO220) envelopes.
3. Epoxy meets UL94 V0 at 1/8".
LM78XX
Series Voltage Regulators
General Description
The LM78XX series of three terminal regulators is available
with several fixed output voltages making them useful in a
wide range of applications. One of these is local on card
regulation, eliminating the distribution problems associated
with single point regulation. The voltages available allow
these regulators to be used in logic systems, instrumentation, HiFi, and other solid state electronic equipment. Although designed primarily as fixed voltage regulators these
devices can be used with external components to obtain adjustable voltages and currents.
The LM78XX series is available in an aluminum TO-3 package which will allow over 1.0A load current if adequate heat
sinking is provided. Current limiting is included to limit the
peak output current to a safe value. Safe area protection for
the output transistor is provided to limit internal power dissipation. If internal power dissipation becomes too high for the
heat sinking provided, the thermal shutdown circuit takes
over preventing the IC from overheating.
Considerable effort was expanded to make the LM78XX series of regulators easy to use and minimize the number of
external components. It is not necessary to bypass the out-
put, although this does improve transient response. Input bypassing is needed only if the regulator is located far from the
filter capacitor of the power supply.
For output voltage other than 5V, 12V and 15V the LM117
series provides an output voltage range from 1.2V to 57V.
Features
n
n
n
n
n
n
Output current in excess of 1A
Internal thermal overload protection
No external components required
Output transistor safe area protection
Internal short circuit current limit
Available in the aluminum TO-3 package
Voltage Range
LM7805C
5V
LM7812C
12V
LM7815C
15V
Connection Diagrams
Metal Can Package
TO-3 (K) Aluminum
Plastic Package
TO-220 (T)
DS007746-3
DS007746-2
Bottom View
Order Number LM7805CK,
LM7812CK or LM7815CK
See NS Package Number KC02A
2000 National Semiconductor Corporation
DS007746
Top View
Order Number LM7805CT,
LM7812CT or LM7815CT
See NS Package Number T03B
www.national.com
LM78XX Series Voltage Regulators
May 2000
LM78XX
Schematic
DS007746-1
(Note 3)
LM78XX
Absolute Maximum Ratings
Maximum Junction Temperature
150˚C
150˚C
−65˚C to +150˚C
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
(K Package)
(T Package)
Storage Temperature Range
Input Voltage
Lead Temperature (Soldering, 10 sec.)
(VO = 5V, 12V and 15V)
35V
Internal Power Dissipation (Note 1)
Internally Limited
Operating Temperature Range (T A)
0˚C to +70˚C
Electrical Characteristics LM78XXC
0˚C
Symbol
VO
TJ
Output Voltage
5V
12V
Input Voltage (unless otherwise noted)
10V
19V
Parameter
Output Voltage
Conditions
Line Regulation
5
5.2
11.5
12
12.5
14.4
15
15.6
V
5.25
11.4
15.75
V
Tj = 25˚C
I O = 500
mA
(7
5 mA I O
+125˚C
25)
VIN
(7.5
VIN
(8
VIN
1.5A
10
IO
Tj
Tj = 25˚C, IO
IO
V IN
Tj
V IN
1A
VMAX
f = 120 Hz
Tj
100 kHz
62
IO
500 mA
62
Dropout Voltage
Tj = 25˚C, I OUT = 1A
Output Resistance
f = 1 kHz
VIN
30)
20)
20)
12)
VIN
VIN
30)
4
(17.5
(15
VIN
27)
VIN
30)
(18.5
VIN
30)
VIN
27)
(17.7
VIN
30)
50
V IN
22)
12
120
(20
mV
V
150
60
(16
mV
V
150
120
(14.6
V
150
120
mV
V
75
mV
V IN
26)
V
12
150
mV
25
60
75
mV
50
120
150
mV
8
8
8
mA
8.5
8.5
8.5
mA
0.5
0.5
0.5
mA
1.0
1.0
1.0
mA
20)
(14.8
VIN
25)
27)
(17.9
(14.5
VIN
30)
55
72
(17.5
54
55
V
1.0
75
80
VIN
30)
1.0
40
1A, Tj = 25˚C
VMAX
120
1.0
IO
or
Tj
VIN
+125˚C
(7
f
0˚C
V IN
(7.5
VMAX
T A =25˚C, 10 Hz
Ripple Rejection
+125˚C
1A
500 mA, 0˚C
14.5
(17.5
4
25
Tj = 25˚C
1A
5 mA
V MIN
VIN
VIN
27)
50
IO
1A, 0˚C
Change
V MIN
50
+125˚C
Tj
5 mA
Quiescent Current
IO
3
12.6 1 4.25
(14.5
50
(8
0˚C
V MIN
20)
Tj = 25˚C
1A
Tj = 25˚C
IO
VIN
+125˚C
Tj
250 mA
750 mA
RO
Max
(7.5
VIN
Output Noise
Voltage
Typ
4.75
0˚C
VN
Min
1A
VIN
IQ
Max
IO
IO
Quiescent Current
Typ
PD
VIN
Load Regulation
Min
4.8
VMAX
Units
Max
1A
V IN
23V
Typ
IO
15W, 5 mA
15V
Min
Tj = 25˚C, 5 mA
0˚C
IQ
230˚C
(Note 2)
VIN
VO
300˚C
TO-220 Package T
125˚C unless otherwise noted.
V MIN
VO
TO-3 Package K
VIN
30)
mA
V
90
µV
70
dB
54
dB
+125˚C
(8
VIN
18)
(15
VIN
25)
(18.5 VIN
28.5)
2.0
2.0
2.0
8
18
19
V
V
m
LM78XX
Electrical Characteristics LM78XXC
0˚C
Symbol
V IN
TJ
(Note 2) (Continued)
125˚C unless otherwise noted.
Output Voltage
5V
12V
Input Voltage (unless otherwise noted)
10V
19V
Parameter
Conditions
Min
Typ
Max
Min
Typ
15V
23V
Max
Min
Typ
Units
Max
Short-Circuit
Current
Tj = 25˚C
2.1
1.5
1.2
A
Peak Output
Current
Tj = 25˚C
2.4
2.4
2.4
A
Average TC of
VOUT
0˚C
0.6
1.5
1.8
mV/˚C
Tj
+125˚C, I O = 5 mA
Input Voltage
Required to
Maintain
Tj = 25˚C, IO
1A
7.5
14.6
17.7
V
Line Regulation
Note 1: Thermal resistance of the TO-3 package (K, KC) is typically 4˚C/W junction to case and 35˚C/W case to ambient. Thermal resistance of the TO-220 package
(T) is typically 4˚C/W junction to case and 50˚C/W case to ambient.
Note 2: All characteristics are measured with capacitor across the input of 0.22 µF, and a capacitor across the output of 0.1µF. All characteristics except noise voltage
and ripple rejection ratio are measured using pulse techniques (tw 10 ms, duty cycle 5%). Output voltage changes due to changes in internal temperature must
be taken into account separately.
Note 3: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. For guaranteed specifications and the test conditions, see Electrical Characteristics.
LM78XX
Typical Performance Characteristics
Maximum Average Power Dissipation
Maximum Average Power Dissipation
DS007746-5
DS007746-6
Output Voltage (Normalized to 1V at TJ = 25˚C)
Peak Output Current
DS007746-7
Ripple Rejection
DS007746-8
Ripple Rejection
DS007746-9
DS007746-10
LM78XX
Typical Performance Characteristics
(Continued)
Output Impedance
Dropout Voltage
DS007746-11
Dropout Characteristics
DS007746-12
Quiescent Current
DS007746-13
Quiescent Current
DS007746-15
DS007746-14
inches (millimeters) unless otherwise noted
Aluminum Metal Can Package (KC)
Order Number LM7805CK, LM7812CK or LM7815CK
NS Package Number KC02A
LM78XX
Physical Dimensions
LM78XX Series Voltage Regulators
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
TO-220 Package (T)
Order Number LM7805CT, LM7812CT or LM7815CT
NS Package Number T03B
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
National Semiconductor
Corporation
Americas
Tel: 1-800-272-9959
Fax: 1-800-737-7018
Email: support@nsc.com
www.national.com
National Semiconductor
Europe
Fax: +49 (0) 180-530 85 86
Email: europe.support@nsc.com
Deutsch Tel: +49 (0) 69 9508 6208
English Tel: +44 (0) 870 24 0 2171
Français Tel: +33 (0) 1 41 91 8790
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
National Semiconductor
Asia Pacific Customer
Response Group
Tel: 65-2544466
Fax: 65-2504466
Email: ap.support@nsc.com
National Semiconductor
Japan Ltd.
Tel: 81-3-5639-7560
Fax: 81-3-5639-7507
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
TL494
PULSE-WIDTHMODULATIONCONTROLCIRCUITS
SLVS074D – JANUARY 1983 – REVISED MAY 2002
D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
Complete PWM Power-Control Circuitry
Uncommitted Outputs for 200-mA Sink or
Source Current
1IN+
1IN–
FEEDBACK
DTC
CT
RT
GND
C1
Output Control Selects Single-Ended or
Push-Pull Operation
Internal Circuitry Prohibits Double Pulse at
Either Output
Variable Dead Time Provides Control Over
Total Range
Internal Regulator Provides a Stable 5-V
Reference Supply With 5% Tolerance
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
2IN+
2IN–
REF
OUTPUT CTRL
VCC
C2
E2
E1
Circuit Architecture Allows Easy
Synchronization
description
The TL494 incorporates all the functions required in the construction of a pulse-width-modulation (PWM) control
circuit on a single chip. Designed primarily for power-supply control, this device offers the flexibility to tailor the
power-supply control circuitry to a specific application.
The TL494 contains two error amplifiers, an on-chip adjustable oscillator, a dead-time control (DTC)
comparator, a pulse-steering control flip-flop, a 5-V, 5%-precision regulator, and output-control circuits.
The error amplifiers exhibit a common-mode voltage range from –0.3 V to VCC – 2 V. The dead-time control
comparator has a fixed offset that provides approximately 5% dead time. The on-chip oscillator can be bypassed
by terminating RT to the reference output and providing a sawtooth input to CT, or it can drive the common
circuits in synchronous multiple-rail power supplies.
The uncommitted output transistors provide either common-emitter or emitter-follower output capability. The
TL494 provides for push-pull or single-ended output operation, which can be selected through the
output-control function. The architecture of this device prohibits the possibility of either output being pulsed twice
during push-pull operation.
The TL494C is characterized for operation from 0C to 70C. The TL494I is characterized for operation from
–40C to 85C.
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
SMALL
OUTLINE
(D)
PLASTIC
DIP
(N)
SMALL
OUTLINE
(NS)
SHRINK
SMALL
OUTLINE
(DB)
THIN SHRINK
SMALL
OUTLINE
(PW)
0C to 70C
TL494CD
TL494CN
TL494CNS
TL494CDB
TL494CPW
–40C to 85C
TL494ID
TL494IN
—
—
—
The D, DB, NS, and PW packages are available taped and reeled. Add the suffix R to device type (e.g.,
TL494CDR).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conformto specifications per the terms of Texas Instruments
standard warranty.
Production processing does not necessarily include
testingof
all parameters.
POST OFFICE BOX 655303
 DALLAS, TEXAS 75265
1
TL494
PULSE-WIDTHMODULATIONCONTROLCIRCUITS
SLVS074D – JANUARY 1983 – REVISED MAY 2002
FUNCTION TABLE
INPUT TO
OUTPUT CTRL
OUTPUT FUNCTION
VI = GND
Single-ended or parallel output
VI = Vref
Normal push-pull operation
functional block diagram
OUTPUT CTRL
(see Function Table)
13
RT 6
CT 5
Oscillator
Q1
1D
DTC
4
Dead-Time Control
Comparator
 0.1 V
1IN+
1IN–
2
9
Q2 11
PWM
Comparator
10
+
16
2IN– 15
E1
C2
E2
Pulse-Steering
Flip-Flop
–
Error Amplifier 2
2IN+
C1
C1
Error Amplifier 1
1
8
12
VCC
+
Reference
Regulator
–
14 REF
7 GND
FEEDBACK
3
0.7 mA
testingof all parameters.
POST OFFICE BOX 655303
 DALLAS, TEXAS 75265
2
TL494
PULSE-WIDTHMODULATIONCONTROLCIRCUITS
SLVS074D – JANUARY 1983 – REVISED MAY 2002
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 V
Amplifier input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.3 V
Collector output voltage, VO
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 V
Collector output current, IO
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 mA
Package thermal impedance, JA (see Note 2 and 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . 108C/W
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65C to 150C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to the network ground terminal.
2. Maximum power dissipation is a function of TJ(max), JA, and TA. The maximum allowable power dissipation at any allowable
ambient temperature is PD = (TJ(max) – TA)/JA. Operating at the absolute maximum TJ of 150C can affect reliability.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions
VCC
VI
Supply voltage
VO
Collector output voltage
Amplifier input voltage
MIN
MAX
7
40
V
–0.3
VCC –2
40
V
Collector output current (each transistor)
200
Current into feedback terminal
fosc
Oscillator frequency
CT
Timing capacitor
RT
Timing resistor
TA
Operating free-air temperature
TL494C
TL494I
POST OFFICE BOX 655303
 DALLAS, TEXAS 75265
UNIT
V
mA
0.3
mA
1
300
kHz
0.47
10000
nF
1.8
500
k
0
70
–40
85
C
3
TL494
PULSE-WIDTHMODULATIONCONTROLCIRCUITS
SLVS074D – JANUARY 1983 – REVISED MAY 2002
electrical characteristics over recommended operating free-air temperature range, VCC = 15 V,
f = 10 kHz (unless otherwise noted)
reference section
TEST CONDITIONS †
PARAMETER
TL494C, TL494I
MIN
TYP‡
MAX
4.75
5
5.25
UNIT
Input regulation
IO = 1 mA
VCC = 7 V to 40 V
2
25
Output regulation
IO = 1 mA to 10 mA
1
15
mV
Output voltage change with temperature
TA = MIN to MAX
REF = 0 V
2
10
mV/V
Output voltage (REF)
Short-circuit output current§
25
V
mV
mA
† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡ All typical values, except for parameter changes with temperature, are at TA = 25C.
§ Duration of the short circuit should not exceed one second.
oscillator section, CT = 0.01 F, RT = 12 k (see Figure 1)
TEST CONDITIONS †
PARAMETER
TL494, TL494I
MIN
TYP‡
Frequency
Standard deviation of frequency¶
All values of VCC, CT, RT, and TA constant
Frequency change with voltage
VCC = 7 V to 40 V,
TA = MIN to MAX
Frequency change with temperature#
MAX
10
kHz
100
Hz/kHz
1
TA = 25C
UNIT
Hz/kHz
10
Hz/kHz
† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡ All typical values, except for parameter changes with temperature, are at TA = 25C.
¶ Standard deviation is a measure of the statistical distribution about the mean as derived from the formula:
N
X) 2
(xn
n 1
N
1
# Temperature coefficient of timing capacitor and timing resistor are not taken into account.
error-amplifier section (see Figure 2)
TL494, TL494I
PARAMETER
TEST CONDITIONS
Input offset current
VO (FEEDBACK) = 2.5 V
VO (FEEDBACK) = 2.5 V
Input bias current
VO (FEEDBACK) = 2.5 V
Input offset voltage
Common-mode input voltage range
VCC = 7 V to 40 V
Open-loop voltage amplification
VO = 3 V,
RL = 2 k,
VO = 0.5 V to 3.5 V,
Unity-gain bandwidth
Common-mode rejection ratio
VO = 40 V,
TA = 25C
VID = –15 mV to –5 V,
MIN
TYP‡
70
UNIT
2
10
mV
25
250
nA
0.2
1
A
–0.3 to
VCC–2
VO = 0.5 V to 3.5 V
RL = 2 k
MAX
V
95
dB
800
kHz
65
80
dB
V (FEEDBACK) = 0.7 V
0.3
0.7
mA
Output source current (FEEDBACK)
VID = 15 mV to 5 V,
V (FEEDBACK) = 3.5 V
‡ All typical values, except for parameter changes with temperature, are at TA = 25C.
–2
Output sink current (FEEDBACK)
POST OFFICE BOX 655303
 DALLAS, TEXAS 75265
mA
4
TL494
PULSE-WIDTHMODULATIONCONTROLCIRCUITS
SLVS074D – JANUARY 1983 – REVISED MAY 2002
electrical characteristics over recommended operating free-air temperature range, VCC = 15 V,
f = 10 kHz (unless otherwise noted)
output section
PARAMETER
TEST CONDITIONS
Collector off-state current
Emitter off-state current
Collector-emitter saturation voltage
Common emitter
Emitter follower
VCE = 40 V,
VCC = VC = 40 V,
VCC = 40 V
VE = 0,
VO(C1 or C2) = 15 V,
VI = Vref
IC = 200 mA
IE = –200 mA
MIN
TYP†
2
VE = 0
MAX
UNIT
100
A
–100
A
1.1
1.3
1.5
2.5
Output control input current
† All typical values except for temperature coefficient are at TA = 25C.
3.5
V
mA
dead-time control section (see Figure 1)
PARAMETER
MIN
TEST CONDITIONS
Input bias current (DEAD-TIME CTRL)
VI = 0 to 5.25 V
Maximum duty cycle, each output
VI (DEAD-TIME CTRL) = 0, CT = 0.01 F, RT = 12 k
Zero duty cycle
Input threshold voltage (DEAD-TIME CTRL)
TYP†
MAX
UNIT
–2
–10
A
45%
3
3.3
MIN
TYP†
MAX
4
4.5
0.3
0.7
MIN
TYP†
MAX
VCC = 15 V
6
10
VCC = 40 V
9
15
Maximum duty cycle
0
V
† All typical values except for temperature coefficient are at T = 25C.
A
PWM comparator section (see Figure 1)
PARAMETER
TEST CONDITIONS
Input threshold voltage (FEEDBACK)
Zero duty cycle
Input sink current (FEEDBACK)
V (FEEDBACK) = 0.7 V
UNIT
V
mA
† All typical values except for temperature coefficient are at TA = 25C.
total device
PARAMETER
Standby supply current
TEST CONDITIONS
RT = Vref,
All other inputs and outputs open
Average supply current
VI (DEAD-TIME CTRL) = 2 V,
† All typical values except for temperature coefficient are at TA = 25C.
See Figure 1
7.5
UNIT
mA
mA
switching characteristics, TA = 25C
PARAMETER
Rise time
Fall time
Rise time
Fall time
TEST CONDITIONS
Common-emitter configuration,
See Figure 3
Emitter-follower configuration,
See Figure 4
MIN
TYP†
MAX
UNIT
100
200
ns
25
100
ns
100
200
ns
40
100
ns
† All typical values except for temperature coefficient are at T = 25C.
A
POST OFFICE BOX 655303
 DALLAS, TEXAS 75265
5
TL494
PULSE-WIDTHMODULATIONCONTROLCIRCUITS
SLVS074D – JANUARY 1983 – REVISED MAY 2002
PARAMETER MEASUREMENT INFORMATION
VCC = 15 V
150 
2W
12
4
Test
Inputs
3
12 k
VCC
DTC
C1
FEEDBACK
E1
RT
C2
6
5
0.01 F
1
2
16
15

13
CT
E2
8
150 
2W
Output 1
9
11
Output 2
10
1IN+
1IN–
2IN+
Error
Amplifiers
2IN–
OUTPUT
CTRL
REF
14
GND
50 k
7
TEST CIRCUIT
VCC
Voltage
at C1
0V
VCC
Voltage
at C2
0V
Voltage
at CT
Threshold Voltage
DTC
0V
Threshold Voltage
FEEDBACK
0.7 V
Duty Cycle
MAX
0%
0%
VOLTAGE WAVEFORMS
Figure 1. Operational Test Circuit and Waveforms
POST OFFICE BOX 655303
 DALLAS, TEXAS 75265
6
TL494
PULSE-WIDTHMODULATIONCONTROLCIRCUITS
SLVS074D – JANUARY 1983 – REVISED MAY 2002
PARAMETER MEASUREMENT INFORMATION
Amplifier Under Test
+
VI
FEEDBACK
–
+
Vref
–
Other Amplifier
Figure 2. Amplifier Characteristics
15 V
68 
2W
Each Output
Circuit
tf
Output
tr
90%
90%
CL = 15 pF
(See Note A)
10%
10%
TEST CIRCUIT
OUTPUT VOLTAGE WAVEFORM
NOTE A: CL includes probe and jig capacitance.
Figure 3. Common-Emitter Configuration
15 V
Each Output
Circuit
Output
CL = 15 pF
(See Note A)
90%
90%
68 
2W
10%
10%
tr
TEST CIRCUIT
tf
OUTPUT VOLTAGE WAVEFORM
NOTE A: CL includes probe and jig capacitance.
Figure 4. Emitter-Follower Configuration
POST OFFICE BOX 655303
 DALLAS, TEXAS 75265
7
TL494
PULSE-WIDTHMODULATIONCONTROLCIRCUITS
SLVS074D – JANUARY 1983 – REVISED MAY 2002
f – Oscillator Frequency and Frequency Variation – Hz
TYPICAL CHARACTERISTICS
OSCILLATOR FREQUENCY AND
FREQUENCY VARIATION†
vs
TIMING RESISTANCE
100 k
VCC = 15 V
TA = 25C
40 k
–2%
0.001 F
–1%
10 k
0.01 F
0%
4k
0.1 F
1k
400
†
Df = 1%
100
CT = 1 F
40
10
1k
4k
10 k
40 k
100 k
400 k
1M
RT – Timing Resistance – 
† Frequency variation (f) is the change in oscillator frequency that occurs over the full temperature range.
Figure 5
AMPLIFIER VOLTAGE AMPLIFICATION
vs
FREQUENCY
A – Amplifier Voltage Amplification – dB
100
VCC = 15 V
VO = 3 V
TA = 25C
90
80
70
60
50
40
30
20
10
0
1
10
100
1k
10 k
100 k
1M
f – Frequency – Hz
Figure 6
POST OFFICE BOX 655303
 DALLAS, TEXAS 75265
8
POWER ELECTRONICS LAB MANUAL
GRIET/EEE
2011-2012
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POWER ELECTRONICS LAB MANUAL
GRIET/EEE
2011-2012
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POWER ELECTRONICS LAB MANUAL
GRIET/EEE
2011-2012
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POWER ELECTRONICS LAB MANUAL
GRIET/EEE
2011-2012
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POWER ELECTRONICS LAB MANUAL
GRIET/EEE
2011-2012
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POWER ELECTRONICS LAB MANUAL
GRIET/EEE
2011-2012
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POWER ELECTRONICS LAB MANUAL
GRIET/EEE
2011-2012
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POWER ELECTRONICS LAB MANUAL
GRIET/EEE
2011-2012
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POWER ELECTRONICS LAB MANUAL
GRIET/EEE
2011-2012
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POWER ELECTRONICS LAB MANUAL
GRIET/EEE
2011-2012
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POWER ELECTRONICS LAB MANUAL
GRIET/EEE
2011-2012
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POWER ELECTRONICS LAB MANUAL
GRIET/EEE
2011-2012
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