Digital Design:
An Embedded Systems
Approach Using VHDL
Chapter 8
I/O Interfacing
Portions of this work are from the book, Digital Design: An Embedded
Systems Approach Using VHDL, by Peter J. Ashenden, published by Morgan
Kaufmann Publishers, Copyright 2007 Elsevier Inc. All rights reserved.
VHDL
I/O Devices and Transducers
„
Transducers convert between real-world
effects and digital representation
„
Input transducers: sensors
„
„
Output transducers: actuators
„
„
May require analog-to-digital converter (ADC)
May require digital-to-analog converter (DAC)
Human-interface devices
„
„
Buttons, switches, knobs, keypads, mouse
Indicators, displays, speakers
Digital Design — Chapter 8 — I/O Interfacing
2
VHDL
Kaypads & Keyboards
„
Recall switches and debouncing
Keypad: array of push-button switches
+V
1
2
3
4
5
6
r1
r2
7
8
1
2
3
4
5
6
7
8
9
*
0
#
9
r3
input
register
*
0
#
r4
c1
outtput
regiister
„
c2
c3
Scan the matrix by driving each row low one at a time
and see if any of the column lines become low.
Digital Design — Chapter 8 — I/O Interfacing
3
VHDL
Knobs & Position Encoders
„
„
In analog circuits, use a variable
resistor
In digital
g
circuits,, could use
pushbuttons
„
„
„
E.g.,
g , volume up/down
p/
Not as easy to use as knobs or sliders
Can use a position encoder attached to
a knob
„
Recall Gray code encoder
Digital Design — Chapter 8 — I/O Interfacing
4
VHDL
Incremental Encoder
„
If absolute position is not important,
incremental encoder is simpler
A
B
counterclockwise
A
B
clockwise
AB
Digital Design — Chapter 8 — I/O Interfacing
5
VHDL
Analog Inputs
„
„
Physical effect produces an analog voltage or
currentt
Microphone
„
„
Accelerometer
„
„
In airbag controllers
Fluid-flow sensors
„
„
I phones,
In
h
cameras, voice
i recorders,
d
…
In industrial machines,
machines coffee machines,
machines …
Gas detectors
„
In safety equipment
Digital Design — Chapter 8 — I/O Interfacing
6
VHDL
Analog-to-Digital Converters
„
Basic element:
analog comparator
Flash ADC
„
„
Simple, fast, but
uses many
comparators
Resolution
„
Number of output
bits
Digital Design — Chapter 8 — I/O Interfacing
+
–
+
–
+
–
Enco
oder
„
Vin
Vf
+
–
+
–
7
VHDL
Successive Approximation ADC
(analog)
Vin
Vf
(analog)
SAR
start
SAR – successive approximation
pp
register
g
DAC
+
–
(analog)
clk
Dout
done
„
Initial approximation: 01111111
„
Comparator output gives d7
„
„
Next approximation: d70111111
„
„
1 if Vin is higher than 01111111,
01111111 0 otherwise
Comparator output gives d6
N
Next
approximation:
i
i
d7d6011111,
011111 etc
Digital Design — Chapter 8 — I/O Interfacing
8
VHDL
LED Indicators
„
Single LED shows 1-bit state
„
On/off, busy/ready, error/ok, …
+V
„
Brightness depends on
current
„
output
driver
„
Determined by resistor
I = ((+V – VLED – VOL) / R
Digital Design — Chapter 8 — I/O Interfacing
9
VHDL
7-Segment LED Displays
„
Each digit has common anodes or
common cathodes
„
Scan: turn on one digit at a time
+V
A3
a
b
c
d
e
f
g
dp
common
anode
A2
A1
A0
a
b
c
d
e
f
g
dp
Digital Design — Chapter 8 — I/O Interfacing
10
VHDL
Example: Multiplexed Display
„
Four BDC inputs, 10MHz clock
„
„
Turn on decimal point of leftmost digit only
50Hz scan cycle (200Hz scan clock)
library ieee;
use ieee.std_logic_1164.all, ieee.numeric_std.all;
entity display_mux is
port ( clk, reset : in
bcd0, bcd1,
bcd2 bcd3 : in
bcd2,
anode_n
: out
segment_n : out
end entity display_mux;
std_logic;
unsigned(3 downto 0);
std_logic_vector(3 downto 0);
std_logic_vector(7 downto 0) );
Digital Design — Chapter 8 — I/O Interfacing
11
VHDL
Example: Multiplexed Display
architecture rtl of display_mux is
constant clk_freq
: natural := 10000000;
constant scan_clk_freq : natural := 200;
constant clk_divisor
: natural := clk_freq
/ scan_clk_freq;
lk f
signal
signal
signal
i
l
signal
scan_clk
digit_sel
b d
bcd
segment
:
:
:
:
std_logic;
unsigned(1 downto 0);
unsigned(3
i
d(3 downto
d
t 0);
0)
std_logic_vector(7 downto 0);
begin
Digital Design — Chapter 8 — I/O Interfacing
12
VHDL
Example: Multiplexed Display
-- Divide master clock to get scan clock
scan_clk_gen
scan
clk gen : process (clk) is
variable count : natural range 0 to clk_divisor - 1;
begin
if rising_edge(clk) then
if reset = '1' then
count := 0;
scan_clk <= '0';
elsif count = clk_divisor
clk divisor - 1 then
count := 0;
scan_clk <= '1';
else
count := count + 1;
scan_clk <= '0';
end if;
end if;
end process scan_clk_gen;
Digital Design — Chapter 8 — I/O Interfacing
13
VHDL
Example: Multiplexed Display
-- increment digit counter once per scan clock cycle
digit_counter
digit
counter : process (clk) is
begin
if rising_edge(clk) then
if reset = '1' then
digit_sel <= "00";
elsif scan_clk = '1' then
digit_sel <= digit_sel + 1;
end if;
end if;
end process digit_counter;
Digital Design — Chapter 8 — I/O Interfacing
14
VHDL
Example: Multiplexed Display
-- multiplexer to select a BCD digit
with digit_sel
digit sel select
bcd <= bcd0 when "00",
bcd1 when "01",
bcd2 when "10",
bcd3 when others;
-- Selected Signal Assignments
-- activate selected digit's anode
with digit_sel select
anode_n <= "1110" when
"1101" when
"1011" when
h
"0111" when
"00",
"01",
"10"
"10",
others;
Digital Design — Chapter 8 — I/O Interfacing
15
VHDL
Example: Multiplexed Display
-- 7-segment decoder for selected digit
with bcd select
segment(6 downto 0) <= "0111111" when
"0000110" when
"1011011" when
"1001111" when
"1100110" when
"1101101" when
"1111101" when
"0000111" when
"1111111" when
"1101111" when
"1000000" when
"0000",
"0001",
"0010",
"0011",
"0100",
"0101",
"0110",
"0111",
"1000",
"1001",
others;
------------
0
1
2
3
4
5
6
7
8
9
"-"
-- decimal point is only active for digit 3
segment(7) <= '1' when digit_sel = "11" else '0';
-- segment outputs are negative logic
segment_n <= not segment;
-- Conditional Signal Assignment
end architecture rtl;
Digital Design — Chapter 8 — I/O Interfacing
16
VHDL
Liquid Crystal Displays (LCDs)
„
Advantages
„
„
„
„
Disadvantages
„
„
„
Low power
Readable in bright ambient light conditions
Custom segment
g
shapes
p
Require backlight for dark conditions
Not as robust as LEDs
LCD panels
„
„
„
Rectangular array of pixels
Can be used for alphanumeric/graphical display
Controlled byy a small microcontroller
Digital Design — Chapter 8 — I/O Interfacing
17
VHDL
Actuators & Valves
„
„
Actuators cause a mechanical effect
Solenoid: current in coil moves armature
„
„
Solenoid valve
„
„
Can attach rods, levers, etc
to translate the movement
Armature controls fluid
or gas valve
The magnetic field created
by the current pulls the
bar inward.
+V
Relayy
„
Armature controls
electrical contacts
output
driver
Digital Design — Chapter 8 — I/O Interfacing
18
VHDL
Motors
„
Can provide angular position or speed
Use gears, screws, etc to convert to linear
position or speed
„
„
Stepper motors
Rotate in discrete steps
„
N
S
S
N
S N
S N
N S
N
S
S
N
Digital Design — Chapter 8 — I/O Interfacing
N S
19
VHDL
Motors
„
Servo-motors
„
„
„
„
DC motor, speed
d controlled
ll d by
b varying the
h
drive voltage
Use feedback to control the speed or to
drive to a desired position
Requires a position sensor or tachometer
Servo-controller
„
„
A digital circuit or an embedded processor
Compensates for non-ideal mechanical
effects
Digital Design — Chapter 8 — I/O Interfacing
20
VHDL
Digital-to-Analog Converters
a(0)
a(1)
a(2)
Vf
R
„
R-string DAC
„
„
R
Voltage divider
and analog
multiplexer
li l
Requires 2n
precision
i i
resistors
R
R
R
Vout
R
R
R
Digital Design — Chapter 8 — I/O Interfacing
21
VHDL
Digital-to-Analog Converters
Vf
„
R-2R ladder DAC
„
„
Sums binaryweighted
currents
Requires 2n
matched
t h d
resistors
a(3)
a(2)
a(1)
a(0)
2R
2R
2R
2R
–
+
2R
Vout
R
R
R
2R
Digital Design — Chapter 8 — I/O Interfacing
22
VHDL
I/O Controllers
„
„
An embedded processor needs to
access inp
input/output
t/o tp t data
I/O controller
„
Circuit
Ci
i that
h connects I/O
/O device
d i to a
processor
„
„
„
„
Includes control circuits
Input registers: for reading data
Output registers: for writing data
I/O ports
„
Registers accessible to embedded software
Digital Design — Chapter 8 — I/O Interfacing
23
VHDL
Simple I/O Controller
„
Just contains input and/or output
registers
egiste s
„
Select among them using a port address
entity gumnut is
port ( clk_i
rst_i
...
port_cyc_o
port_stb_o
port_we_o
port_ack_i
p
port_adr_o
port_dat_o
port_dat_i
;
... );
end entity gumnut;
: in
: in
std_logic;
std_logic;
:
:
:
:
:
:
:
std_logic;
std_logic;
std_logic;
std_logic;
g ;
unsigned(7 downto 0);
std_logic_vector(7 downto 0);
std_logic_vector(7 downto 0);
out
out
out
in
out
out
in
Digital Design — Chapter 8 — I/O Interfacing
24
VHDL
Example: Keypad Controller
„
„
Output register for row drivers
Input register for column sensing
Gumnut
Keypad Controller
1 2 3
port_adr_o
port_dat_i
port_dat_o
dat_i
port_ack_i
port_cyc_o
cyc_i
port_we_o
we_i
keypad_col
port_stb_o
stb_i
dat_o
keypad_port_
yp
p
addr
=
keypad_row
4 5 6
7 8 9
* 0 #
ack_o
Digital Design — Chapter 8 — I/O Interfacing
25
VHDL
Example: Keypad Controller
library ieee; use ieee.std_logic_1164.all;
entity keypad
keypad_controller
controller is
port ( clk_i
: in std_logic;
cyc_i
: in std_logic;
stb_i
: in std_logic;
we i
we_i
: in std_logic;
std logic;
ack_o
: out std_logic;
dat_i
: in std_logic_vector(7
dat_o
: out std_logic_vector(7
keypad row : out std_logic_vector(3
keypad_row
std logic vector(3
keypad_col : in std_logic_vector(2
end entity keypad_controller;
downto
downto
downto
downto
0);
0);
0);
0) );
architecture rtl of keypad_controller is
signal col_synch : std_logic_vector(2 downto 0);
begin
...
Digital Design — Chapter 8 — I/O Interfacing
26
VHDL
Example: Keypad Controller
...
row_reg
row
reg : process (clk_i)
(clk i) is
-- Register to drive rows
begin
if rising_edge(clk_i) then
if cyc_i = '1' and stb_i = '1' and we_i = '1' then
keypad row <= dat_i(3
keypad_row
dat i(3 downto 0);
end if;
end if;
end process row_reg;
col_synchronizer
l
h
i
: process (clk_i)
( lk i) is
i
begin
if rising_edge(clk_i) then
dat_o <= "00000" & col_synch;
col_synch
l
h <= k
keypad_col;
d
l
end if;
end process col_synchronizer;
Remember that the keypad
signals are asynchronous and
need to be synchronized.
y
and stb_i;
;
ack_o <= cyc_i
end architecture rtl;
Digital Design — Chapter 8 — I/O Interfacing
27
VHDL
Control/Status Registers
„
Control register
„
„
„
Status register
„
„
„
Contains bits that govern operation of the
I/O device
Written by processor
Contains bits that reflect status of device
Read byy p
processor
Either or both may be needed in an
input or output controller
Digital Design — Chapter 8 — I/O Interfacing
28
VHDL
Example: ADC Controller
„
Successive approximation ADC
„
„
„
Control register
„
„
„
Selects reference voltage
Hold input voltage & start ADC
Status register
„
„
1 × analog input with sample/hold
4 × analog reference voltages
Is conversion done?
Input data register
„
Converted data
Digital Design — Chapter 8 — I/O Interfacing
29
VHDL
Example: ADC Controller
Vin
port_cyc_i
port_stb_i
Vf_0
Vf 1
Vf_1
port_ack_o
Vf_2
Vf_3
port_dat_i
port_cyc_i
port_stb_i
port_we_i
rst_i
clk_i
port_adr_i(0)
0
1
2
D0 Q0
D1 Q1
D2 Q2
CE
reset
clk
Y0
D0 Y1
D1 Y2
Y3
ADC
Vin Dout
Vf
start done
reset
clk
0
0
Digital Design — Chapter 8 — I/O Interfacing
7...1
1
port_dat_o
30
VHDL
Autonomous I/O Controllers
„
Independently sequence operation of a
device
„
„
„
„
Processor initiates actions
Controller notifies processor of events,
such as data availability, error condition, …
Processor can perform other operations
concurrently
Device operation not limited by
processor performance or load
Digital Design — Chapter 8 — I/O Interfacing
31
VHDL
Example: LCD Module
„
Rectangular array of pixels
„
„
„
Row and column connections
Controller scans rows, activates columns
Image or character data stored in a
small memoryy in the controller
„
Updated by an attached processor
Digital Design — Chapter 8 — I/O Interfacing
32
VHDL
Direct Memory Access (DMA)
„
For high-speed input or output
„
„
„
„
„
Processor writes starting address to a
control register
Controller transfers data to/from memory
autonomously
Notifies processor on completion/error
Reduces load on processor
Common with accelerators
Digital Design — Chapter 8 — I/O Interfacing
33
VHDL
Parallel Buses
„
Interconnect components in a system
„
„
Conceptual
p
structure
„
„
Transfer bits of data in parallel
All inputs and
output connected
In practice
„
Can t tie
Can’t
multiple outputs
together
data
source
data
source
Digital Design — Chapter 8 — I/O Interfacing
data
destination
data
destination
data
destination
34
VHDL
Multiplexed Buses
„
Use multiplexer(s)
to select among
data sources
„
data
source
data
source
0
1
data
source
Can partition
C
titi to
t
aid placement on chip
data
source
data
destination
data
source
data
source
1
1
1
0
0
0
data
destination
data
destination
data
destination
data
destination
data
d i i
destination
Digital Design — Chapter 8 — I/O Interfacing
35
VHDL
Example: Wishbone Bus
„
Non-proprietary bus spec
„
„
OpenCores Organization
Gumnut uses simple
p form of Wishbone
„
„
„
One bus for each of instruction memory,
data memory, and I/O ports
“…_o” denotes output
“…_i”
_ denotes input
p
Digital Design — Chapter 8 — I/O Interfacing
36
VHDL
Example: Wishbone Bus
Keypad Controller
=4
Gumnut
port_adr_o
dat_i
dat_o
cyc_i
ack_o
we_i
stb_i
ADC Controller
adr_i(0)
0
0
port_dat_i
port_dat_o
dat_i
dat_o
port_ack_i
port_cyc_o
cyc_i
ack_o
port_we_o
we_i
port_stb_o
stb_i
1
0
1
= 0...1
ADC Controller
adr_i(0)
0
0
dat i
dat_i
dat o
dat_o
cyc_i
ack_o
1
0
1
we_i
= 2...3
stb_i
Digital Design — Chapter 8 — I/O Interfacing
37
VHDL
Tristate Buses
„
Use tristate drivers for data sources
„
„
Can “turn-off”
ff (Hi-Z) when not supplying data
Simplified bus wiring
d(0)
bus(0)
en1
d(1)
bus(1)
en2
d(2)
toff
bus
…
…
…
d(n)
en
bus(2)
data 1
ton
data 2
bus(n)
Digital Design — Chapter 8 — I/O Interfacing
38
VHDL
Tristate Bus Issues
„
Floating bus can cause spurious switching
„
„
Use pull-up resistors or weak keepers
Need to avoid driver contention
„
„
Dead
D
d cycle
l between
b t
turn-off and turn-on
Or delayed enable
d
d_bus
weak
drive
en
„
Not all CAD tools and implementation
fabrics support tristate buses
Digital Design — Chapter 8 — I/O Interfacing
39
VHDL
Tristate Drivers in VHDL
„
„
Assign 'Z' to a signal to turn driver off
Example: single-bit driver
„
„
Example: multi-bit driver
„
„
d_out <= d_in when d_en = '1'
else 'Z';
b
bus_o
<= dat
d t when
h
d t
dat_en
= '1'
else "ZZZZZZZZ";
Any other driver contributing '0'
0 or '1'
1
overrides 'Z' value
„
Std logic signals are resolved
Std_logic
Digital Design — Chapter 8 — I/O Interfacing
40
VHDL
Altera I/O : ALT_IOBUF Primitive
The ALT_IOBUF primitive allows you to do the following:
„
„
„
„
„
„
„
„
Make a location assignment
Make an I/O standard assignment
M k a drive
Make
d i strength
t
th (current
(
t strength)
t
th) assignment
i
t
Make a slow slew rate assignment
Enable bus-hold circuitry
Enable a weak pull-up resistor
Make an on-chip termination (OCT) assignment to a
bidirectional p
pin from a lower-level entityy
This primitive is available for supported device (Cyclone III and
Stratix III) families.
Digital Design — Chapter 8 — I/O Interfacing
41
VHDL
Altera I/O : ALT_IOBUF Primitive
component alt_iobuf
generic(
i
io_standard
t d d
current_strength
slew_rate
slow_slew_rate
location
enable_bus_hold
weak_pull_up_resistor
termination
input_termination
output_termination
port(
g ;
i : in std_logic;
oe : in std_logic;
io : inout std_logic;
o : out std_logic);
end component;
:
:
:
:
:
:
:
:
:
:
string
ti
:= "NONE";
"NONE"
string := "NONE";
integer := -1;
string := "NONE";
string := "NONE";
string := "NONE";
string := "NONE";
string := "NONE";
string := "NONE";
string := "NONE" );
LIBRARY altera;
USE altera.altera_primitives_components.all;
lt
lt
i iti
t ll
Digital Design — Chapter 8 — I/O Interfacing
42
VHDL
Example: SN74x16541
library ieee; use ieee.std_logic_1164.all;
en1_1
en1_2
a1(0)
y1(0)
a1(1)
( )
y1(1)
( )
…
…
…
a1(7)
y1(7)
en2_1
en2
1
en2_2
a2(0)
y2(0)
a2(1)
y2(1)
…
…
…
a2(7)
y2(7)
entity
tit sn74x16541
74 16541 is
i
port
( en1_1, en1_2,
en2_1, en2_2 : in std_logic;
a1,
1 a2
2 : in
i
std_logic_vector(7
td l i
t (7 d
downto
t 0);
0)
y1, y2 : out std_logic_vector(7 downto 0) );
end entity sn74x16541;
architecture rtl of sn74x16541 is
begin
y1 <= a1 when en1_1 = '0' and en1_2 = '0' else
(others => 'Z');
Z );
y2 <= a2 when en2_1 = '0' and en2_2 = '0' else
(others => 'Z');
end architecture rtl;
Digital Design — Chapter 8 — I/O Interfacing
43
VHDL
Unknown Values in VHDL
„
What if two drivers are turned on?
„
„
„
„
One driving '0', the other driving '1'
Resolved value is 'X' — unknown
Can test for 'X' during simulation
'Z' a
and
d 'X' are
a e not
ot electrical
e ect ca logic
og c levels
e es
„
„
Notations for simulation and synthesis
Real logic levels are only 0 or 1
Digital Design — Chapter 8 — I/O Interfacing
44
VHDL
Open-Drain Buses
+V
CMOS
drain
gate
source
„
„
Bus is 0 if any driver pulls it low
If allll drivers
di
are off,
ff bus
b is
i pulled
ll d high
hi h
„
„
Wired-AND
Can also use
open-collector drivers
+V
collector
base
TTL
emitter
Digital Design — Chapter 8 — I/O Interfacing
45
VHDL
Open-Drain Drivers in VHDL
„
„
Assign '0' or 'Z' to model driver
M d l pull-up
Model
ll
using
i 'H'
„
„
„
Logic operations
„
„
bus_sig <= 'H';
Weak high
high, overriden by '0'
0
gated_sig <= bus_sig and sig_en;
Strip strength for comparisons
„
mux_out <=
a1 when To_X01(bus_sig)
To X01(bus sig) = '1' else
a0 when To_X01(bus_sig) = '0' else
"XXXXXXXX";
Digital Design — Chapter 8 — I/O Interfacing
46
VHDL
Bus Protocols
„
Specification of signals, timing, and
seq encing of b
sequencing
buss ope
operations
ations
„
„
„
Allows independent design of components
Ensures interoperability
Standard bus protocols
„
PCI VXI,
PCI,
VXI …
„
„
For connecting boards in a system
AMBA (ARM),
(ARM) CoreConnect (IBM),
(IBM)
Wishbone (Open Cores)
„
For connecting blocks within a chip
Digital Design — Chapter 8 — I/O Interfacing
47
VHDL
Example: Gumnut Wishbone
„
„
Minimal 8-bit subset used for I/O ports
Signals
„
„
„
„
„
„
„
port_cyc_o: “cycle” control for sequence of port
operations
port_stb_o: “strobe” control for an operation
port we o: write enable
port_we_o:
port_ack_i: acknowledge from addressed port
port_adr_o: 8-bit port address
port_dat_o: 8-bit data output from Gumnut
port_dat_i: 8-bit data input to Gumnut
Digital Design — Chapter 8 — I/O Interfacing
48
VHDL
Gumnut Wishbone Write
clk
port_adr_o
port_dat_o
port_cyc_o
port_stb_o
port_we_o
port_ack_i
No wait cycles
One wait cycle
Digital Design — Chapter 8 — I/O Interfacing
49
VHDL
Gumnut Wishbone Read
clk
port_adr_o
port_cyc_o
port_stb_o
port_we_o
port_dat_i
d i
port_ack_i
No wait cycles
One wait cycle
Digital Design — Chapter 8 — I/O Interfacing
50
VHDL
Serial Transmission
„
Bits transmitted one after another on a single
wire
„
„
Can afford to optimize the wire for speed
C.f. parallel transmission, one wire per bit
„
Requires more wires
„
„
Requires more pins
„
„
Cost of larger package
Other effects
„
„
Cost per wire, greater area for wiring, complexity of
place & route
C
Crosstalk,
t lk skew,
k
delay
d l due
d to
t increased
i
d area
Serializer/deserializer (serdes)
„
Converts between p
parallel and serial form
Digital Design — Chapter 8 — I/O Interfacing
51
VHDL
Example: 64-bit Serdes
tx_D
64-bit
shift reg
D in
D_in
D
Q0
load_en
CE
clk
+V
64-bit
shift reg
serial D
serial_D
receiver
control
start rx_ce
reset
clk rx_rdy
start
reset
clk
start
rx_ce
rx rdy
rx_rdy
D0
D1
D2
D3
D62 D63
Q
rx_D
CE
clk
rx_rdy
„
clk
serial_D
D_in
Bit o
order
de iis
arbitrary,
provided both
ends agree
„
Digital Design — Chapter 8 — I/O Interfacing
Often specified
p
by standards
52
VHDL
NRZ Transmission
„
Non-Return to Zero
„
„
„
Just set signal to high or low for each bit time
No indication of boundary between bit times
Need to synchronize transmitter and receiver
separately
„
E.g., by a common clock and control signals, as in
previous example
1 1 0 0 1 1 1 1
Digital Design — Chapter 8 — I/O Interfacing
53
VHDL
Start/Stop Bit Synchronization
„
„
Hold signal high when there is no data
To transmit
„
„
„
Drive signal
g
low for one bit time (start
(
bit))
Then drive successive data bits
Then drive signal high for one bit time
(stop bit)
1 1 1 0 0 1 0 0
Digital Design — Chapter 8 — I/O Interfacing
54
VHDL
UARTs
„
Universal Asynchronous
Receiver/Transmitter
„
„
Common I/O controller for serial
transmission using NRZ with start/stop bits
Relies on Tx and Rx clocks being
approximately
i
l the
h same frequency
f
Tx_clk
Tx_D
Rx clk
Rx_clk
Digital Design — Chapter 8 — I/O Interfacing
55
VHDL
Manchester Encoding
„
Combine Tx clock with Tx data
„
„
Ensures regular
l edges
d
in the
h seriall signall
Example: Manchester encoding
„
Transition in the middle of each bit time
„
„
„
0: low-to-high transition
1: high-to-low
high to low transition
May need a transition at the start of a bit time
1 1 1 0 0 1 0 0
Tx_clk
Tx D
Tx_D
Digital Design — Chapter 8 — I/O Interfacing
56
VHDL
Clock Recovery
„
Transmitter sends preamble before data
„
„
„
A sequence of encoded 1 bits
Serial signal then matches Tx clock
Receiver uses a phase-locked
phase locked loop (PLL) to
match Rx clock to Tx clock
idle
data word
Tx_clk
Tx D
Tx_D
Rx_clk
locked
Digital Design — Chapter 8 — I/O Interfacing
57
VHDL
Serial Interface Standards
„
„
„
Connection of I/O devices to computers
Connection of computers in networks
Use of standards reduces design effort
„
„
Reuse off-the-shelf components or IP
RS-232: NRZ,
NRZ start/stop bits
„
Originally for modems, now widely used for
low-bandwidth I/O
Digital Design — Chapter 8 — I/O Interfacing
58
VHDL
Serial Interface Standards
„
I2C: Inter-Integrated Circuit bus
„
„
„
USB: Universal Serial Bus
„
„
„
„
„
2 wires (NRZ data,
data clock),
clock) open drain
Simple protocol, low cost, 10kb/s–3.4Mb/s
For connecting I/O devices to computers
Differential signaling on 2 wires
1.5Mb/s, 12Mb/s, 480Mb/s, …, complex protocol
IP blocks available
FireWire: IEEE Std 1394
„
„
2 differential pairs (data, synch)
400Mb/s,
/ , 3.2Gb/s,
/ , complex
p
protocol
p
Digital Design — Chapter 8 — I/O Interfacing
59
VHDL
I2C Example: Temperature Sensor
„
Gumnut, Analog Devices AD7414
„
I2C controller IP from OpenCores respository
Gumnut
port_adr_o
port_dat_o
port_dat_i
port we o
port_we_o
port_stb_o
port_cyc_o
port_ack_i
int_req
int_ack
rst i
rst_i
clk_i
i2c_master_top
wb_adr_i
wb_dat_i
wb_dat_o
wb we i
wb_we_i
scl pad i
scl_pad_i
wb_stb_i
scl_pad_o
wb_cyc_i
scl_padoen_o
wb_ack_o
wb_inta_o
sda_pad_i
arst_i
sda_pad_o
wb rst i
wb_rst_i
sda padoen o
sda_padoen_o
wb_clk_i
+V
+V
AD7414
scl
sda alert
clk
rst
Digital Design — Chapter 8 — I/O Interfacing
60
VHDL
I/O Software
„
„
Use input and output instructions to
access I/O controller registers
I/O devices interact with the physical
p y
world
„
„
„
Software must respond
p
to events when
they occur
It must be able schedule activity at specific
times or at regular intervals
Real-time behavior
Digital Design — Chapter 8 — I/O Interfacing
61
VHDL
Polling
„
Software repeatedly reads I/O status to see if
an event has occurred
„
„
Multiple controllers
„
„
„
If so, it performs the required action
Software executes a polling loop, checking
controllers in turn
Advantage:
Ad
t
simple
i l I/O controllers
t ll
Disadvantages
„
„
Processor is continually busy,
busy consuming power
Delay in dealing with an event if processor is busy
with another event
Digital Design — Chapter 8 — I/O Interfacing
62
VHDL
Polling Example
„
Safety monitor in factory automation
„
„
Gumnut core
16 alarm inputs
„
„
„
Temp sensor ADC at address 20
„
„
„
One per
pe bit in registers
egiste s at addresses
add esses 16 & 17
0 ⇒ ok, 1 ⇒ abnormal condition
8-bit binary code for °C
Above 50°C is abnormal
Alarm output at address 40
„
0 ⇒ ok, 1 ⇒ ring alarm bell
Digital Design — Chapter 8 — I/O Interfacing
63
VHDL
Polling Example
alarm_in_1:
alarm_in_2:
temp_in:
alarm_out:
max_temp:
equ
equ
equ
equ
equ
16
17
20
40
50
poll loop:
poll_loop:
inp
sub
bnz
inp
sub
bnz
inp
sub
bnc
out
jmp
add
out
jmp
r1,
r1 alarm_in_1
alarm in 1
r0, r1, 0
set_alarm ; one or more alarm_in_1 bits set
r1, alarm_in_2
r0, r1, 0
set_alarm ; one or more alarm_in_2 bits set
r1, temp_in
r0, r1, max_temp
set
set_alarm
alarm ; temp_in
temp in > max_temp
max temp
r0, alarm_out ; clear alarm_out
poll_loop
r1, r0, 1
r1, alarm_out
alarm out ; set alarm
alarm_out
out bit 1 to 1
poll_loop
set_alarm:
;
;
;
;
;
address
address
address
address
maximum
of alarm_in_1 input register
of alarm_in_2 input register
of temp_in input register
of alarm_out output register
permissible temperature
Digital Design — Chapter 8 — I/O Interfacing
64
VHDL
Interrupts
„
I/O controller notifies processor when an
eventt occurs
„
„
Processor interrupts what it was doing
Executes interrupt service routine
„
„
„
„
A.k.a. interrupt handler
Then resumes interrupted
p
task
May enter low-power standby
Some systems prioritize interrupt requests
„
Allow higher priority events to interrupt service of
lower priority events
Digital Design — Chapter 8 — I/O Interfacing
65
VHDL
Interrupt Mechanisms
„
„
Interrupt request signal
Means of disabling/enabling interrupts
„
„
Save p
processor state on an interrupt
p
„
„
Until processor has saved state
Find the handler code for the event
„
„
So interrupted task can be resumed
On interrupt, disable further interrupts
„
„
So processor can execute critical regions
Vector: address of handler, or index into table of
handler addresses
Instruction to return from handler
„
Restoring saved state
Digital Design — Chapter 8 — I/O Interfacing
66
VHDL
Gumnut Interrupt Mechanisms
„
„
„
„
„
int_req signal
disi and enai instructions
On interrupt, PC, Z, and C saved in special
registers
i
On interrupt, further interrupts are disabled
Handler code starts at address 1
„
„
Gumnut sets PC to 1
reti
i instruction
i
i
„
Restores PC, Z, and C from special registers, reenables interrupts
Digital Design — Chapter 8 — I/O Interfacing
67
VHDL
Interrupt Acknowledgment
„
Process may not respond immediately
„
„
But must tell controller when it does
Controller then deactivates request
„
„
To avoid multiple interrupts for one event
Processor acknowledges
g the request
q
„
„
E.g., int_ack signal on Gumnut
Alternative: reading
g a status register
g
Digital Design — Chapter 8 — I/O Interfacing
68
VHDL
Example: Sensor Controller
„
8-bit input from sensor
„
Interrupt request on change of value
dat_o
sensor_in
int_ack
rst_i
clk_i
D
Q
reset
clk
D
Q
reset
clk
≠
D
Q
reset
clk
cyc_i
stb_i
int_req
ack o
ack_o
Digital Design — Chapter 8 — I/O Interfacing
69
VHDL
Example: Sensor Handler
saved_r1:
d 1
data
bss
b
1
sensor_data:
text
equ
0
org
stm
inp
...
ldm
reti
; address of sensor data
; input
p
register
g
1
r1, saved_r1
r1, sensor_data
; process the data
r1, saved_r1
Digital Design — Chapter 8 — I/O Interfacing
70
VHDL
Timers
„
Real-time clock (RTC)
„
„
„
„
Generates periodic interrupts
Uses a counter to divide system clock
Control register for divisor
Interrupt
te upt handler
a d e ca
can pe
perform
o
pe
periodic
od c
tasks
„
E.g., activate next digit of a scanned
display
Digital Design — Chapter 8 — I/O Interfacing
71
VHDL
Example: RTC for Gumnut
„
10µs timebase, divided by a down
counter
„
„
Initial count loaded from a register
Interrupt triggered on count value = 0
Offset
Output Registers
Input Registers
0
start_count
count_value
1
– – – – – – – E
0 0 0 0 0 0 0 I
Interrupt
Enable
Interrupt
Triggered
Digital Design — Chapter 8 — I/O Interfacing
72
VHDL
Real-Time Executives
„
Control program
„
„
„
A.k.a.
k real-time
l
operating system (RTOS)
( O )
Timing based on a real-time clock
S h d l execution
Schedules
ti off tasks
t k
„
„
In response to interrupts and timer events
Can also manage other resources
„
„
„
„
Memory allocation
Storage (file system)
Use of I/O controllers
Use of accellerators
Digital Design — Chapter 8 — I/O Interfacing
73
VHDL
Example: Gumnut Executive
„
„
RTC based at address 16
Calls task_2ms every 2ms
;;; --------------------------------------------------------;;; Program reset: jump to main program
text
org
jmp
0
main
;;; --------------------------------------------------------;;; Port addresses
rtc_start_count:
rtc_count_value:
rtc_int_enable:
rtc_int_status:
equ
equ
equ
equ
16
16
17
17
;
;
;
;
data output register
data input register
control output register
status input register
Digital Design — Chapter 8 — I/O Interfacing
74
VHDL
Example: Gumnut Executive
;;; --------------------------------------------------------;;; init_interrupts:
Initialize 2ms periodic interrupt, etc.
rtc_divisor:
data
equ
199
rtc int flag:
rtc_int_flag:
bss
1
text
add
out
add
out
stm
...
ret
r1, r0, rtc_divisor
r1, rtc
rtc_start_count
start count
r1, r0, 1
r1, rtc_int_enable
r0, rtc_int_flag
; other initializations
init_interrupts:
; divide 100kHz down
; to 500Hz
Digital Design — Chapter 8 — I/O Interfacing
75
VHDL
Example: Gumnut Executive
;;; --------------------------------------------------------;;; Interrupt handler
int_r1:
data
bss
text
t
t
org
int_handler:
check_rtc:
stm
inp
p
sub
bz
add
stm
check_next:
...
int end:
int_end:
ldm
reti
1 ; save location for
; handler registers
1
r1, int_r1
; save registers
r1,
, rtc_status ; check for
; RTC interrupt
r0, r1, 0
check_next
r1,
, r0,
, 1
r1, rtc_int_flag ; tell main
; program
r1
r1, int_r1
int r1 ; restore registers
Digital Design — Chapter 8 — I/O Interfacing
76
VHDL
Example: Gumnut Executive
;;; --------------------------------------------------------;;; main program
main:
main loop:
main_loop:
main_next:
„
text
jsb
enai
stby
ldm
sub
bnz
jsb
stm
...
jmp
init_interrupts
r1, rtc_int_flag
r0, r1, 1
main_next
task
task_2ms
2ms
r0, rtc_int_flag
main_loop
Note: task_2ms not called as part of interrupt
handler
„
W ld slow
Would
l
down
d
response to other
h interrupts
i
Digital Design — Chapter 8 — I/O Interfacing
77
VHDL
Summary
„
Transducers: sensors and actuators
„
„
„
Input and output devices
Controllers
„
„
„
Analog-to-digital
l
d
l and
d digital-to-analog
d
l
l
coverters
IInput,
t output,
t t control,
t l and
d status
t t registers
i t
Autonomous controllers
B
Buses:
multiplexed,
lti l
d tristate,
t i t t open-drain
d i
„
Bus protocols: signals, timing, operations
Digital Design — Chapter 8 — I/O Interfacing
78
VHDL
Summary
„
Serial transmission
„
„
Real-time software
„
„
„
NRZ, embedded clock
Reacting to I/O and timer events
Polling, interrupts
Real-time executives
Digital Design — Chapter 8 — I/O Interfacing
79