UJJWAL GUIN
371 Fairfield Way, Unit 4157, Storrs, CT 06269
SUMMARY
Experienced with expert understanding on Hardware Security, VLSI Testing & Reliability and Counterfeit IC Detection & Avoidance.
SKILLS
Languages: C/C++, Java, Perl, Verilog, VHDL, SPICE, and Matlab.
Tools: Netbeans, Design Compiler, TetraMAX ATPG, HSPICE, Xilinx ISE WebPack,
ModelSim, MATLAB & Simulink, and EClipse.
EXPERIENCE
Research Assistant
July 2011 - Present
Dept. of ECE, University of Connecticut, Storrs, CT
1. Working on developing approaches for securing intellectual properties (IPs) from piracy and
integrated circuits (ICs) from overproduction. Skills: Design Compiler, TetraMAX ATPG, and
Perl
2. Developed several light-weight on-chip structures for detecting recycled ICs. Proposed two algorithms for reducing the spread of process variation during the registration of new ICs. Skills:
HSPICE, Perl, and MATLAB
3. Worked in a group of developing a web-based tool (Assessment Framework) to assess the
detection capability of counterfeit detection methods. Skills: C/C++, Java, HTML, PHP, and
JavaScript
4. Worked on the assessment of counterfeit detection technologies. Proposed a systematic approach
of evaluating the detection capability of test methods. Skills: C/C++
5. Developed comprehensive taxonomies for counterfeit types, defects and detection methods.
6. Developed novel DFT structures for the initialization during functional testing (as a part of
functional fmax analysis). Proposed an algorithm to synthesize the minimum size decoder in my
proposed design. Skills: Design Compiler, TetraMAX ATPG, and Perl
Java Developer
November 2010 - June 2011
Prudent Infotech Inc, Plainsboro, NJ
(Contract Java developer, ACS: A Xerox Company, Nashville, TN)
1. Worked on @Vantage framework of ACS which provides a solution to put all relevant information
about a client and a case supported by Health and Human Services (HHS). Skills: Java, HTML,
and JavaScript
Research & Teaching Assistant
August 2008 August 2010
Dept. of ECE, Temple University, Philadelphia, PA.
1. Proposed a design for bit-error-rate estimation of high-speed serial links (SerDes). Skills: Matlab
2. Designed a novel Time-to-Digital converter. Skills: SPICE
3. Teaching, monitoring and troubleshooting all hardware and software issues for Embedded System,
Microprocessor System, and Digital Circuit Design Labs. Skills: Verilog, VHDL, and C
Assistant Manager
July 2004 July 2008
Plasma Display Panel (PDP) Unit, Samtel Color Limited, Ghaziabad, India.
1. Designed new cell structures to improve the efficiency of plasma display cells (Luminous Efficacy).
2. Timing generation to drive the PDP cell using Xilinx Spartan FPGAs. Skills: Verilog
3. Involved on Intellectual Property Rights (IPR) activities.
4. Worked as a member of process team for developing and stabilizing the manufacturing process.
PROFESSIONAL 1. Member of SAE G-19A Test Laboratory Standards Development Committee (AS6171: Test
ACTIVITIES
Methods Standard; Counterfeit Electronic Parts).
2. Reviewer of IEEE Transactions on VLSI Systems (TVLSI), ACM Transactions on Design Automation of Electronic Systems (TODAES), IET Computers & Digital Techniques, Journal of
Electronic Testing: Theory and Applications (JETTA), Environment Systems and Decisions
(ENVR), and IEEE International Test Conference (ITC).
3. Member of Publications of IEEE VLSI Test Symposium (VTS), 2011.
4. Graduate Student Member of IEEE.
5. Member of Electron Tubes and Display Devices LITD 04, Bureau of Indian Standards.
2007 - Sept 2007
PUBLICATIONS
Book
1. M. Tehranipoor, U. Guin, and D. Forte, Counterfeit Integrated Circuits: Detection and Avoidance, Springer, 2015.
Book Chapter
1. M. Tehranipoor, H. Salmani, and X. Zhang, Integrated Circuit Authentication: Hardware Trojans
and Counterfeit Detection, Springer, July 2013.
Journal Papers
1. U. Guin, D. Forte, and M. Tehranipoor, “Design of Accurate Low-Cost On-Chip Structures for
protecting Integrated Circuits against Recycling”, IEEE Transactions on VLSI Systems (TVLSI),
Minor Revisions.
2. U. Guin, K. Huang, D. DiMase, J. M. Carulli Jr., M. Tehranipoor, and Y. Makris, “Counterfeit
Integrated Circuits: A Rising Threat in the Global Semiconductor Supply Chain,” Proceedings
of the IEEE, 2014.
3. U. Guin, D. DiMase, and M. Tehranipoor, “Counterfeit Integrated Circuits: Detection, Avoidance, and the Challenges Ahead,” Journal of Electronic Testing: Theory and Applications
(JETTA), 2014.
4. U. Guin, D. DiMase, and M. Tehranipoor, “A Comprehensive Framework for Counterfeit Defect Coverage Analysis and Detection Assessment,” Journal of Electronic Testing: Theory and
Applications (JETTA), 2014.
Conference
Papers
1. U. Guin, X. Zhang, D. Forte, and M. Tehranipoor, “Low-Cost On-Chip Structures for Combating
Die and IC Recycling,” Design Automation Conference (DAC), 2014.
2. U. Guin, D. Forte, D. DiMase, and M. Tehranipoor, “Counterfeit IC Detection: Test Method
Selection Considering Test Time, Cost, and Tiel Level Risk,” GOMACTech, 2014.
3. U. Guin, D. Forte, and M. Tehranipoor, “Low-cost On-Chip Structures for Combating Die and
IC Recycling,” GOMACTech, 2014.
4. U. Guin, D. Forte, and M. Tehranipoor, “Anti-Counterfeit Techniques: From Design to Resign,”
IEEE Microprocessor Test and Verification (MTV), 2013.
5. U. Guin and M. Tehranipoor, “CDIR: Low-Cost Combating Die/IC Recycling Structures,”
DMSMS, 2013 (Extended Abstract).
6. U. Guin, T. Chakraborty, and M. Tehranipoor, “Functional Fmax Test-Time Reduction using
Novel DFTs for Circuit Initialization,” IEEE Int. Conference on Computer Design (ICCD), 2013.
7. U. Guin, T. Chakraborty, and M. Tehranipoor, “Novel DFTs for Circuit Initialization to Reduce
Functional Fmax Test Time,” IEEE North Atlantic Test Workshop (NATW), 2013.
8. U. Guin and M. Tehranipoor, “On Selection of Counterfeit IC Detection Methods,” IEEE North
Atlantic Test Workshop (NATW), 2013. Received Best Paper Award.
9. M. Tehranipoor and U. Guin, “Counterfeit Detection Technology Assessment,” GOMACTech,2013.
10. N. Murphy, U. Guin, and M. Tehranipoor, “Counterfeit Detection Technology Assessment,”
DMSMS & Standardization, 2012.
11. U. Guin and C. -H. Chiang, “Design for Bit Error Rate Estimation of High Speed Serial Links”,
IEEE VLSI Test Symposium (VTS), 2011.
Technical Reports 1. U. Guin, M. Tehranipoor, D. DiMase, and M. Megrdician, “Counterfeit IC Detection and Challenges Ahead,” ACM SIGDA, March 2013.
Thesis
1. U. Guin, “Design for Bit Error Rate Estimation of High Speed Serial Links”, Masters Thesis,
Temple University, PA, 2010.
PATENTS
1. “A PLASMA DISPLAY PANEL AND ITS MANUFACTURING THEREOF” filed at Indian
Patent Office, New Delhi on 10th March, 2008 with application no 598/DEL/2008.
2. “AN AC PDP WITH REDUCED ADDRESS VOLTAGE” filed at Indian Patent Office, New
Delhi on 8th November, 2007 with application no 2341/DEL/2007.
3. “A PLASMA DISPLAY PANEL WITH ENHANCED LUMINOUS EFFICACY” filed at Indian
Patent Office, New Delhi on 19th October, 2007 with application no 2188/DEL/2007.
4. “A PLASMA DISPLAY PANEL AND ITS MANUFACTURING THEREOF” filed at Indian
Patent Office, New Delhi on 6th August, 2007 with application no 1885/DEL/2007.
EDUCATION
Doctor of Philosophy (PhD)
University of Connecticut
Major: Electrical & Computer Engineering
Advisor: Dr. Mahammad Tehranipoor
GPA: 3.989/4.0
July 2011 - Present
Masters of Science (MS)
August 2008 - August 2010
Temple University, Philadelphia, PA
Major: Electrical & Computer Engineering
Advisor: Dr. Chen-Huan Chiang
Thesis Title: “Design for Bit Error Rate Estimation of High Speed Serial Links.”
GPA: 4.0/4.0
Bachelor of Engineering (BE)
Jul 2000 - May 2004
Bengal Engineering and Science University, India
Major: Electronics & Telecommunications Engineering
Thesis Title: “Study and Development of Ferrimagnetic Ferrite substrates core element to be used
as Microstrip radiator on a Laboratory scale at room temperature.”
Marks Obtained: 82/100.
GRADUATE
COURSES
Computer Architecture, Hardware Security and Trust, Advanced VLSI Design, VLSI Design Verif.
and Testing, Advance Microprocessor Systems, Nano Apps, Digital Signal Processing, Mixed Signal
VLSI Design, Adaptive Signal Processing, Appl Probability & Stochastic, Probability & Random
Processes and Engineering Analysis.
CONTACT
Email: ujjwal.guin@{uconn.edu, gmail.com}
INFORMATION Mobile: 615-516-6885
Work (Lab): 860-486-5274
Webpage: http : //www.engr.uconn.edu/ ∼ ujg11001/
Preferred