MVSG-­‐RF: Model Manual NEEDS Program Ujwal Radhakrishna Prof. Antoniadis Group MIT INTRODUCTION .................................................................................................................................................... 3 GAN HEMT: WORKING PRINCIPLE .................................................................................................................. 3 MVSG-­‐RF MODEL .................................................................................................................................................. 4 MVSG-­‐RF MODEL: VERILOG-­‐A IMPLEMENTATION .................................................................................... 5 1. TERMINAL VOLTAGE DEFINITION ......................................................................................................... 5 2. TEMPERATURE DEPENDENCE ................................................................................................................. 6 3. INTRINSIC TRANSISTOR DRAIN CURRENT FORMULATION ........................................................... 7 Saturation current ................................................................................................................................................................. 7 Non-­‐saturation current ....................................................................................................................................................... 8 GaN specific effects ................................................................................................................................................................ 8 4. SOURCE AND DRAIN IMPLICIT-­‐GATE TRANSISTOR DRAIN CURRENT FORMULATION ..... 10 Transition from non-­‐saturation to saturation current ...................................................................................... 12 5. INTRINSIC TRANSISTOR CHANNEL CHARGE FORMULATION .................................................... 16 Gate charge in Quasi-­‐ballistic regime ........................................................................................................................ 16 Gate charge in drift diffusion regime ......................................................................................................................... 17 Model for fringing field capacitances ........................................................................................................................ 19 MVSG-­‐RF MODEL: PARAMETER LIST .......................................................................................................... 21 PARAMETER EXTRACTION PROCEDURE FOR MVSG-­‐RF MODEL ....................................................... 22 DEVICE PARAMETERS ............................................................................................................................................................. 22 CG EXTRACTION ........................................................................................................................................................................ 23 EXTRACTION OF VTO, S AND DIBL (DELTA1) .................................................................................................................... 23 EXTRACTION OF VSATO/VXO, Β (BETA) AND 𝜽𝒗 (VTHETA), 𝜽𝝁 (MTHETA) AND RTH .................................................... 24 SPECTRE SIMULATION RESULTS .................................................................................................................. 25 REFERENCES ....................................................................................................................................................... 31 Introduction Compact models for Gallium Nitride (GaN) based high electron mobility transistors (HEMTs) are necessary for GaN-­‐circuit simulations. Several compact models of GaN HEMTs have been developed for this purpose [1]. In this work the compact model developed at MIT for these devices is discussed. Details of the Verilog-­‐A model equations along with parameter extraction procedure are explained. GaN HEMT: Working principle Gallium Nitride HEMT is an attractive candidate for HV and HF applications. This is due to superior and unique properties AlGaN/GaN system such as high electron density (~ 1×
10!" cm! ), high electron mobility in two dimensional electron gas (2DEG)(~ 1500 cm! /Vs), good thermal conductivity (~ 1.5 W/cm. K) and high breakdown field (~ 3.0 MV/cm) . These properties are compared with other materials and summarized in Fig.1. As can be seen, a combination of good transport properties and high breakdown field enables the GaN HEMT applications in the RF power domain. Fig.1: Table showing material properties. GaN shows a combination of high electron mobility, electron velocity and breakdown field [2] GaN-­‐based HEMTs, similar to other HEMTs, are field effect transistors having a hetero-­‐
junction formed between two materials (in this case AlGaN and GaN) with different lattice constants. A schematic of the device structure is shown in Fig. 2a. The difference in electron affinity (χ) and band gap (𝐸! ) results in the formation of a nearly triangular potential well at the interface on the GaN side where electrons can be confined and form a 2DEG as shown in Fig. 2b. However, the cause for the 2DEG is different from other HEMT devices. The polar nature of the AlGaN/GaN system results in spontaneous polarization and in addition, the difference in lattice constants of the two layers results in piezoelectric polarization. In GaN HEMTs, the 2DEG is not induced by doping but instead by donor-­‐like surface states on the AlGaN layer facilitated by spontaneous and piezoelectric electric field in AlGaN layer. Fig.2: (a) Device structure schematic. (b) Band diagram of heterostructure showing different types of charges Confinement of electrons in the quantum well and absence of dopants in the channel result in high mobility and peak velocity. Operation of the device requires a gate terminal to modulate the 2DEG and hence drain to source current (𝐼!" ). Since the 2DEG exists due to the heterostructure, a negative gate voltage is required to deplete it under the gate and prevent current flow. Therefore, GaN HEMTs without special gate stack engineering are normally-­‐on (depletion-­‐mode, D-­‐mode) devices. Further details on the working principle can be found in [2]. With this basic understanding of device operation, we can look at the approach taken by the MIT Virtual Source GaNFET (MVSG) –RF model to capture the device behavior under operating bias voltage. MVSG-­‐RF Model Typical device structure of GaN HEMT is shown in Fig. 3a. There are two distinct regions of the device, which require modeling attention. There is the intrinsic transistor region under the gate, where the 2DEG is modulated by the gate voltage (Vg) and there are regions next to the gate called the access regions (these devices are not self-­‐aligned). The access regions (between source-­‐gate and drain-­‐gate) are modeled as non-­‐linear implicit-­‐gate transistors. The MVSG model captures carrier transport in these different regions of the device with the help of sub-­‐circuit model shown in Fig. 3b. More details of the model equations can be found in [2]. In this manual, the implementation of the model equations in Verilog-­‐A code will be described in detail. Figure 3. (a) Cross-­‐sectional schematic of GaN HEMTs on SiC. (b) The equivalent circuit for the model with intrinsic transistor and implicit-­‐gate access region transistors is shown. MVSG-­‐RF Model: Verilog-­‐A implementation 1. Terminal voltage definition The following sections will describe the Verilog-­‐A code lines in the order they appear in the file ‘MVSG_RF_1_0_0.va’. First part of the Verilog-­‐A implementation of the MVSG-­‐RF model involves the definition of terminal voltages for each sub-­‐circuit element shown in Fig. 4. Figure 4. The equivalent circuit for the model showing all the intrinsic and extrinsic nodes along with intrinsic transistor, implicit-­‐gate access region transistors and contact resistance (Rc) is shown. The equivalent gate-­‐source and gate-­‐drain voltages of each transistor element should be defined in the Verilog-­‐A version of the model. Figure 4. shows the MVSG GaN HEMT schematic where external terminals are labeled as d (Drain), g (Gate) and s (Source) (There is no body terminal). Internal gate is same as the external one. Internal drain terminal of the intrinsic transistor is labeled as di, while internal source terminal is labeled as si. In addition, there are source and drain contact resistances which require additional intrinsic nodes: src and drc. src forms the intrinsic source node of source-­‐implict-­‐gate transistor and drc forms the intrinsic drain node of the drain-­‐implict-­‐gate transistor. Intrinsic transistor Conditional statements are put up to enable source-­‐drain symmetry in the intrinsic transistor. Even though the GaN HEMT is inherently an asymmetric device due to different source and drain access region lengths, ensuring source-­‐drain symmetry ensures that the code is robust around VDS=0 V. Vgs_raw = type * ( V(g)-­‐V(si) ); Vgd_raw = type * ( V(g)-­‐V(di) ); if ( Vgs_raw >= Vgd_raw ) begin // forward mode Vdsi = type * ( V(di)-­‐V(si) ); Vgsi = Vgs_raw; dir = 1; end else begin // reverse mode Vdsi = type * ( V(si)-­‐V(di) ); Vgsi = Vgd_raw; dir = -­‐1; end Source and drain implicit-­‐gate transistors The source and drain access regions do not have actual gate terminal. The implicit gate terminal (denoted by VIG in Fig. 4) is non-­‐existent and is only linked to the sheet resistance (Rsh) and carrier mobility (mu0) in these regions through an additional fitting parameter Cgrs (Cgrd). More details can be found in [2]. The terminal voltages for these implicit-­‐
transistors are defined in a way similar to that of the intrinsic transistor region as shown below: Source implicit-­‐gate transistor Vgsrs_raw = type * ( VtOrs + 1.0 / ( Rsh * Cgrs * mu0 ) -­‐ V(src) ); Vgdrs_raw = type * ( VtOrs + 1.0 / ( Rsh * Cgrs * mu0 ) -­‐ V(si) ); if ( type * ( V(si) -­‐ V(src) ) >= 0.0 ) begin // forward mode Vdsrsi = type * ( V(si)-­‐V(src) ); Vgsrsi = Vgsrs_raw; dirrs = 1; end else begin // reverse mode Vdsrsi = type * ( V(src)-­‐V(si) ); Vgsrsi = Vgdrs_raw; dirrs = -­‐1; end Drain implicit-­‐gate transistor Vgsrd_raw = type * ( VtOrd + 1.0 / ( Rsh * Cgrd * mu0 ) -­‐ V(di) ); Vgdrd_raw = type * ( VtOrd + 1.0 / ( Rsh * Cgrd * mu0 ) -­‐ V(drc) ); if ( type * ( V(drc) -­‐ V(di) ) >= 0.0 ) begin // forward mode Vdsrdi = type * ( V(drc)-­‐V(di) ); Vgsrdi = Vgsrd_raw; dirrd = 1; end else begin // reverse mode Vdsrdi = type * ( V(di)-­‐V(drc) ); Vgsrdi = Vgdrd_raw; dirrd = -­‐1; end 2. Temperature dependence GaN HEMTs have high power dissipation due to high current densities (few A/mm) and poor thermal conductivity. Therefore GaN compact models must incorporate temperature dependence on carrier transport parameters such as mobility and carrier velocity. In addition self-­‐heating is captured in the model by employing a thermal node (dt). Both change in temperature due to change of ambient temperature and due to device self-­‐
heating is included. The temperature dependence of mobility (mu0), velocity (vxo) and subthreshold slope (S) are captured by the following equations: TambK TnomK Tsh T Tfac Tfacrd Tfacrs Tvfac phit = $temperature; = Tnom + `P_CELSIUS0; = Temp(dt); = TambK + Tsh; = pow( T/TnomK , epsilon ); = Tfac; = Tfac; = ( 1.0 + vzeta * TnomK ) / ( 1.0 + vzeta * T ); = $vt(T); 3. Intrinsic transistor drain current formulation GaN HEMTs designed for high fT operation typically have very short gate lengths (Lg), in the order of tens of nm. At such short gate length it is observed that current in saturation has linear gate-­‐voltage dependence. Since mean free path in GaN is very short (~5 nm), transport cannot be fully ballistic even when Lg scales down to ~30 nm. Such scaled GaN HEMTs have a conduction band energy profile in the channel, at some large positive drain bias as shown in Fig. 5. The band peaks at a point close to the intrinsic source (at node si) (x=xo). This makes it possible to model the intrinsic transistor region as a quasi-­‐ballistic FET. The core-­‐transistor formalism can then be adopted from the MVS-­‐Si model [3]. Fig. 5: Conduction band profile in channel under gate for scaled GaN HEMTs Saturation current In the “charge-­‐sheet approximation,” the drain (channel) current normalized by width (ID/W) of a FET can be described by the product of the local charge areal density times the local carrier velocity anywhere in the channel. It is particularly useful to write this expression at the location of the VS point i.e., at the location of the top of the energy barrier (x = xo) point (node si) where the channel charge density Qixo, is easiest to model I! /𝑊 = 𝑄!"# 𝑣!" (1) In (1), 𝑣!" is the velocity at the virtual source. The virtual source velocity (vxo) described in [3] is a fixed bias-­‐independent parameter. However in GaN HEMTs, the velocity at the virtual source appears to show dependence on vertical field (or on Qixo) and on self-­‐heating. In the MVSG-­‐RF model, vxo is given by the bias independent velocity, called the injection velocity at the virtual source (𝑣!"# ), multiplied by functions that model these additional GaN-­‐specific effects. This is explained in detail in the next section. As in [3], the virtual-­‐
source charge density (Qixo) can be approximated quite closely by the empirical function in (2). This expression allows for a continuous expression for the GaN 2DEG charge density, analogous to the MOSFET inversion charge density, at the virtual source from weak to strong accumulation. 𝑄!"# = 𝐶! 𝑛 𝜑! 𝑙𝑛 1 + 𝑒𝑥𝑝
!!"# ! !! !!"! !!
! !!
(2) Cg is the effective gate-­‐to-­‐channel capacitance per unit area in strong accumulation (we borrow the term “accumulation” from MOSFETs to denote the state of the GaN channel charge density), 𝜑! is the thermal voltage, 𝑉!"# is the internal gate-­‐source voltage, corrected for the voltage drop on the source access region, n is the subthreshold coefficient, which is related to the subthreshold swing by S = n𝜑! ln 10, and 𝑉! is the threshold voltage corrected for drain-­‐induced barrier lowering, DIBL, a well-­‐known short channel effect. The term following VT in (2) allows for the requirement of different values of threshold voltage in strong and weak accumulation (a shift of VT by about α𝜑! =3.5𝜑! ). The function Ff is a Fermi function that allows for a smooth transition between the two values of VT and is centered at the point halfway between them [3]: !
𝐹! =
(3) !
! !! !!"! /!
!!!"# !"#
! !!
Non-­‐saturation current To account for the non-­‐saturation region, the velocity 𝑣!" in (1) is multiplied with the empirical saturation function Fsat, [3]. Fsat increases smoothly from 0, at VDSi= 0, to 1, at VDSi>> VDSAT, where VDSAT is the saturation voltage. Fsat is similar to the Caughey and Thomas [4] formulation for carrier velocity saturation. !!"#/ !!"#$
𝐹!"# =
; I! /𝑊 = 𝑄!"# 𝑣!" 𝐹!"# (4) ! !/!
!! !!"#/ !!"#$
While β is a fitting parameters, it has been found over many fits to experimental devices, from Si MOSFETs to GaN HEMTs that β=1.5-­‐1.8 provides excellent fit. Finally, to allow a smooth transition between the strong-­‐ and weak-­‐ accumulation values of the saturation voltage VDSAT, a generalized form of the saturation voltage is introduced by employing again Ff. ! !
𝑉!"#$ = 𝑉!"#$" (1 − 𝐹! ) + 𝜑! 𝐹! and 𝑉!"#$" = !"! ! (5) Here µμ is carrier mobility and 𝐿! is the gate length. Please note that Eqs. (3)-­‐ (5) are heuristic in nature, [3]. GaN specific effects In GaN HEMTs electron velocity decreases as charge density increases due to strong electron-­‐optical phonon interaction (scattering) and this is modeled empirically using Qixo. Including this and the temperature dependence due to self-­‐heating, 𝑣!" is modeled as [5]-­‐
[6] !!"#
𝑣!" =
1 − 𝜂! I! V! (6) !!"#
!!!!
!!"# where 𝑣!"# is the bias independent injection velocity at low channel charge. The term in the denominator accounts for carrier scattering and the last term in the numerator accounts for velocity reduction due to self-­‐heating. 𝜃! and 𝜂! are fitting parameters. Carrier mobility also decreases due to scattering and self-­‐heating and is modeled as [5]-­‐[6] !!
µμ =
(7) !! ! ! !
!
!!!! !"#
!!"# !!
! !
!!
Here 𝜃! , 𝜂! and 𝜀 are fitting parameters and 𝑇! is reference temperature. The detailed procedure for the extraction of these parameters is provided at the end of this manual. The following lines in the Verilog-­‐A file implement the core-­‐equations of the intrinsic transistor drain current described in this section. Electrostatic parameters of intrinsic transistor alpha_phit delta n VtOb FFs alpha_phit ) ) ); two_ns_phit = alpha * phit; = delta1 * Vdsi; = S / ( 2.3 * phit ) + nd * Vdsi; = VtO; = 1.0 / ( 1 + exp( ( Vgsi -­‐ ( VtOb -­‐ delta -­‐ alpha_phit / 2.0 ) ) / ( n * = 1.0 * n * phit; Source charge computation Qrefs = Cg * two_ns_phit; etas = ( Vgsi -­‐ ( VtOb -­‐ delta -­‐ 0.5 * alpha_phit * FFs ) ) / two_ns_phit; if ( etas <= `LARGE_VALUE ) begin Qinvs = Qrefs * ln( 1.0 + exp( etas ) ); end else begin Qinvs = Qrefs * ( etas ); end Qinv = Qinvs; GaN specific effects for mobility and velocity mu vx01 / Leff ); Non-­‐saturation formulation vx0 Vdsats Vdsats1 Vdsat Vdsat1 Vdsc Fsat beta ) ); v Ids = FFs * phit + ( 1 -­‐ FFs) * vx01; = vx01 * Leff / mu; = vx01 * Leff / mu ; = Vdsats * ( 1 -­‐ FFs ) + two_ns_phit * FFs; = Vdsats1 * ( 1 -­‐ FFs ) + two_ns_phit * FFs; = Vdsi; = Vdsc / Vdsat / ( pow( 1.0 + pow( abs( Vdsc / Vdsat ), beta ), 1.0 / = vx01 * Fsat; = dir * type * Wg * Qinvs * v; Sub-­‐circuit element definition I(di,si) = mu0 / Tfac / ( 1.0 + mtheta * Qinvs / Cg ); = vxo / ( 1.0 + vtheta * ( Qinvs / Cg ) ) * Tvfac * ( 1.0 + lamda * Vdsi <+ Ids; In the next section, the model formulation for currents of source and drain access regions will be explained. 4. Source and drain implicit-­‐gate transistor drain current formulation In the MVSG-­‐RF model, the source and drain access regions are assumed to be long enough (compared to mean free path) so that carrier transport is drift-­‐diffusion based. So the implicit-­‐gate model for these regions are essentially long channel transistor models which are suitable for channel lengths longer than ~500nm. The gate overdrive voltage is linked to the sheet resistance as given in [7]. The rest of the formulation is that of a conventional long channel FET model. The long channel model equations employed in MVSG-­‐RF model for these regions assumes the band profile as shown in Fig. 6. Fig. 6: Conduction band profile assumed in long channel transistor model under drain bias. The current is still given by the product of charge and velocity at the VS point (for that matter at any point in the channel, current is the product of local charge and velocity) but while the charge at the VS point is still the same as given by (2), the velocity at the VS point is no longer a simple constant, bias-­‐independent quantity as in scaled HEMTs. In long channels, transport is governed by drift/diffusion (DD) and the carrier velocity at any point in the channel is dependent on the local field as 𝑣! = µμ!"" 𝐸! . The current is evaluated using the following procedure: The master equation for drift current is given by !"
I! /𝑊 = 𝑄!" 𝑣! = 𝑄!" µμ!"" 𝐸! = 𝑄!" µμ!"" !" (8) Here ψ is the potential at location x. For the charge-­‐based simplified all-­‐region model, the channel layer charge is expressed as given in [8] and !!!"
= 𝐶!"# (9) !"
Using Caughey and Thomas model [4] for carrier velocity dependence on field, the effective mobility is given by !
µμ!"" =
!!
! !/!
!!
!"
!! ! !
(10) This formulation assumes that the carrier velocity profile with field is similar to that of Si i.e. carrier velocity increases with field and saturates at saturation velocity. It takes the form of drift velocity in strong accumulation and diffusion velocity in weak accumulation. In addition, in strong accumulation the velocity ‘v’ includes GaN specific effects such as self-­‐
heating and scattering whose functions are multiplied to bias-­‐independent saturation velocity (vsat0). Using (9-­‐10), (8) can be rewritten as !
I! /W = Q !"
!!
!!!"
!!!"
!!"# !! ! !!"
Using current continuity and assuming !!!"
!"
=
! !/!
!!"# !"
!!" !!!"
!!
(11) in the denominator of (11), we can integrate the above expression from x=0 to x=L! and Q !" = Q !" to Q !" = Q !" . The resulting current is given by I! /𝑊
= !!
!!" ! !!!" !
!
!"# !!
!!
!/!
!!" !!!" !
!!"# !! ! !
(12) Here 𝑣 is the carrier velocity combining strong and weak accumulation regimes, as discussed below. In order to make the current expression look similar to that of VS model expression in (4), the previous expression (12) can be reformulated as follows !!
!
= 𝑣 !!
!!" ! !!!" !
!
!"# !!"#$
!!
!!" !!!"
!!"# !!"#$
Where 𝐹!"#$ =
!!
!
!!" !!!" ! !
!!"# !!"#$
!!" !!!"
!!"# !!"#$
!
! !
=𝑣
!!" !!!"
!
𝐹!"#$ (13) and 𝑉!"#$ is similar to that in (5). 𝑉!"#$ must account for both strong and weak accumulation regimes and so should 𝑣. To do this we follow a similar procedure as in (5) and is shown below. ! !
𝑉!"#$ = 𝑉!"#$" (1 − 𝐹! ) + 2𝑛𝜑! 𝐹! and 𝑉!"#$" = !"#! ! (14a) !
𝑣 = 𝑣!"# (1 − 𝐹! ) + 2𝜑! ! 𝐹! (14b) !
𝑣!"# is what we call the GaN ‘saturation velocity’ which is similar to the saturation velocity in Si. In the long channel limit, where transport is mobility limited (Non-­‐velocity saturation: ! !!
! !!
NVsat), 𝑉!"#$ ≫ !"! !" which means 𝐹!"#$ = ! !"! !" and (13) reduces to !"# !"#$
!"#
!!
!
! ! !!!" !
= 𝑣 !!!"
!"# !!"#$
(15) (15) has a form very similar to the EKV model used for long channel MOSFETs. In shorter ! !!
channel velocity saturation (Vsat) limit, 𝑉!"#$ ≪ !"! !" and 𝐹!"#$ = 1 which leads to a !"#
simple current expression !!
𝑄!" = 2𝐶!"# 𝑛 𝜑! 𝑙𝑛 1 + 𝑒𝑥𝑝
!
=𝑣
!!" !!!"
(16) This expression for current is of the same form as VS model expression of (4) except that the charge here is the average of source-­‐end and drain-­‐end charges while in the VS Model it is just the charge at the VS point. The expression for charges at the source-­‐end and drain-­‐
end is similar to that in (2) and are given by (17) !
!!"# ! !! !!"! !!
𝑄!" = 2𝐶!"# 𝑛 𝜑! 𝑙𝑛 1 + 𝑒𝑥𝑝
!! !!
!!"# ! !! !!"! !!
!! !!
The charge expressions above expressions above are needed to model the subthreshold regime accurately. In the subthreshold regime the above expressions are reduced to ! ! !! !!"!
!
! ! !!"!
𝑄!" = 2𝐶!"# 𝑛 𝜑! 𝑒𝑥𝑝 !"# !! !
; 𝑄!" = 2𝐶!"# 𝑛 𝜑! 𝑒𝑥𝑝 !"# !! !!
(18) !
!
Substituting (14) and (18) in (13), the current I! in subthreshold regime, where diffusion current dominates, is !!
!
= 𝑣 !!
!
! !! !!"!
!!!"# ! !! !"# !"#
!
!! !!
!
! !! !!"!
!
! !! !!"!
!!!"# ! !! !"# !"# !! !
!!!!"! ! !! !"# !"# !! !
!
!
!!"# !!"#$
! !!!"# ! !! !
≈ 2𝜑! !
!
!
= 𝜑! !
!
!
! !! !!"!
! !!!"# ! !! !"# !"#
!! !!
!"# !!"#$
!!
!!
!
! !!!"# !!"!
2𝐶!"# 𝑛 𝜑! 𝑒𝑥𝑝
𝑒𝑥𝑝
!!"# ! !! !!"!
!!"# ! !! !!"!
! !!
! !!
− 𝑒𝑥𝑝
!!"# ! !! !!"!
! !!
!
!
! !
!
! ! !!"!
− 2𝐶!"# 𝑛 𝜑! 𝑒𝑥𝑝 !"# ! !!
(19) !
This is similar to the well-­‐known sub threshold MOSFET diffusion current. Transition from non-­‐saturation to saturation current In order to facilitate smooth transition from linear to saturation regimes under applied V!" we use the same function 𝐹!"# as in (4). The charge expression at the drain-­‐end is modified accordingly as 𝑄!" = 2𝐶!"# 𝑛 𝜑! 𝑙𝑛 1 + 𝑒𝑥𝑝
!!"# !!!"#$ !!"# ! !! !!"! !!
!! !!
(20) Where 𝑉!"#$ 𝐹!"# is given by 𝑉!"#$ 𝐹!"# = 𝑉!"#$
!!"#/ !!"#$
!! !!"#/ !!"#$
! !/!
=
!!"#
!! !!"#/ !!"#$
! !/!
(21) Here 𝑉!"#$ is as given in (14a) and 𝑉!"# = 𝑉!" − 𝑉!" is the intrinsic drain to source voltage. In the linear regime (at low 𝑉!"# ), 𝑉!"#$ 𝐹!"# approaches 𝑉!"#" and 𝑄!" in (20) becomes comparable to 𝑄!" . Thus, the current formulation of (12) reduces to !!
!
= !!
!!" ! !!!" !
!
!"# !!
!!
!!" !!!"
!!!" !!"#$
!
! !
= !!
!
!"# !!
!!!"
𝑄!" ! − 𝑄!" ! ≈ !
!"# !!
𝑄!" − 𝑄!" (22) Irrespective of 𝑉!"#$ , the denominator of the first expression in (22) tends to 1 as 𝑄!" − 𝑄!" << 𝐶!"# 𝑉!"#$ . Thus, transport regime (NVsat or Vsat) has no bearing on current in linear regime. More details of this long channel implicit-­‐gate model can be found in [2]. The equations described so far for the access regions are implemented in the Verilog-­‐A file as given below: Drain side implicit-­‐gate transistor Electrostatic parameter definition //Current in drain side access transistor dibsatrd = Vdsrdi / ( pow ( 1.0 + pow( abs( Vdsrdi / Vdibsat ), betard ), 1.0 / betard ) ); deltard = ( delta1rd -­‐ delta2rd * dibsatrd ) * Vdsrdi; nrd = Srd / ( 2.3 * phit ) + ndrd * Vdsrdi; VtObrd = VtOrd; etaFFsrd = ( Vgsrdi -­‐ ( VtObrd -­‐ deltard -­‐ alpha_phit / 2.0 ) ) / ( nrd * alpha_phit ); if ( etaFFsrd <= `LARGE_VALUE ) begin FFsrd = 1.0 / (1 + exp( etaFFsrd ) ); end else begin FFsrd = exp( -­‐etaFFsrd ); end two_ns_phitrd = 2.0 * nrd * phit; Source charge definition Qrefsrd = Cgrd * two_ns_phitrd; etasrd = ( ( Vgsrdi ) -­‐ ( VtObrd -­‐ deltard -­‐ 0.5 * alpha_phit * FFsrd ) ) / two_ns_phitrd; if ( etasrd <= `LARGE_VALUE ) begin Qinvsrd = Qrefsrd * ln( 1.0 + exp( etasrd ) ); end else begin Qinvsrd = Qrefsrd * ( etasrd ); end GaN specific effects definition murd = mu0 / Tfacrd / ( 1.0 + mtheta * Qinvsrd / Cgrd ); vx01rd = vxo / ( 1.0 + vthetard * ( Qinvsrd / Cgrd ) ) * Tvfac; vx0rd = 2.0 * FFsrd * phit * murd / Ld + ( 1 -­‐ FFsrd ) * vx01rd; Vdsatsrd = vx01rd * Ld / murd; Vdsats1rd = vx01rd * Ld / murd; Vdsatrd = Vdsatsrd * ( 1 -­‐ FFsrd ) + two_ns_phitrd * FFsrd; Vdsat1rd = Vdsats1rd * ( 1 -­‐ FFsrd ) + two_ns_phitrd * FFsrd; Fsdrd = 1.0 / pow( 1.0 + pow( abs( Vdsrdi / Vdsat1rd ) , betard ), 1.0 / betard ); Vdxrd = Vdsrdi * Fsdrd; etaFFdrd =( Vgsrdi -­‐ Vdsrdi -­‐ ( VtObrd -­‐ deltard -­‐ alpha_phit / 2.0 ) ) / ( nrd * alpha_phit ); if ( etaFFdrd <= `LARGE_VALUE ) begin FFdrd = 1.0 / ( 1 + exp( etaFFdrd ) ); end else begin FFdrd = exp( -­‐etaFFdrd ); end two_nd_phitrd = 2.0 * nrd * phit; Drain charge definition Qrefdrd = Cgrd * two_nd_phitrd; etadrd = ( Vgsrdi -­‐ Vdxrd -­‐ ( VtObrd -­‐ deltard -­‐ 0.5 * alpha_phit * FFdrd ) ) / two_nd_phitrd; if ( etadrd <= `LARGE_VALUE ) begin Qinvdrd = Qrefdrd * ln( 1.0 + exp( etadrd ) ); end else begin Qinvdrd = Qrefdrd * ( etadrd ); end Vdscrd = ( Qinvsrd -­‐ Qinvdrd ) / Cgrd; Fsatrd = Vdscrd / Vdsatrd / ( pow( 1.0 + pow( abs( Vdscrd / Vdsatrd ), betard ), 1.0 / betard ) ); vrd = vx0rd * Fsatrd; Idsrd = dirrd * type * Wg * 0.5 * ( Qinvsrd + Qinvdrd ) * vrd; Sub-­‐circuit element definition if (Rsh > 0 && Ld > 0) I(drc,di) <+ Idsrd; else V(drc,di) <+ 0; Drain side contact resistance definition //Drain side contact resistance if (Rc > 0) I(drc,d) <+ V(drc,d) / ( Rc / Wg ); else V(drc,d) <+ 0; Source side implicit-­‐gate transistor Electrostatic parameter definition //Current in source side access transistor dibsatrs = Vdsrsi / ( pow( 1.0 + pow( abs( Vdsrsi / Vdibsat ), betars ), 1.0 / betars ) ); deltars = ( delta1rs -­‐ delta2rs * dibsatrs ) * Vdsrsi; nrs = Srs / ( 2.3 * phit ) + ndrs * Vdsrsi; VtObrs = VtOrs; etaFFsrs = ( Vgsrsi -­‐ ( VtObrs -­‐ deltars -­‐ alpha_phit / 2.0 ) ) / ( nrs * alpha_phit ); if ( etaFFsrs <= `LARGE_VALUE ) begin FFsrs = 1.0 / ( 1 + exp( etaFFsrs ) ); end else begin FFsrs = exp( -­‐etaFFsrs ); end two_ns_phitrs = 2.0 * nrs * phit; Source charge definition Qrefsrs = Cgrs * two_ns_phitrs; etasrs = ( ( Vgsrsi ) -­‐ ( VtObrs -­‐ deltars -­‐ 0.5 * alpha_phit * FFsrs ) ) / two_ns_phitrs; if ( etasrs <= `LARGE_VALUE ) begin Qinvsrs = Qrefsrs * ln( 1.0 + exp( etasrs ) ); end else begin Qinvsrs = Qrefsrs * ( etasrs ); end GaN specific effects definition murs = mu0 / Tfacrs / ( 1.0 + mtheta * Qinvsrs / Cgrs ); vx01rs = vxo / ( 1.0 + vthetars * ( Qinvsrs / Cgrs ) ) * Tvfac; vx0rs = 2.0 * FFsrs * phit * murs / Ls + ( 1 -­‐ FFsrs ) * vx01rs; Vdsatsrs = vx01rs * Ls / murs; Vdsats1rs = vx01rs * Ls / murs; Vdsatrs = Vdsatsrs * ( 1 -­‐ FFsrs ) + two_ns_phitrs * FFsrs; Vdsat1rs = Vdsats1rs * ( 1 -­‐ FFsrs ) + two_ns_phitrs * FFsrs; Fsdrs = 1.0 / pow( 1.0 + pow( abs( Vdsrsi / Vdsat1rs ), betars), 1.0 / betars ); Vdxrs = Vdsrsi * Fsdrs; etaFFdrs =( Vgsrsi -­‐ Vdsrsi -­‐ ( VtObrs -­‐ deltars -­‐ alpha_phit / 2.0 ) ) / ( nrs * alpha_phit ); if (etaFFdrs <= `LARGE_VALUE) begin FFdrs = 1.0 / ( 1 + exp( etaFFdrs ) ); end else begin FFdrs = exp( -­‐etaFFdrs ); end two_nd_phitrs = 2.0 * nrs * phit; Drain charge definition Qrefdrs = Cgrs * two_nd_phitrs; etadrs = ( Vgsrsi -­‐ Vdxrs -­‐ ( VtObrs -­‐ deltars -­‐ 0.5 * alpha_phit * FFdrs ) ) / two_nd_phitrs; if (etadrs <= `LARGE_VALUE) begin Qinvdrs = Qrefdrs * ln( 1.0 + exp( etadrs ) ); end else begin Qinvdrs = Qrefdrs * ( etadrs ); end Vdscrs = ( Qinvsrs -­‐ Qinvdrs ) / Cgrs; Fsatrs = Vdscrs / Vdsatrs / ( pow( 1.0 + pow( abs( Vdscrs / Vdsatrs ), betars ), 1.0 / betars ) ); vrs = vx0rs * Fsatrs; Idsrs = dirrs * type * Wg * 0.5 * ( Qinvsrs + Qinvdrs ) * vrs; Sub-­‐circuit element definition if (Rsh > 0 && Ls > 0) I(si,src) <+ Idsrs; else V(src,si) <+ 0; Source side contact resistance definition //Source side contact resistance if (Rc > 0) I(src,s) <+ V(src,s) / ( Rc / Wg ); else V(src,s) <+ 0; This completes the Verilog-­‐A code for modeling drain current in RF-­‐GaN HEMTs. In addition to currents, charges associated with the device are to be modeled to enable dynamic device applications. This is explained in the following section. 5. Intrinsic transistor channel charge formulation Any compact model in addition to models for terminal currents must also include model for terminal charges. Models for charges (and hence capacitances) are essential to reproduce dynamic behavior of devices for circuit simulation purposes. MVSG-­‐RF model has model for gate charge. Further, the gate charge is partitioned into gate-­‐source charge (𝑄!"# ) and gate-­‐
drain charge (𝑄!"# ) using the well known Ward-­‐Dutton charge partitioning. A simple single moment partition method is used to get analytical closed form expressions for 𝑄!"# and 𝑄!"# . 𝑄!"# =
!!!!
!!!
𝑄!"# =
!!!! !
!!!
!!
!
1−!
!
𝑄!" x dx (23a) 𝑄!" x dx (23b) Here 𝑄!" x is the areal charge density at any point ‘x’ in the channel. 𝑄!" x and its dependence on bias depends on the mode of transport of carriers in the channel. In this regard as before there are three cases possible. Firstly model for gate charge in highly scaled GaN HEMTs where transport could be quasi-­‐ballistic will be discussed. This will be followed by model for gate charge in longer channel GaN HEMTs where transport is drift-­‐
diffusion (DD) based, either in velocity saturation or mobility limited regime. Gate charge in Quasi-­‐ballistic regime In highly scaled GaN HEMTs with conduction band profile as shown in Fig. 5, quasi-­‐ballistic transport causes total average areal gate charge density to be lower than the case where transport is DD limited. This is because once carriers are injected at the VS point with velocity 𝑣!" , they are accelerated due to the high field after VS point. So in order to sustain the same current, ballistic transport, which has higher carrier velocity in most part of the channel in comparison to DD transport, would require lesser average channel charge density. To model gate charge, we employ current continuity and energy conservation for carriers. Since the areal charge density at VS point (equation (2)) and the velocity at this point (𝑣!" ) are known, if velocity at every point in the channel could be known then areal charge density can be known as a function of position by employing current continuity. 𝐼! = 𝑄!"# 𝑣!" = 𝑄!" x 𝑣! (𝑥) (24) To compute 𝑣! (𝑥) energy conservation is employed. Carriers crossing the VS point are accelerated by the field which increases their velocity. This velocity can be found as !
!
! 𝑚! 𝑣!! 𝑥 = ! 𝑚! 𝑣!! + 𝛾𝑞𝑉(𝑥) (25) where V(x) is channel potential as a function of V(x). If V(x) is assumed a linear function of position (25) gives 𝑣! (𝑥) as 𝑣! 𝑥 =
𝑣!! +
!!"# !
!
=
𝑣!! +
!!"#!!"#"
!!!
(26) Here 𝛾 is a parameter which governs the fraction of total energy due to drain voltage (𝑞𝑉!"#" ) that is gained by carriers. Using (26) in (24) we get closed form expression for 𝑄!" x . (23) then gives 𝑄!"# and 𝑄!"# as 𝑄!"# = 𝑊𝐿! 𝑄!"#
!!!!
!!!!(!!!!)
!!!!
!!!!!
; 𝑄!"# = 𝑊𝐿! 𝑄!"#
; (27) !! !
!!"!!"#"
Where = !! ! . Similar set of equations can be derived assuming parabolic dependence !! !
!
of channel potential on position. It has been found that choice of assumption has negligible bearing on 𝑄!"# and 𝑄!"# [9]. Gate charge in drift diffusion regime Gate charge in DD transport regime is generally higher than ballistic gate charge as velocity in channel is lesser in DD case (both in velocity saturation and mobility limited regimes). To model gate charge in DD regime, approach adopted by Prof. Tsividis is closely followed. Mobility dominated regime The derivation procedure for gate charge in this regime is similar to that found in the book written by Prof. Tsividis (section 6.4.2, chapter 6) [8] and is not repeated here. The final model equations are as below [8] 𝑄!"# = 𝑊𝐿! 𝑄!"
6+12t+8t2 +4t3
!(!!!)!
; 𝑄!"# = 𝑊𝐿! 𝑄!"
4+8t+12t2 +6t3
!(!!!)!
; (28) Here 𝑡 = 1 − 𝐹!"#$ = 1 −
!!"#" /!!"#$%
!! !!"#" /!!"#$%
! !/!
and 𝑉!"#$% =
3𝜑!
!
+
!!"
!
!"!"# . These definitions of t and 𝑉!"#$% bring in self-­‐consistency with transport model. Since expressions for 𝑄!" and 𝐹!"#$ remain the same as that in model for current and (28) is arrived at based on physics (please refer [8] for more details) , charge model is self-­‐
consistent with current model. Velocity saturation dominated regime A detailed derivation of gate charge model in Vsat case can be found in appendix of [9] and is not repeated here. The model equations are as follows !"!"#$%
!!"#$% !!"#$
!"!"#$%
𝑄!"# = 𝑊𝐿! 𝑄!"
−
+
𝐴
(1
−
𝐵
)
; 𝑄
=
𝑊𝐿
𝑄
−
!
!
!"#
!
!"
!
!.!
!
!!"#$% !!"#$
!.!
Where 𝐴! = A 1 +
+ 𝐴! 𝐵! ; (29) !!"#$% !!"#$
!!!
; 𝐵! = 𝐵 1 + !!!!
!
With A =
!
!"!"#$% !!"#$
!"!!!!"#$
!
! !!"#$% !!"#$
!
!
!!"
!!!!!"#$% !!"#$
!"!"# !!!!
; 𝐵 = !"!!!!"#$ !"#$
Just like in the previous case, the charge model in velocity saturation is also physics based (please refer [9] for more details) and the use of Q !" and F!"#$ makes the model consistent with current model. The following lines in the Verilog-­‐A file implement the core-­‐equations of the intrinsic transistor charge described in this section. Drift diffusion formulation Vgt alp Vdsatq beta1 Fsatq / beta1 ) ); t den qsc qdc Quasi-­‐ballistic formulation = Qinv / Cg; = 1.0; = sqrt( 9.0 * phit * phit + Vgt * Vgt / ( alp * alp ) ); = 1.5; = ( ( Vdsi ) / Vdsatq ) / ( 1.0 + pow( pow( Vdsi / Vdsatq, beta1 ), 1.0 = 1.0 -­‐ Fsatq; = 15.0 * ( 1.0 + t ) * ( 1.0 + t ); = ( 6.0 + t * ( 12.0 + t * ( 8.0 + 4.0 * t ) ) ) / den; = ( 4.0 + t * ( 8.0 + t * ( 12.0 + 6.0 * t ) ) ) / den; me = 9.1e-­‐31 * mc; kq = 0.0; tol = ( `SMALL_VALUE * vxo / 100 ) * ( `SMALL_VALUE * vxo / 100 ) * me / ( 2 * `P_Q ); if ( Vdsi <= tol ) begin kq2 = ( 2.0 * `P_Q / me * Vdsi ) / ( vxo * vxo ) * 10000.0; kq4 = kq2 * kq2; qsb = 0.5 -­‐ kq2 / 24.0 + kq4 / 80.0; qdb = 0.5 -­‐ 0.125 * kq2 + kq4 / 16.0; end else begin kq kq2 qsb qdb end qs qd1 = sqrt( 2.0 * `P_Q / me * Vdsi ) / vxo * 100.0; = kq * kq; = asinh( kq ) / kq -­‐ ( sqrt( kq2 + 1.0 )-­‐1.0 ) / kq2; = ( sqrt( kq2 + 1.0 )-­‐1.0 ) / kq2; = Qinv * ( qsc * ( 1.0 -­‐ Fsat ) + qsb * Fsat ); = Qinv * ( qdc * ( 1.0 -­‐ Fsat ) + qdb * Fsat ); DIBL correction formulation etai = ( Vgsi -­‐ ( VtOb -­‐ FFs * alpha_phit ) ) / ( n * phit ); if ( etai <= `LARGE_VALUE ) Qinvi = Qrefs * ln( 1.0 + exp( etai ) ); else Qinvi = Qrefs * etai; dQinv = Qinv -­‐ Qinvi; qd = qd1 -­‐ ( 1.0 -­‐ Fsat ) * ( qs + qd1 ) * dQinv; Model for fringing field capacitances In addition to gate to channel capacitances GaN HEMTs also have outer and inner fringing capacitances. The schematic of these capacitances is shown in Fig. 7. Fig. 7: Schematic showing fringing capacitances in strong and weak inversion While inner fringing capacitance (Cif) is small in GaN HEMT compared to Si MOSFETs (as S/D are not self-­‐aligned with gate) the outer fringing capacitances (Cof) still have an effect. The inner fringing capacitances are screened in the on state by 2DEG in channel (by Cgc) but the outer fringing capacitance is present in both off and on states. Cof is just a parameter in the model, which can be extracted from C-­‐V in on state of different Lg devices with other geometry elements kept identical. Cif is also a number, which can be extracted from the same procedure as Cof, but C-­‐V must be done in off state. De-­‐embedding of pad and other parasitic capacitances is needed for extraction of Cif and Cof. Since Cif is screened in on state by channel charge, a transition function, which goes from 0 in on state to 1 in off state, is needs to be multiplied with Cif. This is implemented in the model by using Fermi-­‐like function similar to 𝐹! given in (3). This completes the description of MVSG-­‐RF model for GaN HEMT terminal current and charges. The model does not yet model GaN specific trap related effects like dynamic Ron and current collapse. In addition, there is no model yet for depletion charge in drain access region under large VDS. The relevant code lines for this sub-­‐section is shown below: Inner fringing capacitance formulation Fs_arg = ( Vgs_raw -­‐ VtOb ) / ( 1.0 * n * phit ); if ( Fs_arg <= `LARGE_VALUE ) begin Fs = 1.0 + exp( Fs_arg ); FFx = Vgs_raw -­‐ n * phit * ln( Fs ); end else begin Fs = 0.0; // not used FFx = Vgs_raw -­‐ n * phit * Fs_arg; end Fd_arg = ( Vgd_raw -­‐ VtOb ) / ( 5.0 * n * phit ); if ( Fd_arg <= `LARGE_VALUE ) begin Fd = 1.0 + exp( Fd_arg ); FFy = Vgd_raw -­‐ n * phit * ln( Fd ); end else begin Fd = 0.0; // not used FFy = Vgd_raw -­‐ n * phit * Fd_arg; end Qsif = type * Cif * FFx ; Qdif = type * Cif * FFy ; Channel capacitance formulation Qinvx Qinvy = type * Leff * 0.5 * ( ( 1 + dir ) * qs + ( 1 -­‐ dir ) * qd ); = type * Leff * 0.5 * ( ( 1 -­‐ dir ) * qs + ( 1 + dir ) * qd ); Outer fringing capacitance formulation Qsov Qdov Qs Qd Qb Qg = Cofs * (V(g) -­‐ V(si)); = Cofd * (V(g) -­‐ V(di)); Total device-­‐level charges formulation = -­‐Wg * ( Qinvx + Qsov + Qsif ); = -­‐Wg * ( Qinvy + Qdov + Qdif ); = 0; = -­‐ ( Qs + Qd + Qb ); Sub-­‐circuit-­‐implementation of charges I(g,si) I(g,di) <+ -­‐ddt(Qs); <+ -­‐ddt(Qd); RC thermal network implementation for capturing self-­‐heating if (Rth !=0) begin Pwr(dt) <+ ddt( Cth * Temp(dt) ); Pwr(dt) <+ -­‐ ( I(di,si) * V(di,si) + I(d,drc) * V(d,drc) + I(src,s) * V(src,s) + V(drc,di) * I(drc,di) + V(src,si) * I(src,si) ); Pwr(dt) <+ Temp(dt) / Rth; end else Temp(dt) <+0.0; end endmodule The module-­‐wise description of the Verilog-­‐A file was described so far. Another important aspect of Verilog-­‐A models is the parameter list that is needed for model optimization to data. This will be described in the following sections. MVSG-­‐RF Model: Parameter list The following table shows the list of all parameters needed for fitting MVSG-­‐RF model to experimental data. The description and data type of the parameters are also listed. The model is benchmarked against two different gate-­‐length-­‐RF-­‐GaN HEMTs. These are listed in the ‘MVSG-­‐RF_modelparameters’ folder with following file names: GaN_HEMT_Lg=42nm.txt : 42 nm gate length GaN-­‐HEMT [10] GaN_HEMT_Lg=105nm.txt : 105 nm gate length GaN-­‐HEMT [10] Data type Parameter Description real integer real real real real real real real real real real real real real real real real real real real real real real real real real real real real real real real real real real real real version MVSG model version = 1.0.0 type Type of transistor. nFET type=1; pFET type=-­‐1 W Width of the device [m] L Length of gate [m] Cg Gate areal capacitance [F/cm2] delta1 DIBL S Subthreshold slope V/Dec nd Factor affects slope change in subthreshold Rsh Access region sheet resistance [ohm/square] Cifm Inner fringing cap on each side[F/m] Cofsm Outer fringing cap on source side[F/m] Cofdm Outer fringing cap on drain side[F/m] vxo Source injection velocity [cm/s] mu0 Low field mobility [cm2/Vs] beta Linear to saturation transition parameter VtO Threshold voltage [V] alpha Strong to weak inversion transition parameter mc Effective mass parameter Lgs Source access region length [m] Lgd Drain access region length [m] vzeta Self heating parameter (scalable) epsilon Self heating mobility parameter (fixed) lamda CLM parameter [1/V] Rc Contact resistance on each side [ohm-­‐cm] Rth Thermal resistance (To be kept equal to zeta) Cth Thermal capacitance Tnom Nominal (extraction) temperature vxord Source injection velocity [cm/s] VtOrd Threshold voltage of drain access transistor[V] Cgrd Drain access areal capacitance [F/cm2] delta1rd DIBL for drain access transitor delta2rd DIBL for drain access transitor Vdibsat DIBL for drain access transitor Srd Subthreshold slope for drain access transitor [V/Dec] zeta Self heating parameter (scalable) betard Linear to saturation transition parameter vthetard Scattering: velocity reduction parameter with Vg ndrd Punchthrough factor real real real real real real real real real vxors = vxord Source injection velocity [cm/s] VtOrs = VtOrd Threshold voltage of source access transistor[V] Cgrs = Cgrd Drain access areal capacitance [F/cm2] delta1rs = delta1rd DIBL for source access transistor delta2rs = delta2rd DIBL for source access transistor Srs = Srd Subthreshold slope for source transistor [V/Dec] vthetars Scattering: velocity reduction parameter with Vg ndrs = ndrd Punch-­‐through factor betars= betard Linear to saturation transition parameter Parameter extraction procedure for MVSG-­‐RF Model The following flowchart shows the extraction procedure of important parameters of MIT GaN HEMT model. Fig. 8: Flowchart showing parameter extraction flow This is not the exhaustive list of parameters but the most significant ones. Most of the other parameters are either fitting parameters or constants for GaN HEMT. All parameters will be discussed in subsequent sub-­‐sections. Device parameters Geometry and structural information are best provided by foundry. For the model, geometry parameters needed are: Gate length (Lg), Source access region (Lgs), drain-­‐access region length (Lgd), device-­‐width (W). In addition, parameters related to field plate such as field plate length, inter-­‐layer dielectric thickness etc. might be necessary for future modeling. Other additional useful parameters required by the model are: Low field mobility (µo), Contact resistance (Rc) and sheet resistance (Rsh), 2DEG density. If these are not provided, additional measurements might be needed to extract them. µo and Rsh extraction would require Hall measurements and special hall structures. Rc can be extracted by measuring resistances of TLM structures of different lengths and extracting the offset at Lg=0. Correct extraction of these parameters can also be verified from Ron match in output characteristics. Cg extraction Cg is an important model parameter in MVSG-­‐RF model. Its accurate extraction is essential for correct modeling. Cg must be extracted from CV measurements rather than from analytical calculation. Accurate analytical calculation must also include quantum correction as charge centroid in 2DEG is shifted away from the interface. This needs dedicated calculations/simulation, which from a compact modeling perspective might not be critical as long as we can directly measure the capacitance. To get Cg, two terminal CV (with VDS=0) of devices with different gate length but identical widths and access region lengths must be measured. The gate to channel capacitance in strong accumulation scales as a function of Lg. From the slope we get the value of Cg (areal gate capacitance) and the intercept gives the parasitic capacitance. Parasitic capacitance includes outer fringing capacitance (Cof) and pad parasitic. To remove the pad parasitic, we need CV of open test structures. Fig. 9: Illustration of extraction of Cg devices of different gate lengths Extraction of Vto, S and DIBL (delta1) Fig. 10: Illustration of extraction of Vto, S and DIBL from transfer curves Threshold voltage (Vt) computation requires knowledge of piezoelectric charges at the interface, heterostructure composition and thickness. Again the model is simplistic in the sense that Vto needed for the model can be extracted from device data. The requirement is one data point (VG, ID, VD) in weak accumulation (just beyond strong to weak accumulation transition) at low VD (~0V where DIBL has negligible impact). Alternately Vto can be approximated as VG at the same (VG, ID, VD) point on transfer curve. Sub threshold slope (S) is obtained from the slope of the transfer curve on log scale in weak accumulation regime. Low VD is preferred to avoid shift of S due to modest punch through in the device. The parameter extracted must make sense for the Lg of the device. DIBL is extracted from the lateral shift of ID (due to shift of Vt) as VD is increased in the transfer curves in weak accumulation. DIBL is multiplied by intrinsic drain voltage (VDi) in the expression for threshold voltage in the model. It can be extracted from the weak accumulation regime as shown in Figure. 14. Extraction of vsato/vxo, β (beta) and 𝜽𝒗 (vtheta), 𝜽𝝁 (mtheta) and Rth vsato/vxo, β and 𝜃! , 𝜃! and 𝑅th can be extracted from output characteristics. vsato/vxo can be fitted to get accurate match with saturation current level. vxo extracted must lie between the bracket of peak electron velocity (2.5×107cm/s) and saturation velocity (1.3×107cm/s) depending on gate length. The transition from linear to saturation current in output characteristics is governed by Fsat which has a parameter β. β should ideally lie between 1.5-­‐3 for these type of HEMTs depending on saturation. 𝜂! is thermal coefficient affecting velocity. They can be extracted from slope of output curves in saturation at large VG where self-­‐heating is dominant. 𝜂! together with the thermal resistance (Rth) is directly responsible for the negative slope of the output curves and can be extracted from fitting. 𝜃! and 𝜃! are also fitting parameters which affect VDSAT. They can be extracted from VDSAT at lower VGS when self-­‐heating has not yet kicked in. Thus by fitting to get correct linear-­‐to-­‐saturation transition voltages at larger VGS we can get values of 𝜃! and 𝜃! . Rth of the thermal network is also obtained in high bias-­‐region where self-­‐heating is predominant. Since Rth characterization through TCAD and evaluation of thermal coefficients through multi-­‐temperature measurements has not been done yet, it has been reduced to a fitting parameter for now. Fig. 11: Illustration of extraction vsato/vinj, β and θ! , θ! , R !" and η! from output curves Spectre simulation results Netlist: idvd.scs
Output characteristics
Parameter file: GaN_HEMT_Lg=105nm
Figure 12: Output characteristics of 105 nm GaN HEMT in (a) linear and (b) semi-­‐log scale. VGS ranges from -­‐6 V to 0 V in steps of 0.5 V. The currents are normalized with respect to gate width (A/mm); with width in this case being 25e-­‐3 mm. Gate current is not included in the model. Compression of current curves at VGS ~ 0 V is due to non-­‐linear access regions. Output conductance
Figure 13: Output-­‐conductance plots in (a) linear and (b) semi-­‐log scale for the 105-­‐nm device. VGS range is from -­‐6 V to 0 V in steps of 0.5 V. The output conductance is normalized with respect to gate width (S/mm), with width in this case being 25e-­‐3 mm. Netlist: idvd.scs
Output characteristics
Parameter file: GaN_HEMT_Lg=42nm
Figure 14: Output characteristics of 42 nm GaN HEMT in (a) linear and (b) semi-­‐log scale. VGS ranges from -­‐6 V to 0 V in steps of 0.5 V. The currents are normalized with respect to gate width (A/mm); with width in this case being 25e-­‐3 mm. Gate current is not included in the model. Compression of current curves at VGS ~ 0 V is due to non-­‐linear access regions. High SCE such as punch-­‐through and DIBL cause high output-­‐conductance in saturation. Output conductance
Figure 15: Output-­‐conductance plots in (a) linear and (b) semi-­‐log scale for the 42-­‐nm device. VGS range is from -­‐6 V to 0 V in steps of 0.5 V. The output conductance is normalized with respect to gate width (S/mm), with width in this case being 25e-­‐3 mm. Netlist: idvg.scs
Transfer characteristics
Parameter file: GaN_HEMT_Lg=105nm
Figure 16: Transfer characteristics of 105 nm GaN HEMT in (a) linear and (b) semi-­‐log scale. VDS ranges from 0.1 V, 0.5 V to 4 V in steps of 0.5 V. The currents are normalized with respect to gate width (A/mm), with width in this case being 25e-­‐3 mm. Modest DIBL and punch-­‐
through in the model captures the sub-­‐threshold regime of the device. Transconductance
Figure 17: Transconductance plots in (a) linear and (b) semi-­‐log scale for the 105-­‐nm device. VDS ranges from 0.1 V, 0.5 V to 4 V in steps of 0.5 V. The transconductance is normalized with respect to gate width (S/mm), with width in this case being 25e-­‐3 mm. Netlist: idvg.scs
Transfer characteristics
Parameter file: GaN_HEMT_Lg=42nm
Figure 18: Transfer characteristics of 42 nm GaN HEMT in (a) linear and (b) semi-­‐log scale. VDS ranges from 0.1 V, 0.5 V to 4 V in steps of 0.5 V. The currents are normalized with respect to gate width (A/mm), with width in this case being 25e-­‐3 mm. Punch-­‐through and DIBL is higher in this device than in 105-­‐nm gate length device. Transconductance
Figure 19: Transconductance plots in (a) linear and (b) semi-­‐log scale for the 42-­‐nm device. VDS ranges from 0.1 V, 0.5 V to 4 V in steps of 0.5 V. The transconductance is normalized with respect to gate width (S/mm), with width in this case being 25e-­‐3 mm. Netlist: cv.scs
Cgg characteristics
Parameter files: GaN_HEMT_Lg=105nm
Figure 20: Input capacitance characteristics (in fF/mm) of 105 nm GaN HEMT device obtained from S-­‐parameter measurements. VDS =0V, 0.5V and 1V. Netlist: cv.scs
Cgg characteristics
Parameter files: GaN_HEMT_Lg=42nm
Figure 21: Input capacitance characteristics of 42 nm GaN HEMT device (in fF/mm) obtained from S-­‐parameter measurements. VDS =0V, 0.5V and 1V. The model fits show a rough estimate of the S-­‐parameter derived input capacitances. Netlist: dc_invertor.scs
Quasi-invertor voltage transfer characteristics
Parameter files: GaN_HEMT_Lg=105nm
Figure 22: Voltage transfer characteristics of a quasi-­‐invertor built using D-­‐mode, 105 nm GaN HEMT device. The load resistor to the driver HEMT is built using diode connected HEMT. The output voltage transition happens at Vin ~ -­‐3 V corresponding to the Vt of the device. Netlist: dc_invertor.scs
Quasi-invertor voltage transfer characteristics
Parameter files: GaN_HEMT_Lg=42nm
Figure 23: Voltage transfer characteristics of a quasi-­‐invertor built using D-­‐mode, 42 nm GaN HEMT device. The output voltage transition happens at Vin ~ -­‐3 V corresponding to the Vt of the device. The smoother transition is due to poorer subthreshold behavior of the 42 nm device compared to 105-­‐nm device. References [1] ‘Modeling GaN: Powerful but challenging’-­‐D. Lawerence et al., IEEE microwave magazine, Oct-­‐2010. [2] ‘Compact transport and charge model for Gallium Nitride-­‐based HEMTs for radio-­‐
frequency applications’-­‐ U. Radhakrishna, MIT, Jun.-­‐2013, Citable URI: http://hdl.handle.net/1721.1/82394
[3] ‘A simple semi-­‐empirical short-­‐channel MOSFET current-­‐voltage model continuous across all regions of operation and employing only physical parameters’-­‐ A. Khakifirooz, O. M. Nayfeh, and D. Antoniadis, IEEE Trans. Electron Devices, vol.56, no. 8, pp. 1674–1680, Aug. 2009. [4] ‘Carrier mobilities in silicon empirically related to doping and field,’-­‐ D. Caughey and R. Thomas, Proceedings of the IEEE, vol. 55, no. 12, pp. 2192{2193}, 1967.
[5] ‘A thermal model for static current characteristics of AlGaN/GaN high electron mobility transistors including self-­‐heating effect’-­‐ Y. Chang, Y. Zhang, Y. Zhang and K.Y. Tong, Journal of App. Physics., 99 (044501), 2006. [6] ‘Effect of gate-­‐field dependent mobility degradation on distortion analysis in MOSFETs,’-­‐R. V. Langevelde, F. M. Klaassen, IEEE Trans. Electron Devices, vol.44, no. 11, pp. 2044–2052, Nov. 1997. [7] ‘Physics-­‐based Compact Model of High Voltage GaN HEMTs: Experimental Verification, Field Plate Optimization and Charge Trapping’-­‐ U. Radhakrishna, D. Piedra, Y. Zhang, T. Palacios, D. Antoniadis, Electron Devices Meeting (IEDM), 2013 IEEE International , Dec. 2013.
[8] ‘Operation and modeling of the MOS transistor’ – Y. Tsividis, 3 edition, Mcgraw Hill. [9] ‘Virtual-­‐Source-­‐Based Self-­‐Consistent Current and Charge FET Models: From Ballistic to Drift-­‐Diffusion Velocity-­‐Saturation Operation,’-­‐ L. Wei, O. Mysore, and D. Antoniadis, IEEE Trans. Electron Devices, vol.59, no. 5, pp. 1263–1271, May. 2012. [10] ’Physics-­‐based GaN HEMT transport and charge model: Experimental verification and performance projection’-­‐ Radhakrishna, U., Lan Wei, Dong-­‐Seup Lee, Palacios, T., Antoniadis, D., Electron Devices Meeting (IEDM), 2012 IEEE International , pp.13.6.1,13.6.4, 10-­‐13 Dec. 2012.