Performance and Limitations
of 65 nm CMOS for
Integrated RF Power Applications
J. Scholvin 1, D. Greenberg 2,
and J. A. del Alamo 1
1 MIT,
Cambridge, MA
2 IBM Research, Hopewell Jct., NY
Sponsors: IBM Faculty Award, IBM PhD Fellowship Program
Acknowledgements: Jack Pekarik
Outline
•
•
•
•
•
•
Why 65 nm CMOS for RF Power
Performance of Standard 65 nm Devices
Output Power Scaling
Optimizing Device Layout
Comparison with 90 nm and 0.25 µm
Conclusions
Why 65 nm CMOS for RF Power?
• System integration Æ 65 nm as a platform for digital
• High-volume, low cost consumer applications
– Current: WLAN, Bluetooth, Cell-phone PA driver, WiMax / 802.16
• Moderate frequencies (2-10 GHz)
• Medium power (<100 mW)
Benefits of Scaling
• Lg ↓ Æ ft ↑ fmax ↑
Gain ↑ PAE ↑
Æ
Peak PAE [%]
40
30
20
10
data for IEEE published GaAs MESFETs,
27 GHz < freq < 50 GHz
0
0
0.2
0.4
0.6
0.8
1
Lg [µm]
• 65 nm RF performance should benefit from scaling
Issues of CMOS for RF Power
• Concerns: CMOS Scaling Æ Vdd ↓ Æ Pout ↓
Power Density [W/mm]
1
0.1
0.01
data for IEEE published
CMOS PA devices and
circuits
0.001
0.1
1
10
Vdd [V]
• Possible Solutions:
– Raise Vdd ⇒ impact on reliability
– Use I/O devices (if available) ⇒ process complexity (cost)
– Increase device width
Outline
•
•
•
•
•
•
Why 65 nm CMOS for RF Power
Performance of Standard 65 nm Devices
Output Power Scaling
Optimizing Device Layout
Comparison with 90 nm and 0.25 µm
Conclusions
Experimental
• Devices designed and fabricated in IBM’s 65 nm CMOS
WG,TOT = NC x NF x WG,F
NC = # of cells
NF = # of fingers
WG,F = unit finger width
NC = 6
• Standard Device:
– WG,TOT = 768 µm
– NC x NF x WG,F = 1x64x12 µm
• Measurements:
– Maury Load Pull System
– 2-18 GHz
NF=4
WG,F = 5 µm
RF power performance of
standard 65 nm devices
70
1x64x12 µm
PAE [%], Gain [dB]
60
Freq = 4 GHz
Vdd = 1 V
50
Id = 26 mA/mm
40
PAE
30
20
Gain
10
0
-10
0
10
20
Pout [dBm]
1x64x12 µm:
Peak PAE = 62% at Pout = 13.8 dBm
RF power performance of
standard 65 nm devices
PAE [%], Gain [dB]
70
60
1x64x12 µm
12x16x4 µm
Freq = 4SGHz 2
50
Vdd = 1 V
Id = 26 mA/mm
40
PAE
30
Gain
20
10
13.8 dBm = 24 mW = 31 mW/mm
0
-10
0
10
20
Pout [dBm]
1x64x12 µm:
12x16x4 µm:
Peak PAE = 62% at Pout = 13.8 dBm
Peak PAE = 66% at Pout = 13.7 dBm
RF power performance of
standard 65 nm devices
PAE [%], Gain [dB]
70
60
1x64x12 µm
12x16x4 µm
Freq = 4SGHz 2
50
Vdd = 1 V
Id = 26 mA/mm
40
PAE
Good PAE, but:
Can we get more power?
30
Gain
20
10
13.8 dBm = 24 mW = 31 mW/mm
0
-10
0
10
20
Pout [dBm]
1x64x12 µm:
12x16x4 µm:
Peak PAE = 62% at Pout = 13.8 dBm
Peak PAE = 66% at Pout = 13.7 dBm
Outline
•
•
•
•
•
•
Why 65 nm CMOS for RF Power
Performance of Standard 65 nm Devices
Output Power Scaling
Optimizing Device Layout
Comparison with 90 nm and 0.25 µm
Conclusions
Increasing Output Power
• 65 nm CMOS features sufficient PAE
• Possibilities to increase Pout
– Supply voltage (Vdd)
– Bias current (Idq)
– Device width (WG,TOT)
• Methodology:
– Optimize for peak PAE
Increasing Pout: Vdd
Peak PAE [%], Pout [mW]
60
40
PAE
20
Pout
0
0
Freq=8 GHz, Vdd=1 V, Id=26 mA/mm
12x16x4 µm
0.5
1
Vdd [V]
• Increases Pout without impacting PAE
• Potential drawback: reliability
1.5
Increasing Pout: IDQ
55
Freq=8 GHz
Vdd=1 V
12x16x4 µm
50
45
30
PAE
25
Pout
40
20
ID
15
35
30
1
10
I DQ [mA]
• Pout largely independent of IDQ
– Strong self-biasing: IDQ 10x Æ ID 1.3x
10
100
Pout [mW]
Peak PAE [%],ID [mA]
• Increase IDQ Æ class AB to A
Increasing Pout: Device Width
Pout ~ WG,TOT = NC x NF x WG,F
Peak PAE [%]
50
100
ideal
scaling
Peak PAE
40
80
30
60
20
40
Pout
10
20
Freq = 8 GHz
Vdd = 1V, Id = 26 mA/mm
W G,TOT = NC x64x12 µm
0
0
1
2
3
4
5
Number of Cells (NC)
6
Pout [mW]
•
0
7
Pout saturates
PAE drops!
Parasitics in Parallel Cells
• Low Vdd Æ High ID Æ High I-R drop in backend
– Layout wires do not scale with WG,TOT
Single Cell (W0)
Drain
Pad
Dual Cell (2W0)
Cell
metal
Cell
Drain
Pad
equivalent to
Cell
metal
Cell
metal
RG
relative to a single cell
metal
ΔRBEOL [Ohm-cell]
Cell
5
4
RS + RD
3
2
extracted
1
ideal scaling
0
Drain
Pad
0
1
2
3
4
Number of Cells
5
6
7
Modeling Parallel Cell Behavior
Increasing RBEOL Æ dissipate power Æ Pout ↓ for PDC=const Æ PAE ↓
Peak PAE [%]
50
200
ideal
ideal
40
150
30
Pout [mW]
•
0.5x
20
ΔRBEOL,meas
0.5x
100
50
10
ΔRBEOL,meas
0
0
0
2
4
6
8
10
12
0
Total Device Width [mm]
•
Simple loss model: behavior matches data
– PAE drops with number of cells
– Pout saturates and eventually decreases
2
4
6
8
10
Total Device Width [mm]
12
Outline
•
•
•
•
•
•
Why 65 nm CMOS for RF Power
Performance of Standard 65 nm Devices
Output Power Scaling
Optimizing Device Layout
Comparison with 90 nm and 0.25 µm
Conclusions
Maximizing 65 nm Performance
fmax [GHz]
60
40
20
1xNF xW G,F = 768 µm
Vdd=1V, Vg=0.6 V
0
1
10
Unit Finger Width (WG,F) [µm]
100
• Wide fingers Æ Parasitic RG losses
• Many narrow fingers Æ Distributed effect losses
fmax [GHz], NF , WG,F [µm]
Maximizing 65 nm Performance:
Power Cell Sizing
60
WG,TOT = 768 µm
Vdd=1V, Vg=0.6V
NF/ WG,F = 4
fmax
50
40
30
NF
20
1 cell
N cells
W G,F
10
0
1
10
100
1000
Number of Cells (NC )
• Optimal unit cell size (NF x WG,F)
• Layout critical for optimizing fmax Æ PAE
Maximizing Performance
• Pout: Source/Drain Metallization
– Must RBEOL scale with 1/ WG,TOT
• Wider and stacked metal lines
• Use of thicker high level layers
• PAE: Multi-cell approach (NC)
– RG Æ Limit WG,F
– Distributed effects Æ Limit NF
Al pad
two 6x
three 2x
five 1x
IBM 90 nm Server CMOS Technology
From: IBM Photo Catalog (online)
Outline
•
•
•
•
•
•
Why 65 nm CMOS for RF Power
Performance of Standard 65 nm Devices
Output Power Scaling
Optimizing Device Layout
Comparison with 90 nm and 0.25 µm
Conclusions
fmax Performance: 65 and 90 nm
60
fmax [GHz]
standard cell
devices
40
90 nm
20
1xNFxWG,F = 768 µm
65nm: V dd=1V, V g=0.6 V
90nm: V dd=1V, V g=0.75 V
0
1
10
65 nm
100
Unit Finger Width (WG,F) [µm]
• Comparable fmax performance of 65 nm and 90 nm
• LG ↓ Æ optimum WG,F ↓
Performance Similar Across Frequency
Pout
15
65 nm
Peak PAE [%]
80
90 nm
10
60
40
90 nm
5
PAE
20
90nm: 1x48x16µm
65nm: 1x64x12µm
V dd=1V, Id = 26 mA/mm
0
0
5
Output Power [dBm]
100
65 nm
0
10
15
20
Frequency [GHz]
• Standard Cell: Similar Pout and PAE behavior
Performance Similar Across Vdd
Lg=65nm
Lg=90nm, Thin Ox
Lg=250nm, Thick Ox
L 90
Thi O
Peak PAE [%]
60
30
25
PAE
50
20
40
30
Pout
15
Id = 26 mA/mm
freq = 8 GHz
All devices are single cell
10
20
10
0
0.1
1.0
Vdd [V]
Output Power Density
[dBm at 1 mm]
70
5
10.0
• Similar Pout and PAE behavior for all three technologies
• Intrinsic devices: similar performance (freq, Vdd)
Performance Differs Across WG,TOT
60
120
Peak PAE [%]
50
100
40
80
90 nm
30
60
Pout
20
40
65 nm
10
Vdd
0
0
W G,TOT 65 nm = NC x64x12 µm
Freq = 8 GHz
= 1V, Id = 26 mA/mm W G,TOT 90 nm = NC x48x16 µm
1
2
3
4
5
6
7
8
Pout [mW]
freq = 2 GHz
Peak PAE
20
0
9
Number of Cells (NC)
65 nm: Pout saturates
90 nm: Pout increases
Conclusions
• 65 nm device
– Similar voltage and freq. performance across 65, 90 nm and 0.25 µm
– 4 GHz: 66% PAE, Pout = 31 mW/mm
– 8 GHz: 54% PAE
• 65 nm BEOL: impact on WG,TOT scaling
– Currently: power saturates
– BEOL critical for performance
• Solutions
– Use layout to reduce RBEOL
– Stacked metal lines
– Use thick top level metal