CS220: Introduction to Computer Organization
Lab #1
Seven Segment Decoder
04 August 2011
1
Introduction
A seven-segment display is a form of an electronic display device for displaying decimal or
hexadecimal numerals. Seven-segment displays are widely used in digital clocks, electronic
meters and other electronic devices for displaying numerical information.
2
Concept
As indicated by the name, a seven-segment display is composed of seven display elements.
Controllable individually, they combine visually to produce simplified representations of the
numeric alphabet.
The seven segments are arranged as a rectangle, with two segments on each side, one on the
top and bottom each, and the last one bisecting the rectangle horizontally at the middle.
The segments are referred to by the letters A to G as shown in the figure, where an optional
DP decimal point (also sometimes referred to as the eight segment) is used for the display of
non-integer numbers.
Figure 1: The individual segments of a seven-segment display.
Figure 2: 7-segment display showing the 16 hexadecimal digits.
1
3
Implementation
Seven-segment displays may use a liquid crystal display (LCD) or arrays of light-emitting diodes
(LEDs). In a simple LED package, which is the type of display that we will be working with,
typically all of the cathodes (negative terminals) or all of the anodes (positive terminals) of the
segments are connected together and brought out to a common pin; these devices are referred
to as ’common cathode’ or ’common anode’ devices respectively. The other terminals are used
to control the segments via a seven-segment decoder.
A seven-segment decoder receives a 4-bit number and displays the alphanumeric representation of that number (0, 1, 2, A, etc.) on a seven-segment display. The outputs of the decoder are
labeled from A to G, which connect directly to the corresponding pins of the display. The decoder design depends on whether the display is a ’common anode’ device or a ’common cathode’
device.
4
Decoder Design
In this lab, we will design a seven-segment decoder, assuming a ’common anode’ device, and
implement it on an FPGA using BSV (Bluespec Verilog). Design for ’common cathode’ device
can be implemented in a similar manner.
A segment on a ’common anode’ device is visible when the input at its cathode is 0. Using
this information, and knowing the inputs for which a segment must be visible, we can determine
the truth table for a particular segment by assigning a value 0 to those inputs for which the
segment must be visible. The final truth table is given in Table 1.
I3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
I2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
I1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
I0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A
0
1
0
0
1
0
0
0
0
0
0
1
0
1
0
0
B
0
0
0
0
0
1
1
0
0
0
0
1
1
0
1
1
C
0
0
1
0
0
0
0
0
0
0
0
0
1
0
1
1
D
0
1
0
0
1
0
0
1
0
0
1
0
0
0
0
1
E
0
1
0
1
1
1
0
1
0
1
0
0
0
0
0
0
F
0
1
1
1
0
0
0
1
0
0
0
0
0
1
0
0
G
1
1
0
0
0
0
0
1
0
0
0
0
1
0
0
0
Table 1: Truth table of a seven segment decoder for a ’common anode’ device
I3 , I2 , I1 and I0 denote the 4-bit binary input, with I3 being the most significant bit.
From Table 1, one can write expressions for A to G in terms of the inputs I3 , I2 , I1 and I0 .
The details of this are left to the reader as an exercise, and the final expressions are given below:
A = I¯3 .I¯2 .I¯1 .I0 + I¯3 .I2 .I¯1 .I¯0 + I3 .I¯2 .I1 .I0 + I3 .I2 .I¯1 .I0
B = I¯3 .I2 .I¯1 .I0 + I¯3 .I2 .I1 .I¯0 + I3 .I¯2 .I1 .I0 + I3 .I2 .I¯1 .I¯0 + I3 .I2 .I1
2
C = I¯3 .I¯2 .I1 .I¯0 + I3 .I2 .I¯1 .I¯0 + I3 .I2 .I1
D = I¯3 .I¯2 .I¯1 .I0 + I¯3 .I2 .I¯1 .I¯0 + I¯3 .I2 .I1 .I0 + I3 .I¯2 .I1 .I¯0 + I3 .I2 .I1 .I0
E = I¯3 .I¯2 .I¯1 .I0 + I¯3 .I¯2 .I1 .I0 + I¯3 .I2 .I¯1 + I¯3 .I2 .I1 .I0 + I3 .I¯2 .I¯1 .I0
F = I¯3 .I¯2 .I¯1 .I0 + I¯3 .I¯2 .I1 + I¯3 .I2 .I1 .I0 + I3 .I2 .I¯1 .I0
G = I¯3 .I¯2 .I¯1 + I¯3 .I2 .I1 .I0 + I3 .I2 .I¯1 .I¯0
5
Exercises
(BSV1) Write BSV module to convert an input hexadecimal number to the seven segement pin
assignments. Write a testbench to test your module.
(FPGA1) Use the module designed above to display an input hexadecimal number on an LED 7
segment display of the FPGA board.
(BSV2) Design a 2-bit Unsigned Up Counter in BSV. (The counter must increment at every positive
edge of the clock.)
(FPGA2) Display the counter on LED 7 segment of the board. For this you may need to slow down
the clock.
(BSV3/FPGA3) Let XXXX, Y Y Y Y and ZZZZ denote the last 4 digits of the roll numbers of your group
members, such that
XXXX ≤ Y Y Y Y ≤ ZZZZ
(Is there a chance that last 4 digits are same for two or more partners ?)
Design a circuit that takes a two bit input and displays the following on the LED 7 segment
displays:
Input
00
01
10
11
7 Segment Displays
C220
XXXX
YYYY
ZZZZ
Use the module designed in Exercise [BSV1] to drive the LED displays.
(BSV4/FPGA4) [OPTIONAL] Connect the circuits designed in Exercise (BSV2/FPGA2) and Exercise
(BSV3/FPGA3) to automatically change the 7 segment displays. The display must keep
changing as:
...-> C220 -> XXXX -> YYYY -> ZZZZ -> C220 -> ...
3