Ruchit Mehta
2076 Birck Nanotechnology Center
West Lafayette, Indiana, USA 47907
Email: mehta20@purdue.edu
Tel: +1-919-534-5715
Education
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Purdue University, West Lafayette, USA
Doctor of Philosophy , Electrical & Computer Engineering
GPA : 4.00 / 4.00 (on plan of study)
(Aug '10 - present)
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Indian Institute of Technology, Bombay , India
Bachelor + Master of Technology in Electrical Engineering
Specialization : Microelectronics
CPI / GPA : 8.69 / 10 (Rank: 5/22)
(Aug '05 - Jun '10)
Research Experience
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Doctoral thesis research - Graphene device applications and Biomaterial interfaces
Advisor: Prof. Zhihong Chen
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(May '11 - present)
Process optimization for Chemical Vapor Deposition grown Graphene and material
characterization through SEM, Raman spectroscopy and XPS
Fabrication and characterization of nanoscale devices for biosensing and optics applications
Graphene based electrical detection of charged biospecies eg. bacteria, DNA
Interfacing biomolecules with gold nanoparticles and study conjugation properties
Master’s Thesis - Device Optimization of sub-20nm SOI-FinFETs with 3D-process TCAD
Advisor: Prof. Maryam Baghini
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(May '09 - Aug '10)
Implemented a novel 3D-process TCAD approach for simulating non-ideal doping profiles
Proposed an implant free process for doping extension regions for achieving conformal
doping profiles and abrupt junctions compared usual titled ion implantation process
Achieved reduction in simulation time over conventional approaches with optimized
simulation mesh to capture 3D parasitics and dynamic nature of source/drain resistances
Evaluated impact of hi-K spacer thickness, implant dose and energy conditions, RTA
anneal temperature and time on device performance
Publications
"Towards System on Chip (SoC) Development Using FinFET Technology: Challenges,
Solutions, Process Co-Development & Optimization Guidelines "
M. Shrivastava, R. Mehta, S. Gupta, N. Agrawal, M. Shojaei Baghini, D. K. Sharma, T. Schulz,
K. Arnim, W. Molzer, H. Gossner, V. Ramgopal Rao ; IEEE Transactions on Electron
Devices, June 2011 (feature article in Synopsys newsletter, May 2011)
Skills
Experimental - Work experience in class 1-10-100 cleanroom and BSL-2 labs, Optical and
Ebeam Lithography, Reactive ion etching, CVD growth and graphene transfer, Electron beam
deposition, Atomic Force Microscopy, Scanning Electron Microscopy, Cyclic voltammetry,
Electrical Characterization, Raman Spectroscopy, XPS, Ellipsometry
EDA Tools - Sentaurus TCAD, ISE TCAD, Mentor Graphics IC Studio, ModelSim, Hspice
Programming and Scripting - C/C++, Perl, Bash, Nvidia CUDA, MATLAB, HTML, CSS
Languages - English , Deutsch (level 1), Spanish(amateur)
Academic Projects
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Wallace tree multiplier design
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Implemented a custom low power 32-bit Wallace Tree Multiplier (from specification to
layout) using supply voltage scaling on TSMC 0.25um CMOS technology
Demonstrated unbalanced pipelining in an optimized pipelined structure for low power
application using voltage over-scaling. Design was completed in Cadence Virtuoso
environment
Technology-circuit interaction in Multi-gate MOSFETs for Analog and Mixed signal
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Reviewed feasibility of Multi-gate MOSFETs (MuGFETs) as possible successor of planar
bulk CMOS for future downscaling in sub-45nm regime
Identified trade-offs between short channel performance and speed/density and impact of
process variablity on circuit perfomance
Analyzed benefits of Independently-driven gate topology for CMFB, Miller OTA and RF
Mixer implementations
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Electronic Design Lab - Personal GPS tracker and Fall detector
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Surveyed the biomedical health care market and developed an affordable device for fall
detection by integration of GPS, Bluetooth, and Accelerometer with Mobile SMS
Increased battery life to 30 hours by employing a customizable caching scheme for storing
GPS data and selecting low power consuming components
High Voltage 4H-SiC Schottky Diode
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Designed a High Voltage SiC Schottky rectifier on Sentaurus TCAD, with optimal tradeoffs between specific on-resistance and breakdown voltage
Studied effects of device termination on Forward and Reverse I-V characteristics. Analyzed
temperature dependence on breakdown
Work Experience
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Summer Intern, Wavelet Group Pvt. Ltd., India
(May '08 - Jul '08)
o Analyzed customer defined specifications, critically reviewed GPS-Pseudolite technology
and proposed top-down system decomposition for precision navigation
o Successfully implemented simulation of Signal acquisition, BPSK modulator and
Numerically Controlled oscillator and documented the complete system design
o Presented basic GPS concepts and detailed implementation approach to the team for
navigational accuracy within 1 meter
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Teaching Assistant, School of ECE, Purdue University
(Aug '10 - Dec '11)
Taught 2 undergraduate courses ECE305 and ECE201. Lab Instructor for ECE208
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Teaching Assistant, IIT Bombay
( Aug '09 - Apr '10)
Presented tutorials on usage of EDA tools, conducted vivas for the laboratory course "Modern
Electronic Design Techniques"
Relevant courses
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Graduate level : Quantum Phenomenon in Semiconductors, Integrated circuit fabrication lab,
Principles of Nanofabrication, Solid State devices, Scanning Electron Microscopy
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Undergraduate : Microelectronics Computation & Fabrication lab, Nanoelectronics, Electronic
Design Lab, Power Semiconductor devices, Numerical Computing techniques, CMOS Analog
Circuit design, Digital VLSI Design and Technology, Computer systems, hardware description
languages, solid state electronics, data structures and algorithms
Awards and Recognition
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Secured AIR(All India Rank) 269 in the Joint Entrance Examination (JEE2005) towards
admission in IITs, out of 300 thousand students appearing in India.
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Chosen among top 20 entries from across India at Elixir,Techfest‟09, for designing a biomedical
fall detector with GPS tracker
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Awarded the Best Conceptual Design Prize for the competition GRIP at Techfest „06; part of the
only freshmen team qualifying for the finals
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Secured State Rank 43 in the state of Maharashtra in the All India Engineering Entrance
Examination , out of over 400 thousand students.
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Placed within top 1% in the state in National Standard Examination in Chemistry, 2005
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1st place in “Prayog”, an intra-IIT technical event, for demonstration of “Analogy between
Economics and Electronics” using the phenomenon of hysteresis
References
 Prof. Zhihong Chen
Associate Professor, School of ECE, Purdue University, USA
Email: zhchen[at]purdue.edu
 Dr. Mayank Shrivastava
Senior Engineer, Intel Mobile Communications , Munich, Germany
Email: mayank.shrivastava[at]intel.com
 Prof. Maryam S. Baghini
Associate Professor, EE Department, IIT Bombay, INDIA
Email: mshojaei[at]ee.iitb.ac.in