Recent Researches in Circuits, Systems, Communications and Computers
Differential Difference Current Conveyor Based Cascadable Voltage
Mode First Order All Pass Filters
P.V.S. MURALI KRISHNA, NAVEEN KUMAR, AVIRENI SRINIVASULU†, R.K.LAL
Department of Electronics & Communication Engineering
†
Vignan University, Guntur-522 213
Birla Institute of Technology, Mesra-835 215
INDIA
†
avireni@ieee.org †http://www.vignanuniversity.org, http://www.bitmesra.ac.in
Abstract: - This paper proposes two first-order all-pass filters using DDCCs as active elements, one resistor and one
capacitor. Both proposed filters have two DDCCs, one grounded resistor and one grounded capacitor. Thus the two
topologies are having minimum number of components and there is no need for matching constraints on passive
components. The performance of the proposed circuits is examined using PSPICE simulations with the model
parameters of a 0.5 µm CMOS process. Obtained results demonstrate excellent agreement with theoretical values.
Keywords: - Current conveyor, CCII, DDA, DDCC, all-pass filter, SPICE
1 Introduction
Second generation current conveyor (CCII),
introduced in 1970 [1], has been a popular building
block in voltage-mode and current-mode analog
applications likes oscillators, various types of filters and
amplifiers, due to its high and versatile performance,
low power consumption, high bandwidth and high
output voltage swing. Many CCII applications were
available in the literature [2-13].
But CCII has a drawback. It has only one voltage
input terminal. Thus it is not suitable for applications
that use differential inputs or floating inputs. So, such
applications require two or more CCIIs. Differential
difference current conveyor (DDCC) is more suitable in
such applications. CMOS based DDCC was introduced
in 1996. DDCC encompasses the good features of
Differential difference amplifier (DDA) like high input
impedance, low output impedance, less number of
components and capability of performing arithmetic
operations, and advantages of CCII such as high gain,
accuracy and bandwidth. DDCC applications such as
realizing squarer, square rooter and multiplier circuits,
differential integrators, and voltage mode and current
mode low-pass filters and high-pass filters were also
demonstrated [14]. Later, many applications using
DDCC were presented [15-21].
All-pass filters of first-order are widely used in
analog signal processing applications for changing the
phase shift, where amplitude remain unchanged. They
are also used to construct quadrature and multiphase
oscillators. Recently many voltage-mode and currentmode all-pass filters were presented using CCII or
DDCC. Grounded passive components provide tuning
facility that is required in analog ICs after manufacture,
because of the problem of high tolerances. The
ISBN: 978-1-61804-056-5
frequency of oscillation can be adjusted by a grounded
resistor without disturbing the oscillation condition.
Grounded capacitors are easier for fabrication and have
less parasitics compared with floating capacitors [5-8],
[11-13], [18-27]. Here two new first order all-pass filters
are proposed using DDCCs as active elements.
The remaining sections of the paper are organized as
follows. The DDCC fundamentals and proposed design
are presented in section 2 and 3. Non-ideal analysis is
included in section 4. Finally, simulation results and
conclusions are given in section 5 and 6 respectively.
2 DDCC Fundamentals
The symbol of five-port DDCC is shown in Fig. 1.
The internal structure of this device is shown in Fig. 2
and it can be characterized by the following matrixrelations between various voltage and current variables
[20, 28].
 I Y 1  0
I  
 Y 2  0
 I Y 3  = 0
  
V X   β1
 I  0
 Z  
0
0
0
-β 2
0
0
0
β3
0
0
0
0
0
0
α
0 

0 
0 

0 
0  
VY 1 
VY 2 
VY 3 

IX 
V Z 
(1)
In the DDCC, Y1, Y2, and Y3 are three voltage input
terminals with high input impedance. Terminal X is a
low impedance current input terminal. There is a high
impedance current output terminal Z. The hybrid matrix
can be represented by the following equations:
I Y 1 = I Y 2 = I Y 3 = 0, V X = β 1VY 1 − β 2VY 2 + β 3VY 3 ,
128
and I Z = α I X
(2)
Recent Researches in Circuits, Systems, Communications and Computers
Here α represents the current tracking error from X to Z
terminal. β1, β2 and β3 represent the voltage tracking
errors from Y1, Y2, Y3 to X terminal. Ideally β1= β2 = β3
= α = 1. Actually these tracking errors arise due to
parasitic capacitance and resistance of the DDCC.
V Y1
IY1
Y2
Y1
IZ
IY2
V Y2
V Y3
It provides 00 to 1800 phase shift. Its phase response is
given by
(6)
φ (ω ) = − 2 tan −1 (ωCR )
DDCC
Y2
IY3
Y3
Vi
VZ
Z
Y2
Z
Z
C
Y1
DDCC1
DDCC2
Y3
Y3
X
X
Y1
X
R
IX
V0
VX
Fig. 3 Proposed all-pass filter 1
Fig. 1 Symbol for DDCC
Vdd
M7
M8
Y2
M11
M9
Vi
Y1
Z
Z
C
Y1
DDCC1
DDCC2
Y3
Y3
Y2
M1
M2
Y3 Y1
M4
M5
X
V0
Fig. 4 Proposed all-pass filter 2
Vb
Vss
Y2
R
Z
X
X
M6
M3
M10
M12
4 Non-Ideal Analysis
Fig. 2 Device level presentation of DDCC
3 Proposed Design
The first proposed filter is shown in Fig. 3. In this
topology, DDCC1 outport Z is fed to the input port Y2 of
DDCC2 with a grounded capacitor C. And also, DDCC1
terminal X is fed to the input port Y1 of DDCC2 with a
grounded resistor R. The voltage transfer function is
given by
Vo ( s) sCR − 1
(3)
=
Vi ( s) sCR + 1
It provides 1800 to 00 phase shift. And the phase
response is given by
(4)
φ (ω ) = 180 0 − 2 tan −1 (ω CR )
The second proposed filter is shown in Fig. 4. In this
topology, DDCC1 outport Z is fed to the input port Y1 of
DDCC2 with a grounded capacitor C. And also, DDCC1
terminal X is fed to the input port Y2 of DDCC2 with a
grounded resistor R. The voltage transfer function is
given by
Vo ( s ) 1 − sCR
(5)
=
Vi ( s ) 1 + sCR
ISBN: 978-1-61804-056-5
So far, ideal characteristics for the DDCC are being
considered in the analysis. However, in this section of
investigation, the analysis could change if the
parameters of non-idealities are taken for granted.
From Fig. 3, we can write voltage transfer function as
V o ( s ) β 11 ( β 21 sCR − α 1 β 22 )
(7)
=
Vi ( s )
sCR + α 1 β 12
and phase response as
β ωCR
ωCR
(8)
φ (ω ) =180 0 − tan −1 21
− tan −1
α 1 β 22
α 1 β 12
From Fig. 4, we can write voltage transfer function as
Vo ( s ) β 11 (α 1 β 21 − β 22 sCR )
=
(9)
Vi ( s )
α 1 β 12 + sCR
and the phase response as
β ωCR
ωCR
φ (ω ) = − tan −1 22
− tan −1
(10)
α 1 β 21
α 1 β 12
Effects of non-ideality on pole frequency:
Ideally, from Eqs. (3) and (5), we can observe that the
pole/zero frequency will be ω p / z = 1 RC and its
sensitivity due to passive element is S Rω,PC/ Z = 1 . From
129
Recent Researches in Circuits, Systems, Communications and Computers
Eqs. (7) and (9) we can observe that the pole frequency
is different from the zero frequency and it is given by the
following characteristic equations.
For Fig. 3, ω P = α 1 β 12 RC , ω Z = α 1 β 22 β 21 RC and
For Fig. 4, ω P = α 1 β 12 RC , ω Z = α 1 β 21 β 22 RC
After completion of analysis we found that the
sensitivity of pole or zero frequency due to DDCC is not
more than unity. The sensitivities for Fig. 3 are given by
S αω1P, β12 = 1
S αω1zβ 21β 22 = 1
MODEL PT PMOS LEVEL=3
+UO=100 TOX=1.0E-8 TPG=1 VTO=-.58 JS=3.8E6+XJ=.1E-6 RS=886 RSH=1.81
LD=0.03EETA=0+VMAX=115E3 NSUB=2.08E17
PB=.911PHI=0.905+THETA=0.120 GAMMA=0.76
KAPPA=2 AF=1+WD=.14E-6 CJ=85E-5 MJ=0.429
CJSW=4.67E-10 +MJSW=0.631 CGSO=1.38E-10
(11)
CGDO=1.38E-10+CGBO=3.45E-10 KF=1.08E-29
(12)
DELTA=0.81 +NFS=0.52E11
and for Fig. 4, they are denoted by
S αω1Pβ1 = 1
2
S αω1zβ 2 β 22
1
(13)
TABLE II. TRANSISTORS ASPECT
RATIOS
=1
(14)
In comparison with the published all pass filter, this
filter can have additional transfer function,
Vo ( s)
1 − sCR
=2
(15)
Vi ( s )
1 + sCR
i.e., this filter is also capable of producing amplified
output by connecting the Y3 terminal to Y1.
TRANSISTOR
M1, M2, M4, M5
5 Simulation Results
The proposed all-pass filters were simulated using
PSPICE with 0.5 µm MITECH parameters. The
parameters are given in table I and the aspect ratios of
transistors are given in table II.
The supply voltages of proposed all-pass filter circuits
are +2.5 V and the biasing voltage VB is -1.7 V. The
simulation results of all-pass network shown in Fig. 3
are given in Fig. 5 and Fig. 6 and those of all-pass
network shown in Fig. 4 are given in Fig. 7 and Fig. 8.
The passive component values selected are R=10 kΩ, C
= 100 pF and the pole frequency f 0 = 159 KHz.
TABLE I
0.5 µm MIETEC CMOS PROCESS MODEL PARAMETERS;
LEVEL-3
MODEL NT NMOS LEVEL=3
+UO=460.5 TOX=1.0E-8 TPG=1 VTO=.62 JS=1.8E6+XJ=.15E-6 RS=417 RSH=2.73 LD=0.
ETA=0+VMAX=130E3 NSUB=1.71E17 PB=.761
PHI=0.905+THETA=0.129 GAMMA=0.69
W (µm) L (µm)
0.8
0.5
M3, M6
14.4
0.5
M7, M8
4.0
0.5
M9, M11
10.0
0.5
M10, M12
45.0
0.5
6 Conclusion
In this paper, two new voltage-mode first-order allpass networks employing two DDCCs, one grounded
resistor, another grounded capacitor are presented. Both
use optimum and canonical number of passive
components. So there is no need for passive component
matching. No capacitors are connected at X terminal.
We found that Total Harmonic Distortion (THD) of both
circuits is less than 4%. However its value is decreasing
for first proposed circuit with increasing frequency and
it is less than 2%. Both the circuits have grounded
resistor and grounded capacitor, which provide the
tunable property. The circuits are verified using SPICE
simulation and the simulated results agreed with
theoretical ones. These are alternative better circuits than
the ones present in [15], and have added advantages of
parasitic resistances and capacitances that can be
minimal. The circuit presented in [18], provides only
low output impedance. And circuits presented in [5-7]
uses the floating passive element and have element
matching restrictions.
KAPPA=0.1 AF=1+WD=.11E-6 CJ=76.4E-5
MJ=0.357CJSW=5.68E-10+MJSW=0.302
CGSO=1.38E-10 CGDO=1.38E-10+CGBO=3.45E-10
KF=3.07E-29 DELTA=0.42+NFS=1.2E11
ISBN: 978-1-61804-056-5
References
[1] A. S. Sedra and K. C. Smith, “A second generation
current conveyor and its application,” IEEE Trans.
130
Recent Researches in Circuits, Systems, Communications and Computers
Circuit Theory, Vol. CT-17, No. 1, pp. 132-134,
Feb. 1970.
[2] A. Srinivasulu, “A novel current conveyor-based
Schmitt trigger and its application as a relaxation
oscillator,” Int. J. Circuit Theo. and Appl. Vol. 39,
No. 6, pp. 679-686, June 2011.
[3] D. Pal, A. Srinivasulu, B. B. Pal, A. Demosthenous,
and B. N. Das, “Current conveyor based
square/triangular–waveform
generators
with
improved linearity,” IEEE Trans. Instr. and
Measur., Vol. 58, No. 7, pp. 2174-2180, 2009.
[4] D. Pal, A. Srinivasulu and M. Goswami, “Novel
current-mode waveform generator with independent
frequency and amplitude control,” Proc. IEEE Int.
Symp. Circuits and Systems, pp.2946-2949, May.
2009.
[5] I. A. Khan and S. Maheshwari, “Simple first order
all-pass filters using a single CCII,” Int. J. Electron,
Vol. 87, No. 3, pp. 303-306, 2000.
[6] N. Pandey and S. K. Paul, “All-pass filters based on
CCII- and CCCII-,” Int. J. Electron., Vol. 91, No. 8,
pp. 485-489, 2004.
[7] O. Cicekoglu, H. Kuntman and S. Berk, “All-pass
filters using a single current conveyor,” Int. J.
Electron., Vol. 86, No. 8, pp. 947-955, 1999.
[8] J. W. Horng, “Current conveyor based all-pass
filters and quadrature oscillators employing
grounded capacitors and resistors,” Comp. and
Electri. Engi. Vol. 31, pp. 81-92, 2005.
[9] P. Kumar, A. U. Keskin and K. Pal, “Wide-band
resistorless all-pass sections with single element
tuning,” Int. J. Electron., Vol. 94, No. 6, pp. 597604, 2007.
[10] S. Minaei and O. Cicekoglu, “A resistorless
realization of the first-order all-pass filter,” Int. J.
Electron., Vol. 93, No. 3, pp. 177-183, 2006.
[11] J. W. Horng, C. L. Hou, C-M. Chang, W-Y. Chung,
H-L. Liu and C-T. Lin, “High output impedance
current-mode first-order all-pass networks with four
grounded components and two CCIIs,” Int. J.
Electron., Vol. 93, No. 9, pp. 613-621, 2006.
[12] R.I. Salawu, “Realization of an all-pass transfer
function using the second-generation current
conveyor,” Proc, IEEE, 68, 183-184, Jan. 1980.
[13] I. A. Khan and S. Maheshwari, “Simple first order
all-pass filters using a single CCII,” Int. J. Electron.,
Vol. 87, No. 3, pp. 303-306, 2000.
[14] W. Chiu, S.I. Liu, H.W. Tsao and J.J. Chen,
“CMOS differential difference current conveyors
and their applications,” IEE Proc. Circuits Dev.
Syst, 143(2), pp. 91-96, 1996.
[15] M. Kumngern and K. Dejhan, “High input lowoutput impedance voltage-mode allpass networks,”
Proc. Integrated Circuits, ISIC, pp.381-384, 2009.
ISBN: 978-1-61804-056-5
[16] S.S. Gupta and R. Senani, “Comments on CMOS
differential difference current conveyors and their
applications,” IEE Proc. Circuits Dev. Syst. 148(6),
pp. 335-336, 2001.
[17] M. A. Ibrahim, H. Kuntman and O. Cicekoglu,
“First-order all-pass filter canonical in number of
resistors and capacitors employing a single
DDCC,” Circuit, Syst. Signal Proce. J. Vol. 22, No.
5, pp. 525-536, 2003.
[18] J-W. Horng, C.L. Hou, C.M. Chang, W.Y. Chung,
C.T. Lin, I.C. Shiu and W-Y. Chiu, “First-order allpass filter and sinusoidal oscillator using DDCCs,”
Int. J. Electron., Vol. 93, No. 7, pp. 457-466, 2006.
[19] M. A. Ibrahim, H. Kuntman and O. Cicekoglu, “A
very
high-frequency
CMOS
self-biasing
complementary
folded
cascade
differential
difference current conveyor with application
examples,” Circuit and System, Vol. 1, pp. 279-282,
2002.
[20] Metin Bilgin, O. Cicekoglu and K. Pal, “DDCC
based all-pass filters using minimum number of
passive elements,” Proc. IEEE MWSCAS/NEWCAS,
pp. 518-521, 2007.
[21] M. A. Ibrahim, H. Kuntman and O. Cicekoglu,
“First-order all-pass filter canonical in number of
resistors and capacitors employing a single
DDCC,” Circuit, Syst. Signal Proce. J. Vol. 22, No.
5, pp. 525-536, 2003.
[22] M.T. Ahmed, I.A. Khan and N. Minhaj, “On
transconductance-C quadrature oscillators,” Int. J.
Electron., Vol. 83, pp. 201-207, 1997.
[23] S.J.G. Gift, “The application of all-pass filters in
the design of multiphase sinusoidal systems,”
Microelectron. J., Vol. 31, pp. 9-13, 2000.
[24] D.T. Comer, D.J. Comer and J.R. Gonzales, “A
high frequency integrable band pass filter
configuration,” IEEE Trans. Circuits. Syst. II:
Analog. Digital Signal Proc., Vol. 44, pp. 856-861,
1997.
[25] S. Maheshwari, “New voltage and current mode allpass filter using a current controlled conveyor, Int.
J. Electron., Vol. 91, pp. 735-743, 2004.
[26] M. A. Ibrahim, S. Minaei and H. Kuntman, “DVCC
based differential mode all-pass and notch filters
with high CMRR,” Int. J. Electron., Vol. 93, pp.
231-240, 2006.
[27] S. Minaei and M. A. Ibrahim, “General
configuration for realizing current mode first-order
all-pass filter using DVCC,” Int. J. Electron., Vol.
92, pp. 347-356, 2005.
[28] R.J. Baker, H.W. Li and D.E. Boyce, CMOS
Circuit Design, Layout and Simulation, Chapter 7,
IEEE Press, New York, 1998.
131
Recent Researches in Circuits, Systems, Communications and Computers
Fig. 5 Phase and magnitude plots of the proposed circuit of Fig. 3
Fig. 6 Dependence of output voltage harmonic distortion on input voltage frequency for 0.2 VPP of Fig. 3
Fig. 7 Phase and magnitude plots of the proposed circuit of Fig. 4
Fig. 8 Dependence of output voltage harmonic distortion on input voltage frequency for 0.2 VPP of Fig. 4
ISBN: 978-1-61804-056-5
132