A D S A N T E C
A d v a n c e d
S c ie n c e
a n d
N o v e l
T e c h n o lo g y
27 Via Porto Grande, Rancho Palos Verdes, CA, 90275.
Ph. # 1-310-377-6029.
Fax # 1-310-377-9940.
ASNT1011
12.5Gbps Digital 16:1 Serializer
•
•
•
•
•
•
•
•
•
•
Broadband up to 12.5Gbps (gigabits per second) 16:1 Serializer.
LVDS-compatible Input Data Buffer.
Full-rate CML Input Clock Buffer with a 50Ohm on-chip single-ended termination to VCC.
CML Output Data Buffer for a 50Ohm external single-ended termination to VCC.
Selectable Clock Output Buffer with CML interface.
Clock-divided-by-16 LVDS Output Buffer with 90º-step phase selection.
Single +3.3V power supply.
Industrial temperature range.
Low power consumption of 550mW at 12.5Gbps.
100-pin MLF package.
Rev.03;
December 2007.
1
ASNT1011
A D S A N T E C
A d v a n c e d
S c ie n c e
a n d
N o v e l
T e c h n o lo g y
27 Via Porto Grande, Rancho Palos Verdes, CA, 90275.
Ph. # 1-310-377-6029.
Fax # 1-310-377-9940.
DESCRIPTION
d00
d01
…
d15
LS
DATA IB
MUX
16:1
CML
OB
qcml
HS
CLOCK
OB
cho
offcho
C
phs1,2
ce
DIVIDER-BY-16
C16S
HS
CLOCK
IB
LVDS
CLOCK
OB
clo
ASNT1011 is a digital broadband 16:1 serializer supporting a differential serial output interface
that can handle data rates from DC up to 12.5Gbps. The primary application of ASNT1011 is to
provide a high-speed output data channel for point-to-point data transmission over a controlledimpedance media of 50Ohm. The transmission media can be a printed circuit board or copper
coaxial cables. The functional distance of the data transfer is dependent upon the attenuation
characteristics of the transportation media and the degree of noise coupling to the signaling
environment.
During normal operation, the serializer’s low-speed input buffer (LS DATA IB) accepts external
16-bit wide parallel data words (“d00”-“d15”) through 16 differential inputs. The multiplexer
(MUX16:1) then latches the data words using a low-speed clock with a frequency of 1/16 of the
data rate, that is generated by an internal divider (DIVIDER-BY-16) from an external full-rate
clock (“ce”). The parallel input words are then serialized and transmitted by a differential CML
output buffer (CML OB) as a high-speed signal (“qcml”).
The low-speed clock generated by the divider is supplied both to the multiplexer (MUX16:1) and
to a low power LVDS output buffer (LVDS CLOCK OB). 4 different phases of the second clock
signal (C16S) can be selected in order to help facilitate system synchronization. A high-speed
clock output buffer (HS CLOCK OB) is included to transmit the serializer’s full rate (C) clock as
the “cho” signal.
The serializer uses a single +3.3V power supply and is characterized for operation from −25°C to
125°C of junction temperature.
Rev.03;
December 2007.
2
ASNT1011
A D S A N T E C
A d v a n c e d
S c ie n c e
a n d
N o v e l
T e c h n o lo g y
27 Via Porto Grande, Rancho Palos Verdes, CA, 90275.
Ph. # 1-310-377-6029.
Fax # 1-310-377-9940.
LS DATA IB
The Low-Speed Data Input Buffer (LS DATA IB) consists of 16 proprietary Universal Input
Buffers. The proprietary Universal Input Buffer (UIB) is designed to accept differential signals
with amplitudes higher than 60mV, DC common mode voltage variation between the negative
and positive supply voltages, and AC common mode noise with a frequency up to 5MHz and
voltage levels ranging from 0 to 2.4V. It can also receive single-ended signals with amplitudes of
more than 60mV and threshold voltages between the negative and positive supply rails. The
buffer outputs standard internal CML signals with amplitude of 220mV.
HS CLOCK IB
The High-Speed CML Clock Input Buffer (HS CLOCK IB) accepts differential signals with
frequencies up to12.5GHz. It can also accept a single-ended signal with a threshold voltage
applied to the “cen” pin. The buffer utilizes on-chip single-ended termination of 50Ohm to the
positive supply rail for each input line.
DIVIDER-BY-16
DIVIDER-BY-16 includes 4 divide-by-2 circuits connected in series. The high-speed input clock
C is fed into the first divide-by-2 circuit that generates an output clock signal (C2) that is half the
rate of the input clock. C2 is routed internally to the next divide-by-two circuit and outside of the
block to MUX16:1. C4, C8, and C16 are formed and routed to MUX16:1 in a similar way.
In addition, C16 is passed onto the LVDS Clock Output Buffer (LVDS CLOCK OB) as the
C16S signal. By utilizing the CMOS control pins “phs1” and “phs2”, the phase of C16S can be
altered in accordance with the table below.
“phs1”
“phs2”
C16S phase
VEE (default) VEE (default)
270°
VEE
VCC
180°
VCC
VEE
90°
VCC
VCC
0°
MUX 16:1
MUX16:1 utilizes standard tree-type architecture and latches the incoming data on the negative
edge of the C16 clock signal that is supplied by DIVIDER-BY-16. The 16-bit wide data word is
subsequently multiplexed by the tree structure using the C8, C4, and C2 clock signals and is
delivered to the high-speed CML Output Buffer (CML OB) as a serial data stream running at a
data rate up to 12.5Gbps. The latency of this circuit block is equal to roughly one period of the
low-speed input clock.
HS DATA OB
HS DATA OB accepts high-speed data from MUX16:1 and converts it into the output CML
signal “qcml” with a single-ended swing not less than 600mV and data rate up to 12.5Gbps. For
Rev.03;
December 2007.
3
ASNT1011
A D S A N T E C
A d v a n c e d
S c ie n c e
a n d
N o v e l
T e c h n o lo g y
27 Via Porto Grande, Rancho Palos Verdes, CA, 90275.
Ph. # 1-310-377-6029.
Fax # 1-310-377-9940.
normal operation, the buffer requires external 50Ohm termination resistors to be connected
between the positive supply rail “vcc” and each output.
HS CLOCK OB
The selectable HS CLOCK OB can be enabled or disabled by the external CMOS control signal
“offcho”. The logic “0” default state corresponds to an operational buffer. The buffer utilizes the
same termination scheme as HS DATA OB and can operate at a frequency up to 12.5GHz while
producing a single-ended CML output swing of 500mV.
LS LVDS CLOCK OB
The LVDS Clock Output Buffer (LVDS CLOCK OB) receives the C16S signal from DIVIDERBY-16 and converts it into an LVDS output signal.
The proprietary low-power LVDS output buffer utilizes NPN HBTs that are common to standard
BiCMOS technologies. It utilizes a special architecture that ensures operation at frequencies up
to 2GHz with a low power consumption level of 30mW. The buffer satisfies all the requirements
of the IEEE Std. 1596.3-1996 and ANSI/TIA/EIA-644-1995.
TERMINAL FUNCTIONS
DESCRIPTION
TERMINAL
Name
No.
Type
chop
chon
qcmlp
qcmln
offcho
phs1
phs2
vcc
vee
nc
Rev.03;
High-Speed I/Os
37 Output CML differential high-speed clock outputs. Require external
SE 50Ohm termination to “vcc”. Can be disabled by
36
“offcho”.
43 Output CML differential high-speed data outputs. Require external
SE 50Ohm termination to “vcc”.
42
Control Signals
28
LS
High-speed clock output disable (active: high, default: low).
CMOS
57
LS
Low-speed output clock phase selection (default: both low).
CMOS
56
Supply and Termination Voltages
many
PS
Positive power supply
many
PS
Negative power supply (Ground node)
many
Unconnected pin.
December 2007.
4
ASNT1011
A D S A N T E C
A d v a n c e d
S c ie n c e
a n d
N o v e l
T e c h n o lo g y
27 Via Porto Grande, Rancho Palos Verdes, CA, 90275.
Ph. # 1-310-377-6029.
Fax # 1-310-377-9940.
DESCRIPTION
TERMINAL
Name
No.
Type
Low-Speed I/Os
cep
cen
clop
clon
d00p
d00n
d01p
d01n
d02p
d02n
d03p
d03n
d04p
d04n
d05p
d05n
d06p
d06n
d07p
d07n
d08p
d08n
d09p
d09n
d10p
d10n
d11p
d11n
d12p
d12n
d13p
d13n
d14p
d14n
d15p
d15n
Rev.03;
31 Input CML differential high-speed clock inputs with internal SE
50Ohm termination to “vcc”.
30
48 Output LVDS low-speed clock outputs. Can transmit four different
clock phases as defined by “phs1” and “phs2” signals.
47
61 Input
62
64
65
67
68
70
71
76
77
79
80
82
83
85
86
Universal low-speed data inputs with LVDS internal
88
termination.
89
90
91
93
94
96
97
99
100
5
6
8
9
11
12
December 2007.
5
ASNT1011
A D S A N T E C
A d v a n c e d
S c ie n c e
a n d
N o v e l
T e c h n o lo g y
27 Via Porto Grande, Rancho Palos Verdes, CA, 90275.
Ph. # 1-310-377-6029.
Fax # 1-310-377-9940.
ELECTRICAL CHARACTERISTICS
PARAMETER
MIN
TYP
MAX
UNIT
COMMENTS
V
V
mW
°C
±5%
General Parameters
VCC
VEE
Power consumption
Junction temperature
3.14
Data Rate
Logic “1” level
0.0
-25
3.3
0.0
550
50
3.47
125
LS Input Data (d00-d15)
800
VCC
Logic “0” level
VCC-0.25
Mbps
V
V
Same for all types
of valid input data
Same for all types
of valid input data
HS Input Clock (ce)
Frequency
Logic “1” level
Logic “0” level
Duty Cycle
0.0
12.5
VCC
40%
VCC-0.4
60%
50%
GHz
V
V
HS Output Data (qcml)
Data Rate
Logic “1” level
Logic “0” level
Jitter
0.0
12.5
VCC
VCC-0.5
15
Gbps
V
V
pS
p-p @ 12.4Gb/s
GHz
V
V
ps
p-p
HS Output Clock (cho)
Frequency
Logic “1” level
Logic “0” level
Jitter
Duty Cycle
0.0
12.5
VCC
45%
VCC-0.5
14
50%
55%
LS Output Clock (clo)
Frequency
Interface
0.0
800
MHz
LVDS
Meets the IEEE Std.
1596.3-1996
CMOS Control Inputs
Logic “1” level
Logic “0” level
VCC-0.4
VEE+0.4
V
V
Timing Parameters
“cho” to “qcml” delay
variation
Rev.03;
December 2007.
±2.5%
6
Over the full
temperature range
ASNT1011