Complementary Metal Oxide Semiconductor
(CMOS) Static Random Access Memory
(SRAM) Cells and Basics of Metal Oxide
Semiconductor Current Mode Logic (MCML)
Technology
APURVA.Y.RANA1, DR. KIRITKUMAR.R.BHATT2
PG STUDENT1, ASSOCIATE PROFFESOR2
(SARDAR VALLABHBHAI PATEL INSTITUTE OF TECHNOLOGY, VASAD, GUJARAT)
(MOS) arranged to form a bi-stable element. They are
ABSTRACT
This paper represents what is SRAM and how to work 6T
and 8T SRAM cell in read and write operationand basics of
MCML technology. Also represent the MCML advantages
and disadvantages over CMOS logic.
characterized by a very low access time making them the
fastest memory technology employed whenever high
speed
is
required
(e.g.,
microprocessors,
mobile
application)
SRAM cell consist of latch, therefore, the cell data is kept as
long as the power is turned on and refresh operation is not
INTRODUCTION OF SRAM MEMORY
required this disadvantage of DRAM so DRAM is replaced
Recent generation is calculate time for do anything
and CPU and advantage of low cost and high density,
because time is money. According to that purpose static
DRAM is used as main memory[4].
random access memory (SRAM) is better as cache memory
1. TYPESOF SRAM CELL:
by the SRAM as cache memory ,interfacing between DRAM
in computer and mobile application .now a day in SRAM
low power as well as high speed also important
The SRAM cells are categorized based on the type of load
parameter.
used in the elementary inverter of the flip-flop cell. There
are commonly three types of SRAM memory cells:
The semiconductor memory arrays capable of storing
quantities of digital information are essential to all digital
system. The semiconductor memory is generally classified
according to the type of data storage and data access. Read
or write in the memory array, as well as retrieval on
demand. The read or write is commonly called random
access memory. There is two volatile memory (1) SRAM
(2) DRAM. [10]
1.1 4T cell (four NMOS transistors plus two poly load
resistors)
1.2 6T cell (six transistors-four NMOS transistors plus two
PMOS transistors)
1.3 TFT cell (four NMOS transistors plus two loads called
TFTs)
1.1 4T (Four Transistor) cell:
In this design consists of four NMOS transistors plus two
SRAM are memories based on storage elements usually
poly-load resistors. Two NMOS transistors are work as
realized with 6 metal-oxide semiconductor transistors
pass-transistors. These transistors have their gates
connected to the word line and connected the cell to the
© 2014, IJOURNALS All Rights Reserved
Page 87
columns. The two other NMOS transistors are the pull-
as in the 6T cell architecture. The oxide between this
downs of the flip-flop inverters. The loads of the inverters
control gate and the TFT polysilicon channel must be thin
consist of a very high poly-silicon resistor. The cell needs
enough to ensure the effectiveness of the transistor. The
room only for the four NMOS transistors. The poly loads
performance of the TFT PMOS transistor is not as good as
are stacked above these transistors. Although the 4T
a standard PMOS silicon transistor used in a 6T cell.
SRAM cell may be smaller than the 6T cell, it is still four
times larger than the cell of a DRAM cell. [4]
Figure: 2 Thin Film Transistor (TFT) SRAM cell
The disadvantage of TFT cell is its complex technology
Figure: 1 (4 Transistor - SRAM cell)
compared to the 4T cell technology and poor TFT
The complexity of the 4T cell is to make a resistor load
electrical characteristics compared to a PMOS transistor.
high enough (in the range of giga-ohms) to minimize the
current. However, this resistor must not be too high to
1.36T (Six Transistor) cell
guarantee good functionality. Despite its size advantage,
A different cell design that eliminates the above
the 4T cells have several limitations.
limitations is the use of a CMOS flip-flop. In this case, the
1. Each cell has current flowing in one resistor. (i.e., the
load is replaced by a PMOS transistor. This SRAM cell is
SRAM has a high standby current)
composed of six transistors, one NMOS transistor and one
2. The cell is sensitive to noise and soft error because the
PMOS transistor for each inverter, plus two NMOS
resistance is so high.
transistors connected to the row line (as shown in figure).
3.
The cell is not as fast as the 6T cell.
1.2 TFT (Thin Film Transistor) cell
This configuration is called a 6T Cell. This cell offers better
electrical performances (speed, noise immunity, standby
current) than a 4T structure.
This new structure overcomes the current flow through
Tp1, Tn1, Tp2 and Tn2 implement the two inverters of the
the resistor load of the old 4T cell. This change in electrical
closed loop, an SRAM is internally organized as a matrix of
characteristics of the resistor load is done by controlling
cells. All cells in a column connected to a couple of lines
the channel of a transistor. This resistor is configured as a
called bit lines (BL and BL in Figure 2.4 and 2.5) through
PMOS transistor and is called a thin film transistor (TFT).
the two pass transistors Pn1 and Pn2. The connection of
It is formed by depositing several layers of polysilicon
above the silicon surface. The source/channel/ drain is
formed in the polysilicon load. The gate of this TFT is
polysilicon and is tied to the gate of the opposite inverter
© 2014, IJOURNALS All Rights Reserved
the cell to the bit lines is controlled by a signal named
word line connected to the gate of the two pass
transistors. All cells of a row are connected to the same
word line WL. The two stable states of the cell are
Page 88
expressed by the following relationships: S0 = {F¯ =T=
transistors Pn1 and Pn2. In this situation, the voltage
0∧T¯ = F = 1} andS1 = {F¯ = T = 1∧T¯ = F = 0}. The
values stored in T and F are transferred to the bit lines by
information is therefore stored in the cell in a differential
leaving BL at its pre-charged value and discharging
way. [7]
BL_BAR through Pn2 and Tn2 and VSS. On the BL side, the
transistors Tp1 and Pn1 pull the bit line toward VDD. If
the content of the memory was a logic 0 (T = 0), the
opposite would happen and BL would be pulled toward
VDD and BL toward VSS. In both situations BL and BL will
have a small voltage difference ΔV between them. A
dedicated circuit connected to the bit lines (sense
amplifier) will sense which line has higher voltage and
thus will tell whether the cell content is a logic 1 or 0. The
higher the sensitivity of the sense amplifier is, the faster
the speed of the read operation is.
1.5 OPERATION OF 8T SRAM CELL
1.5.1 Read operation
Read operation in 8T cell is performed by using MOSFETs
Figure: 3 Equivalent CMOS-based SRAM cell circuit
N5 and N6 and RWL. Suppose 1 is stored at one node T
[7][1][2]
and 0 is stored at node F than N2 transistor in on
condition and RWL also 1 is applied to N5, N5 is on but N6
1.4 OPERATION OF 6T CELL
is off so RBL get 1 because RBL is precharge by VDD. Now
1.4.1 Write operation
node T=0 and T=1 than N6 become on and N5 become on
Write operations require an external write driver able to
due to RWL. So RBL become 0.that RBL is sense by the
impose the logic value to write in the cell to the two bit
lines. The write cycle starts by applying the value to be
written to the bit lines. If we wish to write a logic 0, we
would apply VSS to BL and VDD to BL_BAR. This is similar
to applying a reset pulse to a set reset latch, which causes
the flip-flop to change state. A logic 1 is written by
inverting the values of the bit lines. WL is then asserted
and the value that must be stored is latched in. Note that
the reason this works is that the bit line input-drivers are
designed to be much stronger than the relatively weak
transistors in the cell itself, so that they can easily override
the previous state of the cross-coupled inverters. Careful
sizing of the transistors in an SRAM cell is required to
ensure proper operation.
sense amplifier. [8]
Figure: 4 (8T SRAM cell) [7]
1.5.2 Write operation
If we wish to write a logic 0, we would apply WWL to VDD,
VSS to BL and VDD to BL_BAR. This is similar to applying a
1.4.2 Read operation
Assume that the content of the cell is 1 (T = 1). The read
cycle starts by pre-charging both the bit lines to VDD, then
reset pulse to a set reset latch, which causes the flip-flop to
change state. A logic 1 is written by inverting the values of
the bit lines. [8]
asserting the word line WL, enabling both the pass
© 2014, IJOURNALS All Rights Reserved
Page 89
product of an MCML logic circuit and its CMOS counterpart
2. MCML Basics
may be given as shown in Table 1.1.
The operation of an MCML gate may be understood with
the help of the basic structure of an MCML gate, shown in
Figure 2.1. The main parts of the MCML gate are: the load
resistances RL, the differential pull-down network (PDN)
Where N is the logic depth of the MCML logic circuit, f (=1/
CMOS) is the frequency of CMOS logic circuit, is transistor
gain.
with complementary sets of inputs and outputs, and a
As can be seen from Table 1.1, the delay of an MCML logic
constant currents.
circuit varies linearly with voltage swing V and does not
vary with the supply voltage VDD as is the case with
conventional CMOS logic circuits. The power dissipated in
an MCML logic circuit varies linearly with the supply VDD
and is independent of the operating frequency unlike
conventional CMOS circuits where power dissipation
depends linearly on operating frequency and has a squarelaw dependence on supply voltage. Since the delay
depends linearly on V and is independent of supply VDD, it
can be minimized by determining an acceptable and a low
voltage swing V while simultaneously minimizing power
dissipation by reducing the supply voltage VDD, which has
Figure: 5
Basic MCML Gate [9]
little effect on the delay. Thus, as the power dissipated is
independent of the operating frequency, MCML circuits
may be operated at very high speeds with minimal power
The differential inputs are fed to the pull down network
Consumption in contrast to conventional CMOS circuits
(PDN). The design of the PDN takes a tree-like differential
structure, similar to a CMOS circuit technique called
Another important issue concerning MCML logic circuits is
Differential Cascode Voltage Switch (DCVS). The output
the need for a shallow logic depth. As in any other logic
and its complement are available at the two arms as
technique, signal regeneration is of prime importance in
indicated in Figure 2.1. The PDN is grounded through a
MCML gates. The DC voltage gain is usually fixed close to
constant current source ICS, which is usually an NMOS
1.4 to account 7 for process variations and the logic depth
transistor. The differential PDN steers the current
is minimized to prevent signal deterioration thereby
between the two pull up resistance and through the
enhancing regeneration and stability. Also, reducing the
constant current source. The differential tree like
logic depth (N) optimizes the energy delay product (EDP)
structure of the MCML gate would be more apparent in the
as EDPMCML varies cubically with N unlike EDPCMOS that
subsequent discussions on logic gates. [9]
varies with square law dependence. Further, keeping the
signal swing (V) at the output at low values of about few
The total voltage swing at the output and its complement
hundred mV helps in minimizing EDPMCML that has a
is V = ISC x RL which is usually controlled by setting the
square law dependence on V, unlike EDPCMOS that
value of the current source ISC usually an NMOS
depends not on the signal swing but on the supply voltage
transistor, and the effective value of RL, which is usually a
itself.
PMOS device. The value of voltage swing is of the order of
a few hundred mV and is a very crucial leverage factor in
high-speed operation. The equations for the total
propagation delay, power dissipation and power delay
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Page 90
Table 1.1 The Equations for the total propagation delay, power dissipation and power
delay product of an MCML logic circuit and its CMOS.
Parameter
Propagation Delay (𝜏 )
MCML Logic Style
𝜏 MCML =
Conventional CMOS Logic
C L ×∆V ×N
C L ×VDD ×N
τ CMOS =
I SC
β
2
×(VDD −VT 2 )
Power Dissipated (PD)
PDMCML =VDD × ISC × N
2
PDCMOS = N × CL × VDD
×f
Power Delay Product
(PDP)
PDPMCML = N2 × CL × ∆V ×
VDD
2
PDPCMOS =N × CL × VDD
Energy Delay Product
(EDP)
EDPMCML =
N 3 ×C L ×∆V 2 ×V 2DD
I SC
[5]
C 2L ×V 2DD ×N 2
EDPCMOS =
β
2
×(VDD −VT 2 )
Leland Chang, Member, IEEE, Robert K. Montoye,
Member, IEEE, Yutaka Nakamura, Kevin A. Batson,Richard
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