J Electron Test (2015) 31:537–548
DOI 10.1007/s10836-015-5551-3
Double Node Upsets Hardened Latch Circuits
Yuanqing Li 1 & Haibin Wang 1,2 & Suying Yao 3 & Xi Yan 3 & Zhiyuan Gao 3 & Jiangtao Xu 3
Received: 22 May 2015 / Accepted: 2 November 2015 / Published online: 17 November 2015
# Springer Science+Business Media New York 2015
Abstract A radiation hardened by design (RHBD) latch and
its temporally hardened version to tolerate double node upsets
are proposed in this paper. C-Elements are used to construct
structures for fault correction. The temporally hardened version can further tolerate some single-event transients (SETs) at
input port and clock line. Compared with Quintuple Modular
Redundancy (QMR), the proposed non-temporally and temporally hardened latches are more area and power efficient
with improved propagation delays. Compared with several
previously reported temporally hardened latches, the proposed
temporally hardened latch may introduce lower performance
loss induced as setup time increase. Several multi-node upset
tolerant latches are also compared with these two designs in
terms of area, power, and delay. A cell level soft error analysis
(TFIT) shows that the upset threshold LETs of the proposed
latches in 180 nm process are higher than 16 MeV-cm2/mg.
Keywords Double node upsets . Latch . RHBD . Setup time .
Temporal hardening
Responsible Editor: S. Hellebrand
* Yuanqing Li
yuan-qing.li@hotmail.com
Jiangtao Xu
xujiangtao@tju.edu.cn
1
Department of Electrical and Computer Engineering, University of
Saskatchewan, Saskatoon, Canada
2
College of IOT Engineering, Hohai University, Changzhou, China
3
School of Electronic Information Engineering, Tianjin University,
Tianjin, China
1 Introduction
Level sensitive latches are fundamental cells in digital systems, since they are commonly used to build edge triggered
flip-flops in the master-slave mode [23]. A conventional latch
often uses an inverter-loop to keep logic states, and this structure is proven to be vulnerable to single-event upsets (SEUs)
caused by particle strikes [20, 21]. Generally, SEUs would not
lead to permanent damages, so they are referred to as soft
errors [3]. Radiation Hardness by Design (RHBD) is a category of methods which promise SEUs protection through applying commercial technologies. For storage cells including
latches, many well-known RHBD techniques, such as triple
modular redundancy (TMR), are expected to eliminate radiation induced faults only at single nodes [1]. However, the
aggressively scaled device size in deep-submicron and nanometer technologies can allow the single-event charge to affect
multiple nodes simultaneously and cause multi-node upsets
(MNUs) [12]. MNUs impose serious threats on electronic
circuits, since they can additionally increase the soft error rates
(SERs) and may not be fully mitigated by traditional RHBD
methods targeting only SEUs. For semiconductor circuits
manufactured in advanced technologies, MNUs have become
non-ignorable sources of soft errors [7].
Another fault mode caused by radiation is single-event transients (SETs) in combinational circuits [16, 24]. SETs can propagate through logic paths and arrive at sequential elements to
cause upsets [5]. Both SEUs and SETs contribute to the total
SER [5, 14, 15]. However, it has been identified that SETs can
become the dominant factor in the cases where circuits are operated with relatively high clock frequencies [5, 14]. Therefore,
the hardness against SETs is also critical for high performance
systems developed for radiation environment applications.
In this paper, an RHBD latch to tolerate double node upsets
(DNUs) is proposed. C-Elements are applied to build this
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2 Proposed Double Node Upsets Hardened Latch
Circuits
2.1 Schematics of the Proposed Latches
A
A
O
O
B
B
(a)
(b)
Fig. 1 Schematic (a) and symbol (b) of a C-Element [22]
latch for fault mask and correction. When a delay unit is
added, this latch is further temporally hardened to tolerate
SETs at input port and clock line with relatively less performance loss compared to several previously presented
methods. The proposed non-temporally and temporally hardened latches are named NTHLTCH and THLTCH in this
paper.
The rest of this paper is organized as follows. Section 2
presents the schematics, fault injection simulation results,
physical designs, and timing characterizations of the
NTHLTCH and THLTCH. Section 3 provides the comparative analysis of the proposed latches and some other
RHBD solutions. Conclusions of this paper are given in
Section 4.
C-Elements (also called guard-gates or Transition AND
Gates) are commonly applied for soft error mitigation [2,
22]. The schematic and symbol of a C-Element are shown in
Fig. 1 [22]. A C-Element acts as an inverter if both inputs are
identical. If the inputs disagree, the C-Element enters the hold
phase with its output floating, and the logic level at the output
node is maintained by the capacitance loads [2, 22].
The schematic of the NTHLTCH is shown in Fig. 2. Nine
C-Elements (C-Element 1 ~ 9) and three inverters (Inverter
1 ~ 3) are used inside this latch. Switches are built by transmission gates. All these components can be classified into the
following groups: {C-Element1, C-Element2, C-Element3},
{C-Element4, C-Element5, C-Element6}, {C-Element7, CElement8, C-Element9}, and {Inverter1, Inverter2,
Inverter3}. Each C-Element group has three inputs and three
outputs, and each input drives two C-Elements of this group.
When one of these three inputs gets upset, the fault is blocked
by the following C-Elements. In the cases where two inputs
get upset at the same time, the faults can propagate through the
C-Element they are both driving. Taking the group {CElement4, C-Element5, C-Element6} as an example, the simultaneous upsets at B1 and B2 can reach C1. However, since
B3 is not affected, C2 and C3 are protected by C-Element5
and C-Element6.
The analysis above provides an important characteristic of
each C-Element group shown in Fig. 2: for single input upset,
CK
CK
CK
NCK
C-Element 1
C-Element 4
C-Element 7
Inverter1
B1
A1
NCK
C-Element 2
C1
C-Element 5
D1
C-Element 8
Inverter2
D
B2
A2
NCK
C-Element 3
C2
C-Element 6
D2
C-Element 9
Inverter3
B3
A3
NQ
Q
Fig. 2 Proposed non-temporally hardened negative latch NTHLTCH
C3
CK
D3
NCK
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(a)
(b)
Fig. 3 Tolerance to double node upsets at (B1, B2) (a) and (C1, D1) (b) of the NTHLTCH
no fault appears at the three outputs; for double input upsets,
there is only one fault at one of the three outputs. This is
helpful for the understanding of the radiation hardness of the
NTHLTCH. As shown in Fig. 2, there are 12 internal nodes
inside the NTHLTCH, and they can be classified into three
groups, {B1, B2, B3}, {C1, C2, C3}, and {A1, A2, A3, D1,
D2, D3}, for clearer SEUs/MNUs analysis. The reason why
A1~A3 and D1~D3 are located in the same group is that an
inverter can be transparent to a change of its input signal. An
SET can propagate through an inverter as long as it has large
enough magnitude and long enough duration.
SEUs hardness analysis of the NTHLTCH is relatively simple, since an upset at any single internal node meets two following C-Elements which stop this fault from propagating,
and finally the upset node can be recovered by its front-end
component. For example, in the hold phase, an SEU at D1 can
propagate through Inverter1 and reach A1, and the fault at A1
is then blocked by C-Element1 and C-Element3. The level at
D1 will be recovered by C-Element7, and after this A1 will
return to its original state.
DNUs tolerance of the NTHLTCH can be analyzed in two
scenarios. First, we assume that the two nodes got upset
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CK
Delay Unit
CK
CK
I
NCK
O
C-Element 1
C-Element 4
C-Element 7
Inverter1
NCK
C-Element 2
D1
C1
B1
A1
C-Element 5
C-Element 8
Inverter2
Inverter
MOS
Capacitor
D
A2
Inverter
A2
NCK
C-Element 3
D2
C2
B2
C-Element 6
C-Element 9
Inverter3
C3
B3
A3
NQ
Q
CK
D3
NCK
Fig. 4 Proposed temporally hardened negative latch THLTCH
belong to one node group. According to the characteristic of
the C-Element group analyzed before, in this case, the two
faults can propagate through their driving C-Element group
and then be blocked by the next following C-Element group,
and finally be eliminated by their front-end components. For
example, if B1 and B2 get upset simultaneously, the faults can
propagate to C1. Since B3 is still correct, C2 and C3 are not
affected. The incorrect level at C1 cannot go on propagating,
therefore D1 ~ D3 and A1 ~ A3 keep their original and correct
levels. The correct levels at A1, A2, and A3 keep C-Element1
and C-Element2 driving nodes B1 and B2, and the charge
deposited at these two nodes will finally be removed. After
B1 and B2 are recovered, C-Element4 begins to recover C1.
Consequently, all nodes return to their original levels.
Second, we assume that the two upset nodes come from
different node groups. In this case, two of the three C-Element
groups have only one fault at their inputs, respectively, and the
inputs of the remaining C-Element group are all correct. The
faults cannot propagate through their driving C-Element
groups and will be eliminated by their front-end components.
For example, when the levels at C1 and D1 are corrupted, the
fault at D1 can propagate through Inverter1 and reach A1.
This will not lead to any fault at B1, B2, or B3. The correct
levels at B1 and B2 keep C-Element4 driving and recovering
C1. After C1 returns to the original level, C-Element7 begins
to recover D1, and then A1 is corrected by Inverter1. Finally,
each node stays in its expected status.
The analysis of the two DNU tolerance scenarios above is
further verified through fault injection simulation. The schematic shown in Fig. 2 is implemented in 180 nm technology
and a single-event induced current pulse is described as a
double exponential function. The expression for this current
pulse is [25],
Q −t=τ α −t=τ β I ðt Þ ¼
e
−e
:
ð1Þ
τ α −τ β
Here Q is the total amount of charge deposited by a singleevent, while τα is the collection time constant for the junction
and τβ is the ion track establishment constant [25]. For the
simulation reported in this paper, τα = 200 ps, τβ = 50 ps,
and Q = 300fC are used [25]. The results are shown in
SET at D
D
CK
Q
duration
pulse
Pulse at Q
(a)
Fig. 5 Waveform of an SET at D in front of CK edge (a) and simulation results (b)
(b)
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D
CK
duration
Q
pulse
SET at CK
Pulse at Q
(a)
(b)
Fig. 6 Waveform of an SET at CK (a) and simulation results (b)
Fig. 3a for double node upsets at B1 and B2, and in Fig. 3b for
upsets at C1 and D1. It can be seen from Fig. 3 that the
recovery processes for double faults are exactly the same as
the analysis given above. In fact, as long as the number of
affected nodes is not more than 2, the critical charge of each
affected node is theoretically infinite.
Figure 4 shows the schematic of the THLTCH, a temporal
hardening version of the NTHLTCH. An additional delay unit
is added to one input of C-Element1 and C-Element2, and
another node A2’ is introduced. The delay unit is constructed
by applying two inverters in series and adding capacitance
loads to the internal node to adjust its delay to a user-defined
value τ [2]. One PMOS and one NMOS of the same dimension are used as the MOS capacitors and connected between
the internal node and supply/ground.
For the THLTCH shown in Fig. 4, when this latch is transparent (CK = 0) and an SET occurs at D, the incorrect input
could propagate through C-Element3 and reach B3. Since the
level at A2’ is still correct at this point, B1 and B2 will not be
affected temporally. If this SET at D has duration shorter than
τ, the incorrect levels at A1, A2, and A3 will disappear before
the fault at D propagate through the delay unit and reach A2’.
Hence, in this case, even if the fault at D can reach A2’, the
correct levels at A1 and A3 then also insure that no more faults
occur at {B1, B2, B3} and make C-Element3 recover B3. If
this SET at D occurs at the point when CK is driven to HIGH,
Inverter1~Inverter3 will begin to recover the levels at A1~A3.
Hence, the captured incorrect data will not induce an upset of
this latch if the total duration of the wrong levels at A1~A3 is
Fig. 7 Layout of the NTHLTCH
shorter than τ. For an SET on clock line which makes the
THLTCH be incorrectly transparent, the added delay unit also
provides protection in the cases where the wrong input does
not have enough time to affect A1~A3 and A2’ simultaneously. The tolerance to SETs at D and CK are further verified
through circuit simulations. A 500 ps delay unit is applied in
the THLTCH. As shown in Fig. 5a, we assume that an SET
occurs at D just before the rising edge of CK, and the duration
between them is scanned to observe the level change at Q. As
one can see in Fig. 4, an SET at D can propagate to Q when the
THLTCH is transparent. The pulse widths of Q measured at
different durations are illustrated in Fig. 5b. In this sub-figure,
when the SET duration at D before CK edge is shorter than
0.6 ns, the pulse width at Q is of a finite value, which means
the THLTCH can recover from such SETs at D. However,
when the duration increases to be longer than 0.7 ns, the pulse
width of Q become infinite, which means these input SETs
have caused the upsets of the latch. Given that only a 500 ps
delay unit is applied, SETs with 700 ps or longer duration
before CK edge can be long enough to be captured by the
THLTCH.
Figure 6 shows the situation that a negative SET pulse at
CK makes the THLTCH incorrectly transparent and leads to a
pulse at Q. Similar to the results in Fig. 5, if the SET pulse
width at CK is short (<0.5 ns), the temporally transparent state
of the THLTCH does not result in an upset. However, the
longer duration of SETs at CK can make the THLTCH get
upset by allowing the incorrect input data to have sufficient
time to enter the circuit.
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Fig. 8 Layout of the THLTCH
Based on the analysis above, it can be concluded that the
THLTCH can provide hardness against internal SEUs/DNUs
and some SETs at input port and clock line.
The NTHLTCH and THLTCH latches are both static. In the
hold phase, all their internal nodes are connected to supply or
ground through low resistance paths, and their states are maintained by the feedback structures. This improves noise robustness of each node and avoids leakage induced signal integrity
problems. Since each node is driven by a CMOS gate (CElement or inverter), the threshold-drop issue does not exist,
and each node has a rail-to-rail level swing. These characteristics help make these two latches applicable on smaller technology nodes.
of the relatively narrower size in the vertical direction of their
layouts, and M3 must be used to connect nodes which are far
away from each other in the horizontal direction.
2.3 Characterization
Maximum, typical, and minimum parasitic extractions are executed for the NTHLTCH and THLTCH. The generated circuit netlists are used for timing characterization through
Cadence Encounter Library Characterizer (ELC). The products of this step are the timing descriptions in the worst, typical, and best conditions for these two designs in Liberty format. The characterization configuration for each condition is
summarized in Table 2.
2.2 Physical Designs
Layouts of the NTHLTCH and THLTCH (τ = 500 ps) are
depicted in Figs. 7 and 8. These layouts are designed according to the template of a standard cell library developed on the
same 180 nm process. Their areas are 166.32 μm2 and
202.9104 μm2, respectively.
This 180 nm process provides 4 metal layers (M1, M2, M3,
and M4). For the layouts of the NTHLTCH and THLTCH,
three metal layers (M1~M3) are used for internal connections.
According to the standard cell library layout template, M1,
M2, M3, and M4 are expected for routing in the horizontal,
vertical, horizontal, and vertical directions, respectively. Most
cells of this standard cell library use M1 only for internal
connections, while the other metal layers are saved for intercell routings in automatic-place-and-route (APR). Therefore,
the layouts of these two latches occupy some routing channels
on M2 and M3. The ratios of occupied routing channels on
each metal layer for them are summarized in Table 1. For both
NTHLTCH and THLTCH, it can be seen in Table 1 that the
routing channels on M2 are less occupied, while about half of
routing channels on M3 are occupied. This is mainly because
3 Comparative Analysis
3.1 Comparison with Modular Redundancy
Modular redundancy with majority voting is a popular method
for soft errors mitigation. However, SEUs hardened TMR can
be vulnerable to DNUs. To fully tolerate DNUs, quintuple
modular redundancy (QMR) is needed. A QMR latch cell
consists of five replicas of a conventional latch and a voter
to choose the output.
TMR and QMR latch cells are designed through Verilog
HDL description and synthesis process. Schematic simulations in Spectre are used to calculate the propagation delay
and power (when activity ratio = 1) of an unhardened latch,
the TMR/QMR latch, and the two proposed RHBD latches.
All the area, performance, and power data are normalized to
those of the unhardened latch and summarized in Table 3.
As listed in Table 3, the proposed latches both perform
better than QMR. The NTHLTCH and THLTCH are 5.0 and
Table 2
Table 1
Occupied routing channels
Characterization configuration
Condition Parasitic extraction Process corner Supply Temperature
Design
Occupied channels on M2
Occupied channels on M3
NTHLTCH
THLTCH
18.04 %
19.7 %
44.4 %
55.6 %
Worst
Typical
Best
Maximum
Typical
Minimum
Slow-slow
1.62 V 125 °C
Typical-typical 1.8 V 25 °C
Fast-fast
1.98 V −55 °C
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Table 3
543
Area, delay, and power comparison
Design
Area
Propagation delay
Power
Unhardened
1
1
1
TMR
3.8
1.01
3.39
radiation hardness, and they both also require setup times of
about 2τ [17]. Therefore, the setup times of these three latches
in Fig. 9 depend on the maximum SET width to tolerate,
which might somehow affect their applications in high performance circuits. For the THLTCH, a setup time of
QMR
NTHLTCH
10.9
5.0
1.95
1.06
11.20
3.77
t setup ¼ τ þ 3t C−Element þ t Inverter þ t Switch
THLTCH
6.1
1.05
5.60
is needed. Here, tC-Element, tInverter, and tSwitch are the delays of a
C-Element, an inverter, and an NCK controlled switch, respectively. As shown in (2), only one τ is added to the
THLTCH’s setup time. Since the duration of an SET can vary
widely from hundreds of picoseconds to longer than one nanosecond [6], the penalty of increased setup time of the
THLTCH may be less significant compared to the three
latches shown in Fig. 9 when τ is relatively large.
The layouts of the three latches in Fig. 9 are also designed
on this 180 nm process, as shown in Fig. 10. The same 500 ps
delay units (Fig. 4) have been applied for them. The area,
power, and setup times of these three latches and the proposed
ones are summarized in Table 4 for comparison (area/power
data are normalized to those of the NTHLTCH).
It can be seen in Table 4 that the three latches in
Fig. 9 are all more area efficient than the THLTCH.
However, they are all less power efficient than the
NTHLTCH. The main sources of their power increase
are the delay units they applied. As shown in Fig. 10,
the MOS capacitors of delay units consume large gate
areas, and consequently much more energy is needed to
charge them. Because the latch in Fig. 9a uses the most
delay units, it consumes more power than the THLTCH.
The latches in Fig. 9 all consume longer setup times
than the proposed ones. This result is consistent with
the analysis above.
6.1 times larger than the unhardened latch. According to the
synthesis result, QMR applies five replicas of the unhardened
latch listed in this table. Hence, compared to the two proposed
latches, the main area increase of QMR comes from the voter.
The complex voter is also responsible for the large propagation delay of QMR. Compared to QMR, TMR requires less
latch replicas, therefore its voter circuit can be simpler, which
leads to smaller area, lower power, and higher speed. It should
also be noticed in Table 3 that the THLTCH consumes more
power than the NTHLTCH, and this is because of the application of the delay unit which needs more energy to charge its
internal MOS capacitors.
3.2 Comparison with Other Temporally Hardened Latch
Circuits
In [11] and [17], three RHBD flip-flops are reported (one in
[11] and two in [17]). These three flip-flops (with excellent
single-event hardness) all apply temporally hardened latches
as the masters inside. The simplified diagrams of their master
latches are depicted in Fig. 9. Inversed TMR voter is applied
to construct the internal feedback of the latch shown in Fig. 9a.
The inversed TMR voter has three inputs with one not delayed, one delayed by τ, and one delayed by 2τ. This structure
is hardened against SEUs, while is also immune to some SETs
at input port and clock line. For correct operation in nonradiation environment, this latch needs a setup time of about
a bit larger than τ. However, for full radiation hardness, a
setup time of about 2τ is required [11]. The latches shown in
Fig. 9b and c both apply C-Element and delay unit for
Inversed TMR voter
ð2Þ
3.3 Comparison with Other MNUs Tolerant Memory
Circuits
Recently, MNUs issue has been paid more attention. In the
RHBD domain, various designs are proposed to protect memory cells (including latches and static random access memory
CK
CK
CK
D
NCK
D
CK
NCK
D
NCK
CK
(a)
NCK
(b)
Fig. 9 Simplified diagrams of the master latches used by the flip-flops reported in [11] (a) and [17] (b, c)
NCK
CK
NCK
(c)
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Fig. 10 Layouts of the three latches shown in Fig. 9
or SRAM cells) against MNUs on the circuit level. In this
paper, the MNUs tolerant designs presented in [4], [9], [10],
[13], and [18] are chosen to compare them to the proposed
designs. For clear description, they are named
CELL_01~CELL_05 in this paper. Their schematics and layouts are given in Figs. 11 and 12. The area, power, and propagation delay comparison results among them and the proposed NTHLTCH are summarized in Table 5.
As listed in Table 5, CELL_01~CELL_05 designs all
have less transistors than the NTHLTCH, which helps
make them smaller and consume less power. However,
CELL_01 and CELL_02 actually require more power
than the NTHLTCH. One reason of this result should
be that both CELL_01 and CELL_02 are pseudo-static
circuits (the NTHLTCH is static), which means a new
data is written into them through overcoming rather
than cutting off their internal feedbacks. In such an
overcoming process, there can be a temporal
Table 4
Comparison among the five latches
Design
Area
Power
Setup time for rising/
falling inputs (ns)
NTHLTCH
THLTCH
In Fig. 9 (a)
In Fig. 9 (b)
In Fig. 9 (c)
1
1.22
1.08
0.74
0.72
1
1.49
1.61
1.15
1.12
0.31/0.28
0.81/0.81
1.12/1.11
1.24/1.22
1.18/1.16
competition between the existed internal feedback and
the driving capability outside. Taking CELL_02 as an
example, the front-end driving circuit and the clock
controlled PMOS transistors have to compete with the
internal 6 C-Elements to change the states of n1~n6.
This process can introduce temporal conduction paths
from supply to ground, which consequently leads to
larger leakage power. By referring to the schematics of
CELL_01~05, we can see that they are actually all
pseudo-static circuits. However, CELL_03~CELL_05
are still more power efficient than the NTHLTCH because they have much less transistors inside.
In Table 5, we can also see that CELL_01, CELL_02, and
CELL_05 have larger propagation delay compared to the
NTHLTCH. This is still partially because of their pseudostatic characteristics, since their internal feedbacks always
try to resist the write operation. Another reason is the weakened driving capabilities of their last stage components. For
CELL_01 and CELL_02, two- and three-inputs C-Elements
are applied to drive the output load. The transistor stacking
inside these C-Element circuits reduces the driving current
they can provide, which enlarges their delay. For CELL_05,
the driving strength of its last stage inverter is weakened by the
threshold-drops at its input, because its front-end circuits apply PMOSs and NMOSs in series to provide logic levels.
CELL_03 and CELL_04 have shorter propagation delay compared to the NTHLTCH, and this is mainly because of that
their output nodes are nearer to the input ports- only a pass
transistor or transmission gate is inserted between them.
J Electron Test (2015) 31:537–548
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n4
n1
n2
D
N0A
N0A
N1A
N2A
N3A
n5
n6
Q
n3
N2A
n2
Q
n3
n6
n5
n4
n1
N0B
N0B
N1B
N2B
N3B
n2
N2B
n4
n6
n1
n3
n5
CK
D
CK
(a) CELL_01
CK
CK
(b) CELL_02
CK
CK
CK
CKN
N0A
Q
N2A
N3A
a1
D
Q
a2
CK
CK
DN
CKN
CK
D
(c) CELL_03
(d) CELL_04
Q
CK
D
(e) CELL_05
Fig. 11 MNUs tolerant designs in [9] (a), [10] (b), [4] (c), [13] (d), and [18] (e)
The soft error resilience of CELL_01~CELL_05 and
the two proposed designs are evaluated through applying
TFIT, an SER analysis tool developed by iROC
Technologies. TFIT reads in the circuit layout and netlist,
automatically recognizes circuit states, and then carries
out a series of simulations to analyze the design’s SERs
[8]. TFIT supports various radiation environments such
as heavy ions, neutrons, and alpha particles [8].
Compared to traditional technology computer aided design (TCAD) simulations, TFIT can provide much higher
simulation speed while keeping the expected accuracy.
The simulation flow in TFIT is illustrated in Fig. 13.
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(a)
CELL_01
(b)
CELL_02
(c)
CELL_03
(d)
CELL_04
(e)
CELL_05
Fig. 12 Layouts of the MNUs tolerant designs in [9] (a), [10] (b), [4] (c), [13] (d), and [18] (e)
TFIT simulation results show that, with 16 MeV-cm2/mg
linear energy transfer (LET), all the RHBD circuits do not
present any errors in the normal operations. Given that very
few ionizing particles can have LETs higher than 15 MeVcm2/mg in silicon [25], TFIT simulation results verify their
superior protection abilities. Because the TFIT simulations
also take layout information into account, charge sharing effects can be analyzed. Therefore, the layouts of the proposed
designs in Figs. 7 and 8 can be considered as well radiation
hardened.
It should be noted that CELL_03~CELL_05 have floating
nodes inside in the hold phase. Therefore, these cells should
J Electron Test (2015) 31:537–548
Table 5
547
Comparison among different MNUs tolerant designs
Design
Transistor amount Area Power Propagation delay
NTHLTCH
60
1
1
1
CELL_01 [9]
30
0.62
1.45
1.53
CELL_02 [10] 38
CELL_03 [4] 16
0.80
0.44
1.24
0.71
3.00
0.21
CELL_04 [13] 13
CELL_05 [18] 20
0.34
0.38
0.29
0.30
0.15
2.46
be frequently refreshed to avoid leakage and noise injection
induced signal integrity issues. For CELL_01, CELL_02, and
the proposed two designs, refreshing operation is not very
necessary since their structures can keep states correctly.
Radiation tolerance and refreshing requirement of each design
is summarized in Table 6.
4 Conclusion
In this paper, an RHBD latch NTHLTCH and its temporally
hardened version THLTCH to tolerate single−/double-node
upsets are proposed. The radiation hardness of these two
latches is implemented by applying C-Elements for fault mask
and correction. Double exponential current pulse model is
applied for the fault injection simulations, and the simulation
results verify and support the DNUs tolerance of these proposed designs. The NTHLTCH is hardened against state upsets in the hold phase, while THLTCH can further tolerate
some SETs at input port and clock line. TMR and QMR are
taken to compare with the NTHLTCH and THLTCH in terms
of area, transport delay, and power. Comparison results show
that the proposed latches perform better than QMR in all the
terms. Compared with three temporally hardened latches
(Fig. 9) applied in three flip-flops reported before, the proposed temporally hardened THLTCH could induce less
Fig. 13 TFIT simulation flow [8, 19]
Table 6
Radiation tolerance and refreshing requirement of each design
Design
Upset threshold
from TFIT
(MeV-cm2/mg)
SET tolerance
Refreshing
NTHLTCH
THLTCH
>16
>16
No
Yes
Not required
Not required
CELL_01 [9]
CELL_02 [10]
>16
>16
No
No
Not required
Not required
CELL_03 [4]
>16
No
Required
CELL_04 [13]
CELL_05 [18]
>16
>16
No
No
Required
Required
performance penalty since it only adds one τ to its total setup
time while those three latches all require 2τ. The NTHLTCH
is more power efficient than those three latches in Fig. 9 because those three designs use more delay units. TFIT simulations show that the two proposed designs do not present any
error with an LET of 16 MeV-cm2/mg.
Acknowledgments The authors appreciate the supports from CMC
Microsystems, iROC Technologies, and NSFC under contract No.
61504038.
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Yuanqing Li received the B.E. degree in electronic science and technology, M.E. and Ph.D degrees in microelectronics and solid-state electronics from Tianjin University, Tianjin, China, in 2008, 2010, and 2014,
respectively. He is now a post-doctoral fellow with the Department of
Electrical and Computer Engineering, University of Saskatchewan, Canada. His research interests include the radiation effects on microelectronic
circuits and devices, radiation hardness by design techniques, and large
scale digital circuits design.
Haibin Wang received the Ph.D degree from the University of Saskatchewan in 2015. He received his Bachelor and Master degrees from Hohai
University. His research interests include radiation effects, fault-tolerant
IC design, reliability engineering, and embedded system design. He has
worked on single event hardened flip-flop and logic design and testing in
28 nm bulk/SOI and 130 nm technologies.
Suying Yao is now a Professor with the Department of Electronic Science
and Technology, School of Electronic Information Engineering, Tianjin
University, Tianjin, China. She is the director of the state key discipline
Microelectronics and Solid-State Electronics in Tianjin University and
the director of the ASIC Design Center, Tianjin University. She is also
on the board of directors of the Chinese Institute of Electronics (CIE) and
a member of the IEEE. Her research interests include the designs of
CMOS image sensors and digital/analog integrated circuits, and modeling
of semiconductor devices.
Xi Yan received the B.E. degree in electronic science and technology in
2013 from Tianjin University, Tianjin, China, where she is currently
working toward the M.E. degree. Her research interests include the development of radiation-hardened CMOS image sensors, and digital circuits design.
Zhiyuan Gao received the B.E. degree in electronic science and technology in 2010 and Ph.D degree in microelectronics and solid-state electronics in 2015 from Tianjin University, Tianjin, China. He is now a postdoctoral fellow with Tianjin University. His research interests include the
development of CMOS image sensors on advanced processes, digital/
analog circuits design, and TCAD modeling for optical-electronic
devices.
Jiangtao Xu received the B.E. degree in electronic science and technology, M.E. and Ph.D. degrees in microelectronics and solid-state electronics from Tianjin University, Tianjin, China, in 2001, 2004, and 2007,
respectively. He is now an Associate Professor with the Department of
Electronic Science and Technology, School of Electronic Information
Engineering, Tianjin University. His research interests include the designs
of CMOS image sensors, power management circuits, and SOCs for
image processing.