FT13
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Session-02
Amplifier Design
Session delivered by:
Chandramohan P.
©M S Ramaiah School of Advanced Studies - Bangalore
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Session Objectives
To understand the concept of amplifier and its applications
To understand different types of amplifier
To understand the concept of small signal model for single stage amplifier
To design, simulate and analysis of single stage amplifier
To design, simulate and analysis of differential amplifier
To design, simulate and analysis of Op-amp
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Session Topics
Single stage amplifier and its types
Small signal Analysis of single stage amplifier
Design of single stage and differential stage amplifier
Simulation of single stage and differential stage amplifier
Design and analysis of single stage, differential stage amplifier and
operational amplifier
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Introduction to Amplifier
A circuit that increases the amplitude of the given input signal is an amplifier
A small AC signal fed to the amplifier is obtained as large AC signal of the
same of frequency at output.
Analog or digital signals are amplified, because it may be to small to drive
load, overcome the noise of a subsequent stage, or provide logical levels to a
digital system
Performance parameters
–
–
–
–
–
–
–
–
Gain
Speed
Linearity
Noise
Maximum voltage swing
Supply Voltage
Power dissipation
Input and Output impedance
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Classification of Amplifier
Based on Transistor configuration
– Common emitter/source amplifier
– Common collector/drain amplifier
– Common base/gate amplifier
Based on active device
– BJT amplifier
– MOS amplifier
Based on the Q-point (Operating point)
– Class A amplifier
– Class B amplifier
– Class AB amplifier
– Class C amplifier
Based on the number of stages
– Single stage amplifier
– Multistage amplifier
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Classification of Amplifier
Based on the output
– Voltage amplifier
– Current Amplifier
Based on the frequency response
– Audio frequency amplifier
– Intermediate frequency amplifier
– Radio frequency amplifier
Based on the bandwidth
– Narrow band amplifier (RF)
– Wide band amplifier (video)
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Common-Source Amplifier
A MOSFET converts variations in its gate-source voltage to a small-signal
drain current, which can pass through a resistor to generate an output
voltage.
Small signal equivalent circuit for saturation region
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Common-Source Amplifier
Draw Back of Resistive load
For example, if a l-MΩ load were required with a 100µA bias current, a
resistive-load approach would require a power-supply voltage of l-MΩ x
100µA = 100 V
This resistive-load approach also greatly increases the power dissipation
As a result. for a given power-supply voltage, a larger voltage gain can be
achieved using an active load than would be possible if a resistor were used
for the load
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Common-Source Amplifier
A common use of simple current mirrors is in a single-stage amplifier with
an active load, as shown in Figure given below
This common-source topology is the most popular gain stage, especially
when high-input impedance is desired
An n-channel common-source amplifier has a p-channel current mirror used
as an active load to supply the bias current for the drive transistor
By using an active load, a high-impedance output load can be realized
without using excessively large resistors or a large power-supply voltage
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Small Signal Model of CSA
Using small-signal analysis, we have vgs1 = vin and, therefore
Depending on the device sizes, currents, and the technology used, a typical gain for
this circuit is in the range of -10 to -100
For low-gain, high-frequency stages, it may be desirable to use resistor loads (if they
do not require much silicon area) because they often have less parasitic capacitances
associated with them.
Resistive loads are also typically less noisy than active loads.
©M S Ramaiah School of Advanced Studies - Bangalore
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Small Signal Model of CSA
Using small-signal analysis, we have vgs1 = vin and, therefore
Depending on the device sizes, currents, and the technology used, a typical
gain for this circuit is in the range of -10 to -100
For low-gain, high-frequency stages, it may be desirable to use resistor loads
(if they do not require much silicon area) because they often have less
parasitic capacitances associated with them.
Resistive loads are also typically less noisy than active loads.
©M S Ramaiah School of Advanced Studies - Bangalore
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CSA – Design Example
VSD2537
Consider a common source amplifier with a current mirror active load as shown in the
figure. Assume all transistors have W/L = 100µm/1.6µm , and that µnCox=90µA/V2,
µpCox=90µA/V2, Ibias = 100µA, rds-n(Ω) = 8,000L(µm)/ID(mA), and rds-p(Ω) =
12,000L(µm)/ID(mA). What is the gain of the stage?
Solution:
We have
Also
and
Therefore
g m1 = 2µ nCox (W / L)1 I bias = 1.06mA / V
rds1 =
8,000 × 1.6 µm
= 128kΩ
0.1mA
rds 2 =
12,000 × 1.6 µm
= 192kΩ
0.1mA
AV = − g m1 (rds1 || rds 2 ) = −1.06(128 || 192) = −81.4
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Common Source Amplifier with a Current Mirror Active Load
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Spice Code for CSA
Vdd 1 0
dc 5
Ibias 2 0
dc 100u
M3
2 2 1 1 pmos W=200u L=2.6u
M2
3 2 1 1 pmos W=200u L=2.6u
M1
3 4 0 0 nmos W=200u L=2.6u
Vin 4 0
VSD2537
dc 0.849 ac 1
.op
.ac dec 10 1k 10000Meg
.plot ac vdb(3)
.lib C:\Documents and Settings\Desktop\SPICE\CMOS 2U.lib
.end
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Frequency Plot for the Common Source Amplifier
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The gain is 36dB, which
corresponds to 63V/V
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Source Follower (or) Common Drain Amplifier
Commonly used as voltage buffers and are therefore commonly called source
followers. They are also referred to as common-drain amplifiers
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Source Follower
The simplified small-signal model of source follower
Vgs1 = Vin – Vout
VoutGs1 – gm1(Vin-Vout) = 0 where Gs1 = l/Rs1
Solving for Vout/Vin we have,
Normally, gs1 is on the order of one-tenth to one-fifth that of gml
Transistor output admittances, gds1 and gds2 might be one-tenth that of the body-effect
parameter gs1
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Source Follower Stage with a Current Mirror
Consider the source follower in the figure where all transistors have W/L = 100µm/1.6µm,
µnCox=90µA/V2, µpCox=30µA/V2, Ibias = 100µA, γn= 0.5V1/2 rds-n(Ω) = 8,000L(µm)/ID(mA).
What is the gain of the stage?
Solution:
We have
Also
g m1 = 2µ n Cox (W / L)1 I bias = 1.06mA / V
rds1 = rds 2 =
8,000 ×1.6 µm
= 128kΩ
0.1mA
Taking body effect into consideration
g s1 =
γg m
2 VSB + | 2φ F |
Consider VSB ≈ 2V ∴ g = 0.5 × g m = 0.15 g = 0.16mA / V
s1
m
2 2 + 0.7
We have
AV =
1.06
= 0.86V / V
1.06 + 0.16 + 1 / 128 + 1 / 128
©M S Ramaiah School of Advanced Studies - Bangalore
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Spice Code for CDA
Vdd 1 0
dc 5
Ibias 1 2
dc 100u
M3
2 2 0 0 nmos W=80u L=2u
M2
3 2 0 0 nmos W=80u L=2u
M1
1 4 3 0 nmos W=80u L=2u
Vin 4 0
VSD2537
dc 2 ac 1
.op
.ac dec 10 1k 1000Meg
.plot ac vdb(3)
.lib C:\Documents and Settings\Desktop\SPICE\CMOS CN20.lib
.end
©M S Ramaiah School of Advanced Studies - Bangalore
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Frequency Plot for the Source-Follower
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The gain is –1.36dB, which
corresponds to 0.86V/V
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Common Gate Amplifier
This stage is commonly used as a gain stage when a relatively small input
impedance is desired.
For example, it might be designed to have an input impedance of 50Ω to
terminate a 50Ω transmission line.
Another common application for a common-gate amplifier is the first stage
of an amplifier designed to amplify current rather than voltage.
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Common Gate Amplifier
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Types of Amplifiers
Voltage amplifiers because they sense a voltage at the input and produce a voltage at
the output
Sensing a voltage must exhibit a high input impedance (as a voltmeter)
Sensing a current must provide a low input impedance (as a current meter)
Generating a voltage must exhibit a low output impedance (as a voltage source)
Generating a current must provide a high output impedance (as a current source)
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Types of Amplifiers
For example, a trans impedance amplifier may have a gain of 2KΩ, which
means it produces a 2-V output in response to a 1mA input
Modification for performance
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Single Ended and Differential Signal
A single-ended signal is defined as one that is measured with respect to a
fixed potential, usually the ground.
A differential signal is defined as one that is measured between two nodes
that have equal and opposite signal excursions around a fixed potential.
The center potential in differential signalling is called the common-mode
(CM) level.
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Differential Signal
Advantages
– Higher immunity to "environmental" noise
Example 1
– If the clock line is placed midway between the two, the transitions
disturb the differential phases by equal amounts, leaving the difference
intact.
– Since the common mode level of the two phases is disturbed but the
differential output is not corrupted, we say this arrangement "rejects"
common-mode noise.
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Differential Signal
Example 2 - Effect of supply noise on single ended and differential signal
– Common-mode rejection occurs with noisy supply voltages
– If VDD varies by ∆V, then Vout, changes by approximately the same
amount,
– i.e., the output is quite susceptible to noise on VDD
– If the circuit is symmetric, noise on VDD affects Vx and Vy, but not Vx
– Vy = Vout
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Differential Signal
Example 3 - It is also beneficial to employ differential distribution for noisy
lines
– Suppose the clock signal is distributed in differential form on two lines,
Then, with perfect symmetry, the components coupled from CK and C K
to the signal line cancel each other.
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Differential Signal
Example 4 - Another useful property of differential signaling is the increase
in maximum achievable voltage swings
– The maximum output swing at X or Y is equal to VDD - (VGS-VTH)
– where as for Vx - Vy, the peak-to-peak swing is equal to 2[ VDD (VGSVTH) ]
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Basic Differential Pair
The two identical single-ended signal paths to process the two phases in Fig
The above circuit indeed offers some of the advantages of differential
signaling; high rejection of supply noise and higher output swing
But what happens if Vin1 and Vin2 experience a large common-mode
disturbance or simply do not have a well defined common-mode dc level
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Basic Differential Pair
The input CM level, Vin,CM changes, so the bias currents of M1and M2
varying both the transconductance of the devices and the output CM level.
The variation of the transconductance in turn leads to a change in the smallsignal gain while the departure of the output CM level from its ideal value
lowers the maximum allowable output swing
If the input CM level is excessively low, the minimum values of Vin1 and
Vin2 in fact turn off M1and M2, leading to severe clipping at the output.
Thus, it is important that the bias currents of the devices have minimal
dependence on the input CM level
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Basic Differential Pair
A simple modification can resolve the above issue
The differential pair employs a current source ISS to make ID1 + ID2
independent of Vin,CM gg
If Vinl = Vin2, the bias current of each transistor equals lss/2 and the output
common-mode level is VDD - RDISS/2.
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Input-output characteristics of a differential pair.
Vinl << Vin2, M1 is off, M2 is on, and ID2 = ISS. Thus, Voutl = VDD and Vout2
= VDD – RDISS l
Vin1= Vin2, then VOut1= Vout2= VDD - RDISS/2.
Vinl >> Vin2, MI carries a greater current than does M2 and Voutl drops
below Vout2
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Common-mode Behaviour of Differential Pair
The role of the tail current source is to suppress the effect of input CM level
variations on the operation of M1 and M2 and the output level
Does this mean that Vin,CM can assume arbitrarily low or high values?
Set Vinl = Vin2 = Vin,CM and vary Vin,CM from 0 to VDD
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Common-mode Behaviour of Differential Pair
For proper operation, Vin,CM >= VGS1 + (VGS3- VTH)
Vin,CM is bounded as follows
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Small-signal Differential Gain of a Differential pair
The gain begins to increase as Vin,CM exceeds VTH
The tail current source enters saturation (Vin,CM = V1), the gain remains
relatively constant.
Finally, if Vin,CM is so high that the input transistors enter the triode region
(Vin,CM= V2), the gain begins to fall
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Differential Amplifier
The differential-mode input voltage, VID, of the differential amplifier is
defined as the difference between V1, and V2
This voltage is defined between two terminals, neither of which is ground
The common-mode input voltage, VIC is defined as the average value of V1
and V2
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Differential Amplifier
Common-mode rejection ratio (CMRR), which is the ratio of the
magnitude of the differential gain to the common-mode gain.
Input common-mode range (ICMB) specifies over what range of commonmode voltages the differential amplifier continues to sense and amplify the
difference signal with the same gain
Offset Voltage, the input terminals of the differential amplifier are
connected together, the output voltage is at a desired quiescent point. In a
real differential amplifier, the output offset voltage is the difference between
the actual output voltage and the ideal output voltage when the input
terminals are connected together
Input offset voltage (VOS), If this offset voltage is divided by the differential
voltage gain of the differential amplifier, then it is called the input offset
voltage. Typically, the input offset voltage of a CMOS differential amplifier
is 5-20 mV.
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Differential Amplifier
VIC,MIN and VIC,MAX of differential amplifier
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Slew Rate
The slew-rate performance of the CMOS differential amplifier depends the
value of ISS and the capacitance from the output node to ac ground
Slew rate (SR) is defined as the maximum Output-voltage rate, either
positive or negative
The slew rate in the CMOS differential amplifier is determined by the
amount of current that can be sourced or sunk into the output compensating
capacitor
Slew rate = ISS/C
C is the total capacitance connected to the output node. For example, if Iss =
10 uA and C = 5 pF the slew rate is found to be 2V/us. The value of Iss be
increased to increase the slew-rate capability of the differential amplifier
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CMOS Differential Amplifier
Design the currents and W/L values of the current mirror load MOS
differential amplifier to satisfy the following specifications:
VDD = -VSS = 1.8V
SR ≥ 10V/µs (CL=5pF),
f-3dB ≥ 100kHz (CL=5pF),
small signal gain of 100V/V,
-1V ≤ ICMR ≤ 1.5V
Pdiss ≤ 1mW.
©M S Ramaiah School of Advanced Studies - Bangalore
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CMOS Differential Amplifier
Design of a CMOS Differential Amplifier with a Current Mirror Load
Design Considerations:
Constraints
Power supply
Technology
Temperature
Specifications
Small-signal gain
Frequency response (CL)
ICMR
Slew rate (CL)
Power dissipation
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CMOS Differential Amplifier
Procedure:
– Pick ISS to satisfy the slew rate
knowing CL or the power
dissipation
– Check to see if Rout will satisfy
the frequency response, if not
change ISS or modify circuit
– Design W3/L3 (W4/L4) to satisfy
the upper ICMR
– Design W1/L1 (W2/L2) to satisfy
the gain
– Design W5/L5 to satisfy the
lower ICMR
– Iterate where necessary
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CMOS Differential Amplifier
Solution
Step1:- To meet the slew rate, and maximum Power Dissipation
I 5 = SR ⋅ CL = (10V / µs) × 5 pF = 50µA
⇒ I 5 ≥ 50µA
LL (1)
Pdiss = (VDD + VSS )⋅ I5
I5 =
1mW
= 277.7µA
(1.8 + 1.8)
⇒ I 5 ≤ 277.7µA LL (2)
Step2:- To meet the frequency requirement
ω3dB =
1
Rout ⋅ C L
1
2π ⋅100k =
Rout ⋅ 5 pF
⇒ Rout
1
=
= 318471.33Ω
2π ⋅100k ⋅ 5 pF
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CMOS Differential Amplifier
2
Rout =
(λN + λP ) ⋅ I5
Rout is given by
2
I5 =
= 34 .888 µA
( 0 .09 + 0 .09 ) ⋅ 318471 .33
⇒ I 5 ≥ 35 µ A L L (3)
From Eqns. (1), (2) and (3) We can pick the I5 as approx. 100µA
Step3:- The maximum input common mode voltage gives
VGS3 = VDD – VIC(max) + VTN1 = 1.8 – 1.5 + 0.379924 = 0.6799V ≈ 0.7V
Therefore, we can write
VSG 3 =
2 ⋅ I DS
+ VTP
 W3 

µ P C ox 
 L3 
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CMOS Differential Amplifier
Solving for W1/L1 gives
0 .7 =
50µA
+ 0.4038864
2  W3 
36µA / V  
 L3 
 W3 
⇒   = 15.839 ≈ 16
 L3 
∴
W3 W4
=
= 16
L3 L4
Step4:- Using the small signal gain specification gives
gm1
AV = gm1 ⋅ Rout =
gds2 + gds4
 W1 
2 I ds 2 ⋅  
 L1 
⇒ AV =
(λ N + λ P ) I 3
Solving for W1/L1 gives
W 
2 × 165.5 ×  1 
 L1 
100 =
1.8 × 50
 W1 
  = 48.9425 ≅ 49
 L1 
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CMOS Differential Amplifier
∴
W2 W1
=
= 49
L2
L1
Step5:- Using the minimum input common mode voltage gives
VDS5(sat) =VIC(min)−VSS −VGS1
VDS 5( sat ) = VIC (min) − VSS −
VDS 5( sat ) = −1 + 1.8 −
2 I D1
+ VTN
W
µ n Cox 1
L1
50
+ 0.379924 = 0.3415
165.5 × 49
This value of VDS5(sat) gives a W5/L5 of
W5
I
100
= ' 25
=
= 5.18
2
L5 K nVDS 5( sat ) 165.5 × (0.3415)
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CMOS Differential Amplifier
W2 W1
∴ = = 49
L2 L1
W3 W4
∴ = =16
L3 L4
W5
=5
L5
W6
=5
L6
©M S Ramaiah School of Advanced Studies - Bangalore
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CMOS Differential Amplifier
SPICE code
CMOS Differential Amplifier with PMOS Current Mirror
M3 P1 P1 Vdd Vdd CMOSP L=1U W=16U
M4 Vout P1 Vdd Vdd CMOSP L=1U W=16U
M1 P1 Vin+ P2 gnd CMOSN L=1U W= 49U
M2 Vout Vin- P2 gnd CMOSN L=1U W=49U
M5 P2 P3 Vss Vss CMOSN L=1U W=5U
M6 P3 P3 Vss Vss CMOSN L=1U W=5U
Cload vout gnd 5pF
Ibias Vdd P3 100U
Vdd Vdd Gnd DC 1.8
Vin1 Vin+ Gnd DC 0.5 ac 1
Vin2 Vin- Gnd DC 0.5
Vss Vss gnd dc -1.8
.AC DEC 25 1 10Meg
.print ac vm(Vout) vdb(vout)
.end
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CMOS Differential Amplifier
Simulation Results
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Introduction to Op-amp
Most versatile and important building blocks in analog circuit design
Classification
– Buffered Op-amp Low output resistance (voltage operational
amplifiers).
– Unbuffered Op-amp - High output resistance (operationalTransconductance amplifiers or OTAs)
Operational amplifiers are amplifiers (controlled sources) that have
sufficiently high forward gain so that when negative feedback is applied, the
closed-loop transfer function is practically independent of the gain of the op
amp
The primary requirement of an op amp is to have an open-loop gain that is
sufficiently large to implement the negative feedback concept
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Introduction and Characterization of Op-amp
©M S Ramaiah School of Advanced Studies - Bangalore
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Operational Amplifiers
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Properties
– open-loop gain: ideally infinite: practical values 20k-200k
– input impedance: ideally infinite: CMOS opamps are close to ideal
– output impedance: ideally zero: practical values 20-100Ω
– zero output offset: ideally zero: practical value <1mV
– gain-bandwidth product (GB): practical values ~MHz
• frequency where open-loop gain drops to 1 V/V
Commercial opamps provide many
different properties
– low noise
– low input current
– low power
– high bandwidth
– low/high supply voltage
– special purpose: comparator, instrumentation amplifier
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Ideal Opamp
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Inverting opamp
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Opamp Characterization
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Linear and Dynamic Characteristics
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Linear and Dynamic Characteristics
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Classification
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Two stage Op-amp
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Op-amp Compensation
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Stability
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Stability
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Uncompensated Frequency Response
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Uncompensated Frequency Response
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Uncompensated Frequency Response
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Miller Compensation
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Miller Compensation
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Generalized Frequency Response
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Frequency Response
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Compensated Op-amp
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Conceptual Perspective of the Roots
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Conditions for Stability
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Two Stage Op-amp - Design
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Design of opamp
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FT13
VSD2537
Design of two stage opamps
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VSD2537
Case Study: Operational Amplifier Design
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Operational Amplifier Design
VSD2537
Design an two stage operational amplifier with the following specifications:
Av
Power supply
Gain Bandwidth (GB)
Load capacitance (CL)
Slew Rate (SR)
Vout range
ICMR
Pdiss
>5000v/v
Vdd = |Vss| = 2.5V
5MHz
10pf
>10v/µs
± 2V
-1 to 2V
≤ 2mW
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Operational Amplifier Design cont…
VSD2537
Solution:
Technology Parameters:
Vth= 0.7 v
K′p= 50 µA/V²
K′n= 110 µA/V²
1. To find the desired compensation capacitor from the
load capacitor for a 60 phase Margin
Cc > 0.22 CL
Cc > 2.2pf
Cc =3pf
=> Cc > 0.22 * 10 pf
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Operational Amplifier Design cont…
VSD2537
2. Finding of bias current from the slew rate and compensation
capacitor
I5 = SR .Cc = 10 µA *3pf = 30 µA
3. Calculating S3 transistor sizing from the ICMR specifications
S3 = (W/L) 3 = I5/ K′3[VDD – Vin (max) – |VTO3|(max) + VTL(min)]²
= 30x10-6/50x10-6 [2.5 – 2 –0.85 + 0.55]²
= 15
S3 = S4 = 15
(W/L)3 = (W/L)4 =15
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VSD2537
Operational Amplifier Design cont…
15µm
1µm
15µm
1µm
30 µA
3pf
10pf
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Operational Amplifier Design cont…
VSD2537
4. Finding Transconductance of the S1 transistor from the gain
bandwidth specification
gm1 =GB. Cc = 5X106 *3x1012 *2π =94.25 µs
5. Calculating S1 transistor sizing from the Transconductance
S1 = S2 = (W/L)1 = (W/L)2 =gm1²/ 2 K′n I1
= (94.25x10-6)2/2*110x10-6*15X10-6
= 2.79
S1 = S2 = 3
(W/L)1 = (W/L)2 = 3
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Operational Amplifier Design cont…
15µm
1µm
VSD2537
15µm
1µm
30 µA
3µm
1µm
3µm
1µm
3pf
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10pf
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Operational Amplifier Design cont…
VSD2537
6. Calculating VDS of transistor S5 from ICMR specifications
VDS5 = Vin(min) – Vss – (I5/β1)½ –VT(max)
= (–1) – (–2.5) – (30x10-6/110x10-6*3)½ – 0.85
= 0.35 V
7.
(W/L)5 = 2 I5/ K′5(VDS5)²
= 2*30x10-6/110x10-6*(0.35)²
= 4.49
(W/L)5 = 4.5
8. Finding tarnsconductance of S6 from gm1
gm6 ≥ 10 gm1 => gm6 ≥ 10 * 94.25 µ
gm6 ≥ 942.5µ
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Operational Amplifier Design cont…
15µm
1µm
VSD2537
15µm
1µm
30 µA
3µm
1µm
4.5µm
1µm
3µm
1µm
3pf
10pf
4.5µm
1µm
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Operational Amplifier Design cont…
VSD2537
9. Calculating S6 transistor sizing from the Transconductance of
gm6 and gm4
(W/L)6 = (W/L)4 * gm6/gm4
= 15* 942.5µ/150µ
= 94
(W/L)6= 94
10. Calculating I6
I6 = (gm6)²/2 K′6(W/L)6
= (942.5x10-6)²/2*50x10-6*94 =94.5uA
I6 =95µA
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VSD2537
Operational Amplifier Design cont…
15µm
1µm
94µm
1µm
15µm
1µm
30 µA
3µm
1µm
4.5µm
1µm
3µm
1µm
3pf
10pf
4.5µm
1µm
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Operational Amplifier Design cont…
VSD2537
11. Calculating of S7 from the S5 ,I6 and I5
(W/L)7 = (W/L)5 * I6 /I5
= 4.5 * 95x10-6/30x10-6
= 14.25
(W/L)7 = 14
12.
Vmin(out) = VDS7(sat) = √(2.I6/ K′(W/L)7)
= √2*95x10-6/110x10-6*14
= 0.3514V
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VSD2537
Operational Amplifier Design cont…
15µm
1µm
94µm
1µm
15µm
1µm
30 µA
3µm
1µm
4.5µm
1µm
3µm
1µm
3pf
4.5µm
1µm
©M S Ramaiah School of Advanced Studies - Bangalore
10pf
14µm
1µm
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Operational Amplifier Design cont…
VSD2537
13. Calculating the power dissipation of opamp
Pdiss
= (I5 + I6) *(VDD+|VSS|)
= (30x10-6+95x10-6)*(2.5+2.5)
Pdiss = 0.625mW
14. Verifying the gain of the two stage operational amplifier
AV = (2.gm2.gm6)/I5 *I6 *(λ2+ λ3) (λ6+ λ7)
= 2*94.25µ*942.5µ/95µ*30µ* (0.04+0.05) (0.05+0.04)
Av = 7696v/v
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Open Loop Transfer Characteristic
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VSD2537
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Spice Deck for Open Loop Transfer Characteristic
CMOS Two Stage Opamp
vin+ 1 0 dc 0 ac 1
vin- 2 0 dc 0
vdd 4 0 dc 2.5
vss 0 5 dc 2.5
.subckt opamp 1 2 6 8 9
m1 4 2 3 3 CMOSN l=1u w=3u
m2 5 1 3 3 CMOSN i=1u w=3u
m3 4 4 8 8 CMOSP l=1u w=15u
m4 5 4 8 8 CMOSP l=1u w=15u
m5 3 7 9 9 CMOSN l=1u w=4.5u
m8 7 7 9 9 CMOSN l=1u w=4.5u
m6 6 5 8 8 CMOSP l=1u w=94u
m7 6 7 9 9 CMOSN l=1u w=14u
ibias 8 7 dc=30u
cc 5 6 3p
.ends
VSD2537
x1 1 2 3 4 5 opamp
cload 3 0 10p
.op
.dc vin+ -0.005 0.005 100u
.plot dc v(3)
.ac dec 10 1 100meg
.plot ac vdb(3) vp(3) vm(3)
.end
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Open Loop Transfer Characteristic
Magnitude Response
VSD2537
Phase Response
Phase margin
Gain Band Width is 5 MHz
Phase Margin is 650
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Open Loop Transfer Characteristic
VSD2537
Output Voltage Swing Response
VOS
Voltage swing is +2.3 to -2.2V
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Measurement of Open Loop Output Current
VSD2537
Rout = RL ((Vo1/Vo2)-1)
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Unity Gain Configuration Test Setup
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ICMR Response Curve
VSD2537
I(M)
ICMR
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Measurement of Slew Rate and Settling Time
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VSD2537
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VSD2537
Unity Gain Transient Response
Positive SR = 10V/us
Negative SR =-6.7V/us
Over shoot
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Measurement of PSRR
VSD2537
Vout
1
=
Vdd PSRR+
Vout
1
=
Vdd PSRR+
Vout
1
=
Vss PSRR−
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Measurement of
PSRR+ Magnitude response
PSRR+
VSD2537
PSRR+ Phase response
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Measurement of
PSRR- Magnitude response
PSRR-
VSD2537
PSRR- Phase response
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Comparison of the Simulation with Design Spec
Specification
Design
Simulation
Open loop Gain
> 5000
10,000
GB (MHz)
5 MHz
5 MHz
ICMR (Volts)
-1 to 2 V
+2.4V, -1.2V
Slew Rate (V/us)
>10(V/us)
+10, -7 (V/us)
Pdiss (mw)
<2 mW
0.625 mW
Vout range (V)
±2 V
+2.3V, -2.2V
PSRR+ (dB)
----
87
PSRR- (dB)
----
116
Phase Margin (Degrees)
60°
65°
Output Resistance (KΩ)
----
122.5 KΩ
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VSD2537
Summary
Amplifiers are amplify an analog or digital signal because it may be too
small to drive a load, overcome the noise of a subsequent stage, or provide
logical levels to a digital circuit
In single stage amplifier, common-source topology is the most popular gain
stage, especially when high-input impedance is desired
Single stage amplifiers can be designed carefully taking care of loading
conditions and active loads for better gain
Differential amplifiers form the basic building block of operational
amplifiers
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Summary
VSD2537
Opamp can be used for various applications in analog design
Two stage and folded cascode opamp are the basic types of opamps available
Opamp compensation is very important for the stability of the opamp
Phase margin of 60 is optimum for the opamp design
Opamp analysis is complete only when noise analysis is done
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