Evaluation Kit
User’s Manual
Integer-N PLL Frequency Synthesizer
PE97240
PE97240
Evaluation Kit Manual
Table of Contents
Introduction …………………………………………………………………………………. 3
Applications Support ……………………………………………………………………… 3
Evaluation Kit Contents and Requirements …………………………………………… 3
Kit Contents …………………………………………………………...………………… 3
Software Requirements ……………………………………………………….………… 3
Hardware Requirements ………………………………………………………………… 3
PE97240 PLL Evaluation Board Assembly ……………………………………………. 4
Overview ………………………………………………………………………………... 4
USB Interface Board ………………………………………………………………….……. 5
USB Interface Board Overview …………………………………………………..……… 5
Connection of the USB Interface Board to the Evaluation Board …………………….… 5
EVK Software Installation ………………………………………………………….……… 6
Using the Application Software Graphical User Interface ………….………………. 9
Evaluation Board Overview ……………………………………………………….……… 11
Hardware Operation …………………………………………………………………….…. 14
Testing the EVK Using the Graphical User Interface …………………………………15
Direct Programming Mode …………………………………………………………………17
Troubleshooting Tips ……………………………………………………………………… 18
Technical Resources ………………………………………………………………………..18
Appendix A ……………………………………………………………………………………19
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PE97240
Evaluation Kit Manual
Introduction
The PE97240 is a high-performance integer-N PLL capable of frequency synthesis up to 5 GHz. The device
is designed for superior phase noise performance for use in commercial space applications. The PE97240
includes a dual modulus prescaler capable of dividing the VCO frequency by either 5/6 or 10/11, depending
on the value of the modulus selected.
The PE97240 PLL Evaluation Kit includes the application software and hardware required to control and
evaluate the functionality of the PLL using a PC running the Windows™ operating system to control the USB
interface board.
Applications Support
For any technical inquiries regarding the evaluation kit or software, please visit applications support at
www.psemi.com (fastest response) or call (858) 731‐9400.
Evaluation Kit Contents and Requirements
Kit Contents
The PE97240 Evaluation Kit (EVK) includes all of the specific software and hardware required to evaluate the
PLL frequency synthesizer. Included in the EVK are:
Quantity
Description
1
PE97240 Integer-N Evaluation Board Assembly (DOC-50870)
1
Peregrine PLL USB Interface Board Assembly (DOC-02635)
1
USB-A to USB-B mini cable
1
Power cable for PE97240
1
Power cable for the VCO
1
Power cable for the Op Amp loop filter
Software Requirements
The application software will need to be installed on a computer with the following minimum requirements:
 PC compatible with Windows™ XP Vista 7 or 8 (32-bit or 64-bit)
 Mouse
 USB port
 HTML browser with internet access
 Administrative privileges
Hardware Requirements
In order to evaluate the phase noise performance of the evaluation board, the following equipment is
required:
 DC power supplies and DC cables
 External TCXO or other low-noise source
CAUTION: The PE97240 PLL EVK contains components that might be damaged by exposure to voltages in excess of the specified voltage, including voltages produced by
electrostatic discharges. Handle the board in accordance with procedures for handling static-sensitive components. Avoid applying excessive voltages to the power supply
terminals or signal inputs or outputs.
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Document No. DOC-15216-4 │ UltraCMOS® RFIC Solutions
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PE97240
Evaluation Kit Manual
PE97240 PLL Evaluation Board Assembly
Overview
The evaluation board is assembled with a PE97240 integer-N frequency synthesizer, an on-board VCO and a
second order active loop filter. The loop filter is followed by two low pass filters to filter out high frequency
noise. The VCO tuning range is from 2915–3155 MHz. The active loop filter is designed for a 50 MHz
comparison frequency, a 3000 MHz output frequency with unity gain crossover at 200 kHz and a phase
margin of 70 degrees. The 3 dB bandwidth is approximately 250 kHz. The data provided was measured with
an external 100 MHz TCXO for best phase noise performance.
Figure 1. PE97240 Evaluation Board
Showing Front-side Assembly
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Figure 2. PE97240 Evaluation Board Showing
Back-side Assembly
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PE97240
Evaluation Kit Manual
USB Interface Board
USB Interface Board Overview
Figure 3. PLL USB Interface Board
A USB interface board (Figure 3) is included in
the EVK. The board allows the user to send
SPI commands to the device under test by
using a PC running the Windows™ operating
system. To install the software, simply extract
the zip file to a temporary directory and follow
the installation procedure included.
Connection of the USB Interface
Board to the Evaluation Board
The evaluation board and the USB interface
board contain a keyed 16-pin header. This
feature allows the USB interface board (socket)
to connect directly to the evaluation board (pin)
on the front side, as shown in Figure 4.
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Figure 4. PLL USB Interface Board Connected to
the PE97240 Evaluation Board for
Serial Programming
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PE97240
Evaluation Kit Manual
EVK Software Installation
In order to evaluate the PE97240 performance using serial programming mode, the application software has
to be installed on your computer. The USB interface and PLL application software is compatible with
computers running Windows™ XP Vista 7 or 8 (32-bit or 64-bit configurations). This software is available
directly from Peregrine’s website at www.psemi.com.
To install the PLL evaluation software, unzip the
archive and execute the “setup.exe.”
Figures 5(a-c). Application Software Installation
Procedure
After the setup.exe file has been executed, a
welcome screen will appear. It is strongly
recommended that all programs be closed prior to
running the install program. Click the “Next>”
button to proceed.
Take a moment to read the license agreement,
then click “I Agree” and “Next>.”
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PE97240
Evaluation Kit Manual
For most users the default install location for the
program files is sufficient. If a different location is
desired, the install program can be directed to
place the program files in an alternate location.
The software is installed for “Everyone” by
default. Once the desired location is selected,
click “Next >.”
Figures 5(d-f). Application Software Installation
Procedure
The next installation screen starts the installation
process. If the PLL application software is
already installed, the installer will update the files
to the newest version.
As the software files are installed, a progress
indicator will be displayed. On slower computers,
installation of the software may proceed for a
few moments.
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PE97240
Evaluation Kit Manual
Once the evaluation software is installed, click
“Finish” to exit.
Figure 5(g). Application Software Installation
Procedure
A new Start Menu item under Peregrine
Semiconductor will appear in the start menu of
your computer. Select “PLL Hi-Rel Evaluation
Software” to launch the GUI.
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PE97240
Evaluation Kit Manual
Using the Application Software Graphical User Interface
Figure 6 displays the PLL application software graphical user interface (GUI), which has the USB interface
board plugged into the computer. See “Hardware Operation” for the EVK hardware configuration to use with
the GUI control software. If the USB interface board is not connected when the application software is
launched, the message “The USB interface board is not connected. Please connect it and restart the
program.” will appear at the bottom of the screen.
In the upper left corner, under the Peregrine logo, there is a drop-down menu item to select the part for
evaluation and the part description is right below the part number box. This is an important drop-down item,
as it determines which serial peripheral interface and telegram structure the program will send to the parts
under test. It is important to select the part being evaluated. Selecting the wrong part number may result in
sending improper commands to the PLL under test, yielding unpredictable test results.
Once the part number to test has been selected, the part number will appear in place of the Select Part
location on the GUI. The software is now ready to use.
Figure 6. PLL Application Software Graphical User Interface (GUI)
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PE97240
Evaluation Kit Manual
Figure 7. PLL GUI Control Bits
Prescaler
Enabling the prescaler control bit activates the 5/6 or 10/11 prescaler. The prescaler can be set to either a 5/6
or 10/11 modulus based on the Mod Select pin. Disabling the prescaler control bit allows FIN to bypass the
5/6 or 10/11 modulus. In this mode, the prescaler and A counter are powered down and the input VCO frequency is divided by the M counter directly.
Mod Select
Selects prescaler modulus of 5/6 or 10/11.
ENH
Enhancement mode. When enabled “Low” the enhancement register bits become functional. The enhancement mode control bit needs to be held “High” (disabled) during normal operation under all programming
modes. Setting the control bit “Low” will either put the part into a shutdown state and the phase detector output will have no output pulse, or it will go into a reset state and the phase detector will have no output pulse,
similar to the shutdown state. Refer to Table 9 in the PE97240 datasheet for the enhancement register bit
functionality.
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PE97240
Evaluation Kit Manual
Evaluation Board Overview
Figure 8. PE97240 Evaluation Board Schematic*
VDD
8
7
6
5
4
3
2
1
1
2
3
4
5
6
7
8
11
9
7
5
3
1
7
5
3
1
1
2
3
4
5
6
7
8
7
5
3
1
18
16
14
12
10
8
6
4
2
9
10
11
12
13
14
15
16
R5
220
R2
220
16
15
14
13
12
11
10
9
VDD
16
15
14
13
12
11
10
9
VDD
R1
220
JP2
JP1
HEADER4X2
HEADER 6X2
12
10
8
6
4
2
8
6
4
2
17
15
13
11
9
7
5
3
1
8
6
4
2
JP5
JP4
HEADER_9X2
HEADER4X2
FR
VDD
CA1-D
GND
11
GND
NC
12
26
GND
NC
13
9
M0
9
1
1
VDD_PD
35
36
FR 37
GND
VDD_E
ENH 39
VDD_R 38
42
43
40
R0
R1
R2
34
TP5
1
27
FIN 25
10
VDD_E_C
11
GND
3
12
VDD_P
24
PRE_5/6_SEL
23
TP4
C3
C2
2
22pF
C4
22pF
22pF
6
10
VDD
C1
100pF
FIN 26
100pF
CA2-B
100pF
CA2-A
100pF
DNI
1
GND
25
4
R9
PRE_ENB
24
100pF
CA2-C
8
GND
1
22
10
PE97240 44Lead Ceramic FlatPk
VDD_E_C
9
NC
M1
A2
8
NC
GND
M2
8
DOUT 28
21
NC
GND
23
M3
7
30
CEXT 29
20
GND
22
5
PD_U
PD_D
TP3
LD
TP2
32
VDD_O 31
U1
A1/EW_R
21
CA2-D
7
GND
6
A0
7
E_WR 6
A3
5
DIRECT
PRE_5/6_SEL
4
19
GND
1
2
3
4
5
6
7
8
18
GND
20
16
15
14
13
12
11
10
9
17
GND
19
6
ENH 5
18
2
M4/S_WR
10
16
100pF
CA1-A
100pF
R5
M5/SDATA
3
S_WR 4
3
TP1
PD_U 33
PD_D
M7
2
S_DATA
NC
R4
M8
S_CLK
NC
17
2
14
NC
16
3
VDD_E_C
13
15
9
220
1
R3
44
CA1-B
1
1
NC
NC
R7
1
14
4
100pF
15
J1
HEADER 26
GND
8
41
5
100pF
CA1-C
M6/SCLK
7
J7
VERT.
R10
R11
R14
51 ohm
51 ohm
DNI
1
DNI
DNI
R15
R12
0
CENTER
R13
DNI
16 GND
ENH 15
14 GND
NC 13
12 GND
NC 11
10 GND
PRE_5/6 9
8 GND
E_WR 7
6 GND
S_WR 5
4 GND
SDATA 3
R8
220
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
F_IN_OUT
SCLK 1
2 GND
HEADER 16
J2
D4
2.4V
D3
D5
D6
D7
2.4V
2.4V
2.4V
D8
2.4V
2.4V
TP
TP
MTG4
1
MTG3
VDD
1
2
J3
VCC_PLL
C6
0.01uF
C7
100pF
C8
22pF
C9
0.01uF
C10
100pF
C11
22pF
C12
0.01uF
C13
100pF
C14
22pF
2
1
1
TP
TP
1
MTG2
1
MTG1
C5
470UF
HEADER 2
Note: *
Use 101-0746-01
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DOC-50870
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PE97240
Evaluation Kit Manual
Evaluation Board Overview
Figure 8. PE97240 Evaluation Board Schematic (cont.)
J4
0.01uF
SMASM
R19
750
2.7nF
-VCC
C25
22pF
2
100pF
VCC_VCO
C29
C28
470UF
+ C30
DNI
100pF
J8
HEADER 2
R37
DNI
SMASM
4
1
8
R25
C34
2 -
390
3 +
C35
C15
R30
6
R22
100
AD797AR
C31
1nF
C32
100pF
R38
VCO
R26
0
R27
22pF
750
16
2
14
DNI
2
14
16
F_IN_OUT
RF
10
1
1
10
DNI
PLACE COMPONENTS ON BACKSIDE
DNI
JP8
JUMPER 3
C43
1
2
3
DNI
DNI
DNI
2
C45
R31
DNI
Y5
R33
5
0
FR
1 VC
R32
DNI
7 GND
2
100pF
C46
C16
10uF
0.01uF
C39
R29
TCXO
C42
2
1
2
3
4
C40
10uF
C41
RF
VCC 3
VCC_TCXO
1
2
C47
C48
100pF
0.01uF
16
350-700 MHz
V350ME52
Y2
3350 MHz – 4550 MHz
V846ME30-LF
1
2
3
J6
+
VT
FOUT 4
J5
VCC_OPAMP
VT
VCC
2
-VCC
10
2
JP7
DNI
HEADER 4
RF
R28
Y4
DNI
VCC
JP6
1
Y1
DNI
CVC055CC-2850-3210
PLACE COMPONENTS ON BACKSIDE
+VCC
VT
VCC
14
C36
J9
1
VCO OUT
560pF
+
DNI
100
U2
2.7nF
560pF
R23
2
120
390
C44
R24
R21
120
6
0.01uF
PD_D
R20
7
5
PD_U
1
2
LOOP FILTER OUT
1
C24
C27
1
C26
2
LOOP FILTER
R16
R35
R36
DNI
DNI
DNI
DNI
TCXO-VFTX120
PLACE COMPONENTS ON BACKSIDE
SMASM
1RF_XO
REF IN
2
J10
DOC-50870
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PE97240
Evaluation Kit Manual
Evaluation Board Overview
Figure 9. PE97240 Evaluation Board Outline Showing Functional Overview
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PE97240
Evaluation Kit Manual
Hardware Operation
1.
2.
3.
4.
5.
6.
7.
8.
Refer to the test setup shown in Figure 9.
Verify that all DC power supplies are turned off before proceeding.
Connect +2.7V DC and GND to J3 on the evaluation board to power the PE97240.
Connect +5V DC and GND to J4 on the evaluation board to power the VCO.
Connect +15V and -5V DC and GND to J5 on the evaluation board to power the Op Amp.
Connect the reference source (TCXO) to the external reference port (J10).
Connect the phase noise tester to the evaluation board using an RF cable.
Turn on the DC power supplies in the following order:
a. PLL (2.7V)
b. VCO (5V)
c. Op Amp (15V and –5V)
9. Connect from the USB interface board to the computer using the USB cable. The red LED on the USB
interface board should blink a few times indicating that the hardware is recognized.
10. Connect the USB interface board to J2 on the evaluation board.
11. Launch the application software. Once the GUI is open, the red LED on the USB interface board should
remain on. The evaluation software is now ready to use.
12. Select the part to be tested from the menu bar on the GUI.
13. Set the registers values and control bits on the GUI to obtain the required frequency and operation
modes.
14. Click the Program Device button on the GUI to program the PLL.
Figure 10. Suggested Test Setup for Evaluating Phase Noise
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PE97240
Evaluation Kit Manual
EVK Testing Using the Graphical Interface (Example 1)
Figure 11 shows the resulting phase noise measurement with the PE97240 evaluation board operating at a
50 MHz comparison frequency with a 3 GHz VCO and the 5/6 prescaler mode selected.
Figure 11. PE97240 Evaluation Board Test Example 1
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PE97240
Evaluation Kit Manual
EVK Testing Using the Graphical Interface (Example 2)
Figure 12 shows the resulting phase noise measurement with the PE97240 evaluation board operating at a
50 MHz comparison frequency with a 3 GHz VCO and the 10/11 prescaler mode selected.
Figure 12. PE97240 Evaluation Board Test Example 2
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PE97240
Evaluation Kit Manual
Direct Programming Mode
Direct programming mode allows for manual evaluation of the EVK without the application software. However, it is handy to have the GUI open to determine the values of the R, M and A register settings needed. The
counters can then be set directly with on-board jumpers (JP1, JP2, JP4 and JP5), as shown in Figure 12. To
enable direct mode programming, both the ENH and the direct programming jumpers (JP5) should be
installed.
Figure 13. Direct Programming Mode Settings Using 5/6 Prescaler from Test Example 1
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PE97240
Evaluation Kit Manual
Troubleshooting Tips
The message “The USB interface board is not connected. Please connect it and restart the program”
reappears after closing and restarting the application software. Follow these steps:
1.
2.
3.
4.
Close the program. Make sure the USB interface board is connected. Restart the application software.
Verify that the USB interface board is well connected. Remove the USB cable from the computer and
reinsert it. Restart the application software.
Go to http://www.ftdichip.com/Drivers/D2XX.htm and follow the instructions for downloading the latest
version of the D2XX driver software for your computer’s operating system.
Repeat Step 1.
If any of the following occur, go to http://www.ftdichip.com/Drivers/D2XX.htm and follow the instructions for
downloading the latest version of the D2XX driver software for your computer’s operating system.



An error message states the driver software not found for FT232R USB UART.
The application software does not close or causes the computer to lock up.
The application software does not work with Windows 8 or on a 64-bit operating system.
Technical Resources
Additional technical resources are available for download in the Products section at www.psemi.com. These
include the Product Specification datasheet, Evaluation Kit schematic and Bill of Materials, PC-compatible
software file, Evaluation Kit instruction manual, phase noise loop filter calculation spreadsheet and application
notes.
Trademarks are subject to trademark claims.
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PE97240
Evaluation Kit Manual
Appendix A
The PE97240 is characterized using a 100 MHz, ultra low noise OCXO frequency reference. An exceptionally
clean reference oscillator will ensure that the reference noise does not limit the phase noise measurement
results. The following table shows the typical phase noise of the OCXO operating at 100 MHz.
Sales Contact and Information
Contact Information:
e2v ~ http://www.e2v-us.com ~ inquiries@e2v-us.com
Advance Information: The product is in a formative or design stage. The datasheet contains design target
specifications for product development. Specifications and features may change in any manner without notice.
Preliminary Specification: The datasheet contains preliminary data. Additional data may be added at a later
date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best
possible product. Product Specification: The datasheet contains final data. In the event Peregrine decides to
change the specifications, Peregrine will notify customers of the intended changes by issuing a CNF (Customer
Notification Form).
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The information in this datasheet is believed to be reliable. However, Peregrine assumes no liability for the use
of this information. Use shall be entirely at the user’s own risk.
No patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party.
Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant,
or in other applications intended to support or sustain life, or in any application in which the failure of the
Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no
liability for damages, including consequential or incidental damages, arising out of the use of its products in
such applications.
The Peregrine name, logo, UltraCMOS and UTSi are registered trademarks and HaRP, MultiSwitch and DuNE
are trademarks of Peregrine Semiconductor Corp. Peregrine products are protected under one or more of the
following U.S. Patents: http://patents.psemi.com.
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