Ordering number : ENA1408B
LV49152V
Bi-CMOS LSI
Class-D Audio Power Amplifier
BTL 15W × 2ch
http://onsemi.com
Overview
The LV49152V is a 15W per channel stereo digital power amplifier that takes analog inputs. The LV49152V uses
unique Our developed feedback technology to achieve excellent audio quality despite being a class D amplifier and can
be used to implement high quality flat display panel (FDP) based systems.
Features
• BTL output, class D amplifier system
• Unique Our developed feedback technology achieves superb audio quality
• High-efficiency class D amplifier
• Soft muting function reduces impulse noise at power on/off
• Full complement of built-in protection circuits : over current protection, thermal protection, and low power supply
voltage protection circuits
• Built in Power limiter
Functions
• Power
: 15W × 2ch output (VD = 15V, RL = 8Ω, fin = 1kHz, AES17, THD + N = 10%)
• Efficiency : 93% (VD = 15V, RL = 8Ω, fin = 1kHz, PO = 15W)
• THD + N : 0.08% (VD = 15V, RL = 8Ω, fin = 1kHz, PO = 1W, Filter : AES17)
• Noise
: 90μVrms (Filter : A-weight)
• Package SSOP44J (275mil)
Semiconductor Components Industries, LLC, 2013
May, 2013
N0409 SY / 40109 MS 20090312-S00013 / 21809 MS PC No.A1408-1/24
LV49152V
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter
Symbol
Conditions
Maximum supply voltage
VD
Supply voltage
Allowable power dissipation
Pd max
Package thermal resistance
θjc
Maximum junction temperature
Tj max
Operating temperature
Storage temperature
Ratings
Unit
20
V
Our PCB, Soldered *
5.05
W
Our PCB, Soldered *
2.1
°C/W
3.6
°C/W
150
°C
Topr
-25 to +75
°C
Tstg
-50 to +150
°C
Our PCB, Not soldered *
* : Mounted on a specified board 110.0mm × 100.0mm × 1.5mm, glass epoxy (two-layer)
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Recommended Operating Range at Ta = 25°C
Ratings
Parameter
Symbol
Conditions
Unit
min
typ
max
Supply voltage range
VD
Supply voltage
9
15
Load impedance range
RL
Speaker load
4
8
18
V
Ω
Electrical Characteristics at Ta = 25°C, VD = 15V, RL = 8Ω, L = 33μH (TOKO : A7502BY-330M), C = 0.1μF,
CL = 0.47μF
Ratings
Parameter
Symbol
Conditions
Unit
min
typ
max
Standby current
Ist
STBY = L, MUTE = L
1
10
μA
Mute current
Imute
STBY = H, MUTE = L
14
20
26
mA
Quiescent current
ICCO
STBY = H, MUTE = H
35
45
55
mA
Voltage gain
VG
fin = 1kHz, VO = 0dBm
28
30
32
dB
Offset voltage
Voffset
Rg = 0
150
mV
-150
Total harmonic distortion
THD+N
PO = 1W, fin = 1kHz, AES17
Output power
PO@10%
THD+N = 10%, AES17
13
0.08
15
0.4
W
Channel separation
CHsep.
Rg = 0, VO = 0dBm, DIN AUDIO
55
70
dB
Ripple rejection ratio
SVRR
fr = 100Hz, Vr = 0dBm, Rg = 0, DIN AUDIO
50
Noise
VNO
Rg = 0, A-weight
High-level input voltage
VIH
STBY and MUTE pin
3
Low-level input voltage
VIL
STBY and MUTE pin
0
Under voltage protection UPPER
UV_UPPER
VD voltage measure
8.0
V
Under voltage protection LOWER
UV_LOWER
VD voltage measure
7.0
V
60
90
%
dB
300
μVrms
VD
V
1
V
Note : The values of these characteristics were measured in the Our test environment. The actual values in an end system will vary depending on the printed
circuit board pattern, the external components actually used, and other factors.
No.A1408-2/24
LV49152V
Package Dimensions
unit : mm (typ)
3285
TOP VIEW
BOTTOM VIEW
Exposed Die-Pad
15.0
23
0.5
5.6
7.6
44
1
22
0.22
0.65
0.2
1.7max
(0.68)
(1.5)
SIDE VIEW
SANYO : SSOP44J(275mil)
Allowable power dissipation, Pd max - W
8
Pd max - Ta
Mounted on a specified board : 110.0 × 100.0 × 1.5mm3
glass epoxy (two-layer)
6
Soldered = 5.05W
4
Not Soldered = 3.35W
2
0
—25
0
25
50
75
100
125
150
Ambient temperature, Ta - C
PVD1
PVD1
OUT1+
OUT1+
BOOT1+
VDD1
BOOT1-
OUT1-
OUT1-
PGND1
PGND1
PGND2
PGND2
OUT2-
OUT2-
BOOT2-
VDD2
BOOT2+
OUT2+
OUT2+
PVD2
PVD2
Pin Assignment
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
MUTE
STBY
VIN1+
VIN1-
PLC
VIN2-
VIN2+
MUTECAP
VCC
BIASCAP
VBIAS
VREG5
GND
NC
NC
NC
NC
NC
NC
NC
NC
NC
LV49152
Top view
No.A1408-3/24
LV49152V
Block Diagram and Application Circuit Example 1 (RL = 8Ω)
470μF
+
0-5V
1
2
0-5V
1μF
VIN1+
1μF
1μF
VIN
2+
+
1μF
1μF
4
6
8
9
10
1μF
11
1μF
PVD1
FB
12
1μF
13
14
15
16
17
18
19
20
21
22
1μF
44
43
42
VIN1PLC
OUTPUT
41
REC. & CONT.
40
VIN2-
VDD1
7
22μF
1μF
STBY
3
5
0 to 20kΩ
PVD1
MUTE
37
OUTPUT
VCC
BIASCAP
36
FB
PGND1
VBIAS
VREG5
GND
PGND1
START
SEQUENCE
POWER LIMITER
PGND2
PGND2
FB
NC1
NC4
REC. & CONT.
26
OUTPUT
NC7
NC8
NC9
25
FB
PVD2
PVD2
OUT1-
RL
0.1μF
0.1μF
OUT133μH
VD
OUT2-
33μH
OUT20.1μF
BOOT20.22μF
0.1μF
0.47μF
28
27
NC6
0.47μF
BOOT1-
32
29
NC5
0.1μF
33
30
VDD2
0.1μF
0.22μF
34
OUTPUT
NC3
BOOT1+
35
31
NC2
33μH
OUT1+
39
38
MUTECAP
OUT1+
RL
BOOT2+
OUT2+
0.1μF
0.1μF
OUT2+
33μH
24
23
1μF
+
470μF
No.A1408-4/24
LV49152V
Application Circuit Example 2 (RL = 6Ω)
470μF
+
0-5V
1
2
0-5V
1μF
VIN1+
1μF
1μF
VIN
2+
+
1μF
1μF
4
6
8
9
10
1μF
11
1μF
PVD1
FB
12
1μF
13
14
15
16
17
18
19
20
21
22
1μF
44
43
42
VIN1PLC
OUTPUT
41
REC. & CONT.
40
VIN2-
VDD1
7
22μF
1μF
STBY
3
5
0 to 20kΩ
PVD1
MUTE
37
OUTPUT
VCC
BIASCAP
36
FB
PGND1
VBIAS
VREG5
GND
PGND1
START
SEQUENCE
POWER LIMITER
PGND2
PGND2
FB
NC1
NC4
REC. & CONT.
26
OUTPUT
NC7
NC8
NC9
25
FB
PVD2
PVD2
OUT1-
RL
0.1μF
0.15μF
OUT122μH
VD
OUT2-
22μH
OUT20.1μF
BOOT20.22μF
0.15μF
0.68μF
28
27
NC6
0.68μF
BOOT1-
32
29
NC5
0.15μF
33
30
VDD2
0.1μF
0.22μF
34
OUTPUT
NC3
BOOT1+
35
31
NC2
22μH
OUT1+
39
38
MUTECAP
OUT1+
RL
BOOT2+
OUT2+
0.1μF
0.15μF
OUT2+
22μH
24
23
1μF
+
470μF
No.A1408-5/24
LV49152V
Application Circuit Example 3 (RL = 4Ω)
470μF
+
0-5V
1
2
0-5V
1μF
VIN1+
1μF
1μF
VIN
2+
+
1μF
1μF
4
6
8
9
10
1μF
11
1μF
PVD1
FB
12
1μF
13
14
15
16
17
18
19
20
21
22
1μF
44
43
42
VIN1PLC
OUTPUT
41
REC. & CONT.
40
VIN2-
VDD1
7
22μF
1μF
STBY
3
5
0 to 20kΩ
PVD1
MUTE
37
OUTPUT
VCC
BIASCAP
36
FB
PGND1
VBIAS
VREG5
GND
PGND1
START
SEQUENCE
POWER LIMITER
PGND2
PGND2
FB
NC1
NC4
REC. & CONT.
26
OUTPUT
NC7
NC8
NC9
25
FB
PVD2
PVD2
OUT1-
RL
0.1μF
0.22μF
OUT115μH
VD
OUT2-
15μH
OUT20.1μF
BOOT20.22μF
0.22μF
1μF
28
27
NC6
1μF
BOOT1-
32
29
NC5
0.22μF
33
30
VDD2
0.1μF
0.22μF
34
OUTPUT
NC3
BOOT1+
35
31
NC2
15μH
OUT1+
39
38
MUTECAP
OUT1+
RL
BOOT2+
OUT2+
0.1μF
0.22μF
OUT2+
15μH
24
23
1μF
+
470μF
No.A1408-6/24
LV49152V
Pin Equivalent Circuit
Pin No.
1
Pin name
MUTE
I/O
I
Description
Equivalent Circuit
Mute control pin
VD
250kΩ
1
10kΩ
100kΩ
GND
2
STBY
I
Standby control pin
VD
250kΩ
2
10kΩ
100kΩ
GND
3
VIN1+
I
Input pin, CH1 plus
VD
3
300Ω
30kΩ
VBIAS
GND
4
VIN1-
I
Input pin, CH1 minus
VD
4
300Ω
30kΩ
VBIAS
GND
5
PLC
I
Power level control pin
VD
5
200Ω
GND
Continued on next page.
No.A1408-7/24
LV49152V
Continued from preceding page.
Pin No.
6
Pin name
VIN2-
I/O
I
Description
Equivalent Circuit
Input pin, CH2 minus
VD
300Ω
6
30kΩ
VBIAS
GND
7
VIN2+
I
Input pin, CH2 plus
VD
300Ω
7
30kΩ
VBIAS
GND
8
MUTECAP
O
Muteing sysytem capcitor connection
VD
VDD
20kΩ 10kΩ
8
GND
9
VCC
O
Internal power supply
VD
decupling capacitor connection
9
GND
10
BIASCAP
O
Internal regulator
VD
decupling capacitor connection
100kΩ
10
1kΩ
1kΩ
100kΩ
GND
Continued on next page.
No.A1408-8/24
LV49152V
Continued from preceding page.
Pin No.
11
Pin name
VBIAS
I/O
O
Description
Equivalent Circuit
Internal regulator
VD
decupling capacitor connection
500Ω
11
500Ω
GND
12
VREG5
O
Internal regulator
VD
decupling capacitor connection
12
500Ω
GND
13
GND
Analog Ground
14
NC
Non connection
15
NC
Non connection
16
NC
Non connection
17
NC
Non connection
18
NC
Non connection
19
NC
Non connection
20
NC
Non connection
21
NC
Non connection
22
NC
Non connection
23
PVD2
CH2 power supply
24
PVD2
25
OUT2+
CH2 power supply
O
Output pin, CH2 plus
VD
25
GND
26
OUT2+
O
Output pin, CH2 plus
VD
26
GND
Continued on next page.
No.A1408-9/24
LV49152V
Continued from preceding page.
Pin No.
Pin name
BOOT2+
I/O
27
28
VDD2
O
I/O
Description
Equivalent Circuit
Boot strap pin, CH2 plus
CH2 internal regulator decupling capacitor
connection
29
BOOT2-
I/O
Boot strap pin, CH2 minus
30
OUT2-
O
Output pin, CH2 minus
VD
30
GND
31
OUT2-
O
Output pin, CH2 minus
VD
31
GND
32
PGND2
CH2 Power Ground
33
PGND2
CH2 Power Ground
34
PGND1
CH1 Power Ground
35
PGND1
36
OUT1-
CH1 Power Ground
O
Output pin, CH1 minus
VD
36
GND
37
OUT1-
O
Output pin, CH1 minus
VD
37
GND
38
BOOT1-
I/O
39
VDD1
O
Boot strap pin, CH1 minus
CH1 internal regulator decupling capacitor
connection
40
BOOT1+
I/O
Boot strap pin, CH1 plus
Continued on next page.
No.A1408-10/24
LV49152V
Continued from preceding page.
Pin No.
41
Pin name
OUT1+
I/O
O
Description
Output pin, CH1 plus
Equivalent Circuit
VD
41
GND
42
OUT1+
O
Output pin, CH1 plus
VD
42
GND
43
PVD1
CH1 power supply
44
PVD1
CH1 power supply
No.A1408-11/24
LV49152V
Operation Mode Summary
STBY mode (STBY = L and MUTE = L)
Each bias becomes off state when the regulator in IC has been turned off.
The most of circuits becomes off state.
The supply current : 1μA (typical).
MUTE mode (STBY = H and MUTE = L)
Each bias becomes on state when the regulator in IC has been turned on.
When more than half of the circuits are active, the amplifier in the output stages become off.
The supply current : 20mA (typical).
Operation mode (STBY = H and MUTE = H)
The LV49152V operates as D-class amplifier.
The output signal is synchronized with the input signal.
The supply current : 45mA (typical)
Function image
No.A1408-12/24
LV49152V
ON TIME/OFF TIME
ON TIME
Please secure ON TIME of 350msec or more for reducing Pop noise.
Function image
ON TIME • • • the time until the MUTE pin is set to high level after the STBY pin is set to high level
OFF TIME
Please secure OFF TIME of 1000msec or more for reducing Pop noise.
Function image
OFF TIME • • • the time until the STBY pin is set to low level after the MUTE pin is set to low level
No.A1408-13/24
LV49152V
SOFT MUTE
The soft mute circuit is able to use fade in/fade out function, and can set Rise time and fall time by the time constant of the
MUTECAP capacitor.
FADE IN
Mute rise time is Applpx.450msec in our recommended external components.
5V/DIV.
MUTE pin
MUTECAP pin
[OUT+] vs [OUT-]
Mute rise time
Function image
FADE OUT
Mute fall time is Applpx.450msec in our recommended external components.
5V/DIV.
MUTE pin
MUTECAP pin
[OUT+] vs [OUT-]
Mute fall time
Function image
No.A1408-14/24
LV49152V
Power supply lowering protection circuit
Since the instable operation in the low voltage is prevented by using this circuit, after the voltage of the PVD pin is
monitored and the voltage below the Attack voltage (PVD = 8V typ.), AMP is turned off.
Also, to prevent the instable operation when the voltage of the PVD pin is decreased by any cause during operations, the
Attack voltage (PVD = 7V typ.) is set.
The voltage of Attack and Recover has hysteresis (About 1V) to prevent ON/OFF continuous action of the power supply
lowering protection circuit.
Function image
Also, this IC is designed to turn off AMP in the same sequence that the MUTE is on as a pop noise measures when the
plug of products are put off.
Over current protection circuit
The over current protection circuit is a protection circuit * to protect the output DMOS from the over current and
corresponds to any mode of the power supply, GND and a load short.
The protection operation is performed when the current reaches the detection current value set out in IC and the output
DMOS is compulsorily turned off for about 20μsec.
After compulsorily tuning off the output DMOS, when the Amplifier is automatically reset in usual operation and the over
current flows continuously, the protection operation is performed again.
Function image
* The over current protection circuit is a function to avoid the abnormal state like the output short-circuit temporarily.
Unfortunately, we cannot guarantee that IC is not destroyed.
No.A1408-15/24
LV49152V
Thermal protection circuit
The LV49152V includes a thermal protection circuit to prevent damage to or destruction of the IC should abnormal
internal heat generation occur.
This means that should the IC junction temperature (Tj) rise above about 175°C due to inadequate heat dissipation or
other reason, the thermal protection circuit will operate to stop IC operation should the temperature rise further.
If the temperature is reduced by lowering the input level or other means, the thermal protection circuit will recover
automatically (about 105°C).
Recovery
Attack
Hystsrisis
Temperature (Tj) rise
Internal
TSD DET.
Shut
down
PWM
Internal
TSD DET.
Temperature (Tj) fall
Shut down
PWM
40
50
60
70
80
90
100 110 110 130 110 150 160 170 180 190 200
Junction temperature Tj [°C]
Function image
* The thermal protection circuit is a function to avoid the abnormal state temporarily.
Unfortunately, we cannot guarantee that IC is not destroyed.
No.A1408-16/24
LV49152V
PLC
The PLC (power level control) function is able to control the maximum index modulation by setting a value of external
PLC resistance R1 voluntarily, and prevent a PWM signal from becoming the over modulation mode. In addition, this
circuit can be use as output power limit circuit because the PLC function can set the maximum index modulation
voluntarily, and variable from 2W to 15W with output power linearly in the state that made the power supply voltage and
load resistance fixation. Because the PLC function can set the suitable rated output with the same power supply
voltage/speaker regardless of screen size in flat screen televisions by this, set can plan the commonization of the board.
Furthermore, The PLC function can reduce abnormal noise in the hard clip so that output wave pattern becomes the soft
clip when it limited output power.
MAX. Power
Half Power
Min. Power
PLC
R1
5
LV49152V
1μF
GND
13
Function image
Measuring condition
VD = 15V, RL = 8Ω, L = 33μH (TOKO : A7502BY-330M), C = 0.1uF,CL = 0.47μF,Ta = 25°C
R1 -- PO@THD + N = 10%
18
R1 [kΩ]
Po@10% [W]
3.0
0.694
3.6
1.073
4.7
1.982
6.2
3.642
10
7.5
5.562
8
8.2
6.855
9.1
8.591
10
10.64
VD = 15V
RL = 8Ω
fin = 1kHz
THD + N = 10%
2ch-Drive
AES17
PO@THD + N = 10% – W
16
14
12
6
4
13
15.32
2
15
15.94
0
20
16.01
0
2
4
6
8
10
12
14
16
18
20
R1 – kΩ
Setting example of the output power limit value
* When it is used this function as output power limit, please use the high-precision resistance such as the metal film
resistor when precision of the electricity value is necessary.
* The value of external PLC resistance R1 please connects more than 3kΩ.
* When it is changed a value of external PLC resistance R1, please turn off an amplifier.
No.A1408-17/24
LV49152V
Cut-off frequency calculation method and the output LC filter setting
L
OUT+
C
CL
RL
C
L
OUT-
The cut off frequency fc of the output LC filter is calculated by the following formula.
fc =
1
2π√2LCL
Also, by setting the cut off frequency fc, the value of CL and L is calculated by using the following formula.
1
CL =
2√2 × π RLfc
L=
√2 × RL
4π fc
In general, the value from 20% to 30% of CL is set to C.
In case of fc = 30kHz
RL [Ω]
L [μH]
CL [μF]
C [μF]
Q
4
15
1
0.22
0.650
6
22
0.68
0.15
0.636
8
33
0.47
0.1
0.704
16
68
0.22
0.047
0.739
Above formula is common calculation method and is a measure of constant setting.
In fact, it is necessary to set with each set that considers the speaker characteristics.
In addition, please set the fixed number to become Q ≤ 1 in currents in the fc neighborhood increasing if Q value of the LC
filter is big.
No.A1408-18/24
LV49152V
Glaph deta
L = 33μH (TOKO : A7502BY-330M), C = 0.1μF, CL = 0.47μF
Ist -- VD
0.15
RL = 8Ω
Rg = 0
STBY = L
MUTE = L
Standby current, Ist – μA
Standby current, Ist – μA
0.15
0.1
0.05
0
0
2
4
6
8
10
12
14
16
Ist -- Ta
VD = 15V
RL = 8Ω
Rg = 0
STBY = L
MUTE = L
0.1
0.05
0
– 50
18
Externally applied voltage, VD – V
Imute -- VD
20
15
10
5
0
0
2
4
6
8
10
12
14
16
15
10
5
VD = 15V
RL = 8Ω
Rg = 0
STBY = H
MUTE = L
0
– 50
18
ICC -- VD
Quiescent current, ICC – mA
Quiescent current, ICC – mA
20
10
0
2
4
6
8
10
12
14
16
30
20
10
VD = 15V
RL = 8Ω
Rg = 0
STBY = H
MUTE = H
0
– 50
18
0
50
100
Ambient temperature, Ta – °C
VCC -- VD
20
RL = 8Ω
Rg = 0
15
VCC -- Ta
VD = 15V
RL = 8Ω
Rg = 0
15
VCC – V
VCC – V
100
40
Externally applied voltage, VD – V
20
50
ICC -- Ta
50
30
0
0
Ambient temperature, Ta – °C
RL = 8Ω
Rg = 0
STBY = H
MUTE = H
40
100
20
Externally applied voltage, VD – V
50
50
Imute -- Ta
25
RL = 8Ω
Rg = 0
STBY = H
MUTE = L
Muting current, Imute – mA
Muting current, Imute – mA
25
0
Ambient temperature, Ta – °C
10
5
10
5
0
0
2
4
6
8
10
12
14
Externally applied voltage, VD – V
16
18
0
– 50
0
50
100
Ambient temperature, Ta – °C
No.A1408-19/24
LV49152V
BIASCAP -- VD
10
10
RL = 8Ω
Rg = 0
8
BIASCAP – V
BIASCAP – V
8
6
4
2
BIASCAP -- Ta
VD = 15V
RL = 8Ω
Rg = 0
6
4
2
0
0
2
4
6
8
10
12
14
16
0
– 50
18
Externally applied voltage, VD – V
VBIAS -- VD
10
10
RL = 8Ω
Rg = 0
8
VBIAS – V
VBIAS – V
8
6
4
0
0
VBIAS -- Ta
VD = 15V
RL = 8Ω
Rg = 0
6
4
2
4
6
8
10
12
14
16
0
– 50
18
Externally applied voltage, VD – V
5
4
4
VREG5 – V
5
3
3
2
2
1
1
4
6
8
10
12
14
16
VD = 15V
RL = 8Ω
Rg = 0
0
– 50
0
2
18
Externally applied voltage, VD – V
6
RL = 8Ω
Rg = 0
5
4
4
VDD – V
5
3
2
1
1
0
2
4
6
8
10
12
14
Externally applied voltage, VD – V
100
50
16
18
VDD -- Ta
VD = 15V
RL = 8Ω
Rg = 0
3
2
0
0
Ambient temperature, Ta – °C
VDD -- VD
6
100
50
VREG5 -- Ta
6
RL = 8Ω
Rg = 0
0
0
Ambient temperature, Ta – °C
VREG5 -- VD
6
VREG5 – V
100
50
2
2
VDD – V
0
Ambient temperature, Ta – °C
0
– 50
0
100
50
Ambient temperature, Ta – °C
No.A1408-20/24
LV49152V
VG -- VD
32
32
RL = 8Ω
fin = 1kHz
VO = 0dBm
31
Gain, VG – dB
Gain, VG – dB
31
30
VG -- Ta
VD = 15V
RL = 8Ω
fin = 1kHz
VO = 0dBm
30
29
29
28
9
12
15
28
– 50
18
Externally applied voltage, VD – V
THD+N -- VD
5
3
2
CH2
0.1
7
CH1
5
3
2
0.01
7
5
RL = 8Ω
fin = 1kHz
PO = 1W
2ch-Drive
AES17
3
2
0.001
9
12
15
5
3
2
CH2
0.1
7
CH1
5
3
2
0.01
7
5
3
2
VD = 15V
RL = 8Ω
fin = 1kHz
PO = 1W
2ch-Drive
AES17
0.01
– 50
18
Externally applied voltage, VD – V
Channel separation, CHsep. – dB
Channel separation, CHsep. – dB
– 50
RL = 8Ω
fin = 1kHz
Rg = 0
VO = 0dBm
DIN AUDIO
– 60
0
– 70
CH1→CH2
– 60
CHsep. -- Ta
VD = 15V
RL = 8Ω
Rg = 0
VO = 0dBm
DIN AUDIO
– 70
CH1→CH2
CH2→CH1
CH2→CH1
– 80
– 50
– 80
9
12
15
18
Externally applied voltage, VD – V
Ripple rejection ratio, SVRR – dB
Ripple rejection ratio, SVRR – dB
0
RL = 8Ω
fin = 100Hz
Rg = 0
VDr = 0dBm
DIN AUDIO
– 20
– 40
CH1
– 60
CH2
– 80
9
12
15
Externally applied voltage, VD – V
0
100
50
Ambient temperature, Ta – °C
SVRR -- VD
0
100
50
Ambient temperature, Ta – °C
CHsep. -- VD
– 50
100
50
THD+N -- Ta
1
7
Total harmonic distortion, THD+N – %
Total harmonic distortion, THD+N – %
1
7
0
Ambient temperature, Ta – °C
18
– 20
SVRR -- Ta
VD = 15V
RL = 8Ω
Rg = 0
VDr = 0dBm
DIN AUDIO
– 40
CH1
– 60
CH2
– 80
– 50
0
100
50
Ambient temperature, Ta – °C
No.A1408-21/24
LV49152V
VNO -- VD
1
Noise, VNO – mVrms
5
7
5
Noise, VNO – mVrms
7
VNO -- Ta
1
RL = 8Ω
Rg = 0
A-weight
3
2
CH2
CH1
0.1
7
5
3
2
3
VD = 15V
RL = 8Ω
Rg = 0
Rplc = 20kΩ
A-weight
2
CH2
0.1
7
CH1
5
3
2
0.01
9
12
0.01
– 50
18
15
0
Externally applied voltage, VD – V
fO -- VD
450
RL = 8Ω
Rg = 0
Oscillating frequency, fO – kHz
Oscillating frequency, fO – kHz
450
400
CH1
350
CH2
300
12
9
15
fO -- Ta
400
CH1
350
CH2
300
– 50
18
0
40
DUTY – %
DUTY – %
CH2
CH1
50
CH1
40
30
30
20
20
10
10
12
9
15
VD = 15V
RL = 8Ω
Rg = 0
0
– 50
0
18
0
Externally applied voltage, VD – V
32
28
RL
100
7
5
3
2
Ω
=4
RL
24
=6
Ω
RL
20
Output power, PO – W
fin = 1kHz
THD+N = 10%
2ch-Drive
AES17
50
100
Ambient temperature, Ta – °C
PO -- VD
36
Output power, PO – W
100
DUTY -- Ta
60
CH2
50
50
Ambient temperature, Ta – °C
DUTY -- VD
RL = 8Ω
Rg = 0
100
VD = 15V
RL = 8Ω
Rg = 0
Externally applied voltage, VD – V
60
50
Ambient temperature, Ta – °C
Ω
=8
16
12
8
4
0
10
7
5
3
2
PO -- VIN
VD = 15V
fin = 1kHz
2ch-Drive
AES17
RL
=
4Ω
RL
1
7
5
3
2
=
8Ω
0.1
7
5
3
2
0.01
9
12
15
Externally applied voltage, VD – V
18
10
2
3
5
7
100
2
3
Input voltage, VIN – mVp
5
7 1000
No.A1408-22/24
1
7
5
Total harmonic distortion, THD+N – %
3
2
THD+N -- PO
VD = 15V
RL = 8Ω
2ch-Drive
AES17
Hz
7k
fin
3
2
.6
=6
Hz
0.1
7
5
fin
3
2
k
=1
fin =
z
100H
0.01
0.001 2 3 5 70.01 2 3 5 7 0.1 2 3 5 7 1
Total harmonic distortion, THD+N – %
Output power, PO – W
10
7
5
3
2
3
2
fin =
0.1
7
5
3
2
z
kH
7
6.6
=
L = 22μH
C = 0.15μF
CL = 0.68μF
z
1kH
z
100H
fin =
0.01
0.001 2 3 5 70.01 2 3 5 7 0.1 2 3 5 7 1
Total harmonic distortion, THD+N – %
3
2
Hz
fin
=
k
.67
6
3
2
3
2
Hz
1k
fin =
L = 15μH
C = 0.22μF
CL = 1μF
fin =
0.01
0.001 2 3 5 70.01 2 3 5 70.1 2 3 5 7 1
Hz
100
1
7
5
3
2
2 3 5 7100
5 7 100
5 7 1k
2 3
0.01
7
5
3
2
10
7
5
3
2
1
7
5
3
2
2 3
5 7100k
CH1
CH2
L = 22μH
C = 0.15μF
CL = 0.68μF
2 3
5 7 100
2 3
5 7 1k
2 3
5 7 10k
2 3
Frequency, f – Hz
5 7100k
THD+N -- f
VD = 15V
RL = 4Ω
PO = 1W
2ch-Drive
AES17
0.1
7
5
3
2
0.01
7
5
3
2
5 7 10k
Frequency, f – Hz
THD+N -- f
CH1
CH2
L = 15μH
C = 0.22μF
CL = 1μF
2 3
5 7 100
2 3
5 7 1k
2 3
5 7 10k
2 3
5 7100k
5 7 10k
2 3
5 7100k
Frequency, f – Hz
Phase -- f
20
VD = 15V
RL = 8Ω
PO = 1W
2 3
VD = 15V
RL = 6Ω
PO = 1W
2ch-Drive
AES17
10
Response -- f
2 3
0.1
7
5
3
2
0.001
2 3 5 7 10
Output power, PO – W
10
10
7
5
3
2
10
THD+N -- PO
0.1
7
5
CH1
CH2
0.01
7
5
3
2
2 3 5 7100
VD = 15V
RL = 4Ω
2ch-Drive
AES17
1
7
5
0.1
7
5
3
2
0.001
2 3 5 7 10
Output power, PO – W
10
7
5
THD+N -- f
VD = 15V
RL = 8Ω
PO = 1W
2ch-Drive
AES17
10
THD+N -- PO
fin
1
7
5
3
2
2 3 5 7100
VD = 15V
RL = 6Ω
2ch-Drive
AES17
1
7
5
10
7
5
3
2
0.001
2 3 5 7 10
Total harmonic distortion, THD+N – %
10
7
5
Total harmonic distortion, THD+N – %
Total harmonic distortion, THD+N – %
LV49152V
0
Phase – deg
Response – dB
0
– 10
– 20
– 40
– 20
– 60
– 30
10
– 80
2 3 5 7100 2 3 5 7 1k
2 3 5 710k 2 3 5 7100k 2 3 5 71000k
Frequency, f – Hz
VD = 15V
RL = 8Ω
PO = 1W
10
2 3
5 7 100
2 3
5 7 1k
2 3
Frequency, f – Hz
No.A1408-23/24
LV49152V
– 60
CHsep. -- f
5
CH1→CH2
CH2→CH1
2
CH2
0.1
CH1
7
5
3
0.01
10
2 3
5 7 100
2 3
5 7 1k
2 3
5 7 10k
2 3
Frequency, f – Hz
5 7100k
1
SVRR -- fr
Rg – Ω
Efficiency -- PO
RL = 8Ω
RL = 4Ω
80
– 40
60
40
CH1
– 60
VD = 15V
fin = 1kHz
2ch-Drive
AES17
20
CH2
– 80
10
2 3 5 7 10 2 3 5 7100 2 3 5 7 1k 2 3 5 710k 2 3 5 7100k
100
VD = 15V
RL = 8Ω
Rg = 0
Vr = 0dBm
DIN AUDIO
Efficiency – %
Ripple rejection ratio, SVRR – dB
3
2
– 80
– 20
VD = 15V
RL = 8Ω
A-weight
7
– 70
0
VNO -- Rg
1
VD = 15V
RL = 8Ω
Rg = 0
VO = 0dBm
DIN AUDIO
Noise, VNO – mVrms
Channel separation, CHsep. – dB
– 50
0.001
2 3
5 7 100
2 3
5 7 1k
2 3
5 7 10k
Ripple Frequency, fr – Hz
2 3
5 7100k
0
2
4
6
8
10
12
14
16
18
20
Output power, PO – W
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PS No.A1408-24/24