School of Electrical Engineering, Seoul National University
SMDL Annual Report 2003
Simulation Study of a New Body-Tied FinFETs (Omega MOSFETs) Using Bulk Si Wafers
Jong–Ho Lee (jongho@ee.knu.ac.kr)
School of Electrical and Electronic Engineering, Kyungpook National University, Daegu, 702-701 Korea
1. Introduction
Double-gate (DG) MOSFET is a promising candidate for
ultimate CMOS device structure because the device has robustness
against short channel effect (SCE), higher current drivability,
nearly ideal subthreshold swing (SS), and mobility enhancement
[1],[2]. However, since these reported devices were achieved by
using SOI wafers, wafer cost is higher than that of bulk wafer and
temperature accumulation may degrade device performance. Also,
these devices may have floating body problem if they are applied to
high voltage integrated circuits (ICs).
In this paper, we propose a new body-tied FinFET and show
it’s device characteristics through 3-dimensional (3-D) device
simulator. Because the body shape resembles Greek letter Omega
(Ω), we call the device Ω MOSFET.
2. Device Structure
The device structure for the Ω MOSFET is shown in Fig. 1
schematically. The gate electrode wraps around the channel region
of the fin, and S/D regions are formed on two ends of the fin. Key
process steps are explained briefly as follows. The starting
substrate is a silicon bulk wafer. Shallow trench isolation (STI) is
performed and followed by ion implantation and drive-in (or
annealing) to form n/p-wells. Then, a part of the flattened oxide
isolation region is etched away vertically, leaving a vertical fin
standing in which the channel and the S/D are formed. The gate
oxide is grown on the exposed Si surface of the fin. After careful
gate patterning, the S/D doping is performed by rotating the tilted
wafer during ion implantation, followed by annealing. Following
process steps are quite conventional.
In Fig. 1, WFin and HFin represent the width and the height of
the fin, respectively. The S/D doping consists of lightly doped drain
(LDD) and heavily doped drain (HDD) in this simulation work.
The junction depth (xj) in Fig. 1 represents the xj of the LDD and is
defined as the depth from the top surface of the fin. TFOX represents
field oxide thickness.
edge and S/D contact is approximately 60 nm and the HDD
concentration is 2×1020 cm-3. The corner regions of the fin were
rounded to remove any possible leakage path. The Ω MOSFETs to
be simulated have the channel on both vertical surfaces of the fin.
For comparison, the SOI FinFETs were designed to have
exactly the same structure and parameters as those of the Ω
MOSFETs. The only difference is the existence of the buried oxide.
Fig. 2 shows the threshold voltage (VT) and drain induced barrier
lowering (DIBL) of NMOSFETs versus the WFin. The subthreshold
swing (SS) characteristics are shown in Fig. 3. The Ω MOSFETs
(solid circles) have nearly the same VT and DIBL characteristics as
those of SOI FinFETs (open circles), which guarantees good
scalability of the Ω MOSFETs. The trend of VT and DIBL
characteristics with the WFin can be explained in [4].
Fig. 4 shows the VT and the SS versus body bias as a function
of WFin (10, 15, 20, 30, 50 nm). For the negative body bias, the VT’s
of Ω MOSFETs with various WFin keep nearly constant, which
alleviates delay problem due to VT increase in bulk MOS devices
connected in series. The SS characteristics for various WFin’s are
nearly constant for negative body bias but increase with positive
body bias. As the WFin decreases, the increase of the SS is less
significant.
Fig. 5 shows effects of the xj on the drain current (ID) and
DIBL characteristics. The xj values are 50, 66, 76, 86, 106 nm at a
fixed HFin of 70 nm. The ID increases linearly with the xj up to about
80 nm which is 10 nm larger than HFin, and then saturated, since the
inversion region is only formed on the vertical surface from 0 to 70
nm and around the 70 nm. We think the optimum xj for a given HFin
is approximately HFin + 10 nm. The DIBL characteristics are nearly
constant with the xj from 55 nm to 106 nm, which means xj
variation has no effect on the device scalability at a fixed WFin of 20
nm. Therefore, we have larger process margin in forming xj for the
Ω MOSFETs.
Fig. 6 shows device temperature versus gate bias at a given
VDS of 0.9 V. The Ω NMOSFET with WFin of 20 nm shows much
lower device temperature than the 30 nm SOI FinFET.
3. 3-D Device Simulation and Results
Electrical characteristics of the Ω NMOSFETs and the SOI ntype FinFETs were studied through the extensive 3-D device
simulation using ATLAS [3]. We adopted the drift-diffusion
transport model in this study, partly because the ATLAS does not
support advanced transport models in 3-D device simulation and
because the drift-diffusion model mostly accounts for the salient
features of the scaling properties. Physical gate length (LG) and
gate oxide thickness (TOX) are 25 nm and 1.5 nm, respectively. The
p-type body concentration is 1×1019 cm-3. The HFin and the TFOX are
fixed at 70 nm and 100 nm, respectively. The WFin and the xj are
variables. The length of LDD region is about 17.5 nm and
concentration is 6×1019 cm-3. The distance between n+ poly-Si gate
4. Conclusions
We have proposed a new body-tied FinFET (Omega
MOSFET) built on the bulk silicon wafer, which may retain the
advantages in wafer cost, defect density, heat transfer, and process
familiarity while keeping nearly same scaling-down characteristics
as the SOI FinFET. By using 3-D device simulator, we have shown
that the Ω MOSFETs have nearly same scaling properties as the
SOI FinFETs. It was also shown that negative body bias in the Ω
MOSFETs has no effect on the threshold voltage. We consider the
Ω MOSFET is very promising candidate for future nano-scale
CMOS technology.
SMDL Annual Report 2003
School of Electrical Engineering, Seoul National University
Acknowledgement
120
0.5
W Fin:
10,
15,
20,
30,
50 nm
0.4
110
0.3
VT (V)
References
[1] Y.-K. Choi, et al., IEDM 2001, pp. 421–424.
[2] J. Kedzierski, et al., IEDM 2001, pp. 437–440.
[3] SILVACO International, ATLAS User’s Manual, version
5.2.0.R, 2000
[4] H.-S. P. Wong, et al., IEDM 1998, pp. 407-410.
100
LG=25 nm
0.2
90
0.1
80
0.0
W Fin:
10,
15,
20,
30,
-1.00 -0.75 -0.50 -0.25 0.00
50 nm
0.25
0.50
70
Subthreshold Swing (mV/dec)
This work was supported by Tera Level Nanodevices Project of
MOST in 2002.
Body Bias (V)
Fig. 4. VT and subthreshold swing (SS) of Ω NMOSFETs versus body bias
as a parameter of fin width. Solid and open symbols represent VT and SS,
respectively.
110
150
0.5
VT (V)
Bulk
SOI
0.3
19
Na=1x10 cm
HFin=70 nm
xj,S/D=66 nm
10
20
60
-3
30
90
50
0
Fin Width (nm)
Fig. 2. Threshold voltage (VT) and DIBL chararcterstics of Ω NMOSFETs
and SOI fin NMOSFETs versus fin width. The n+ poly-Si gate was applied.
Subthreshold Swing (mV/dec)
100
95
LG=25 nm
TOX=1.5 nm
90
Bulk
SOI
VDS=0.05 V
80
19
Na=1x10 cm
10
20
60
30
-3
70
80
90
100
110
110
Fig. 5. Drain current (ID) and DIBL characteristics of Ω NMOSFETs versus
source/drain junction depth at a fixed WFin of 20 nm. The ID was obtained at
VGS=VDS=0.9 V. Solid squares and solid circles represent ID and DIBL,
respectively.
475
450
LG=30 nm
425
TOX=1.5 nm
400
VDS=0.9 V
SOI
375
350
Bulk
325
300
0.2
0.4
0.6
0.8
1.0
Gate Voltage (V)
85
70
50
0.0
VDS=0.9 V
75
120
TOX=1.5 nm
30
40
W Fin=20 nm
LDD S/D Junction Depth (nm)
DIBL (mV/0.9V)
120
0.1
HFin=70 nm
70
150
T OX=1.5 nm
0.2
130
80
Device Temperature (K)
0.4
140
90
60
180
LG=25 nm
100
DIBL (mV/0.9V)
Fig.1. 3-dimensional schematic view of body-tied FinFET. HFin and WFin
represent fin height and width, respectively. TFOX and xj stand for the field
oxide thickness and the source/drain junction depth, respectively.
ID (VGS=VDS=0.9 V) (µA)
LG=25 nm
HFin=70 nm
xj,S/D=66 nm
40
50
Fin Width (nm)
Fig. 3. Subthreshold swing characteristics versus WFin for the Ω MOSFET
and the SOI FinFET as a function of VDS.
Fig. 6. Temperature characteristics of Ω NMOSFET and SOI n-type fin
MOSFET versus gate bias. The results were obtained through 3-D device
lattice temperature simulation.