Modeling and Control of the Single-Phase Photovoltaic
Grid-Connected Cascaded H-Bridge Multilevel Inverter
S.J. Lee, H.S. Bae, B.H. Cho
School of Electrical Engineering, Seoul National University
Gwanak P.O. Box 34, ENG420-043, Seoul, 151-744, Korea
jun21583@snu.ac.kr
In this paper the control design using the loop gain
approach for achieving an individual MPPT for each PV
array and the power factor control is presented. The
proportional and integral (PI) current controller with duty
ratio feed-forward compensation method for the steady state
error and the phase delay is applied. Also, in order to obtain
the maximum power from each PV array, the DC voltages of
each array are individually controlled through the loop design
approach. The proposed control schemes are validated from
the experiment of the 2-kW five-level single-phase cascaded
multilevel inverter system.
Abstract -- This paper presents the modeling and control of
the single-phase photovoltaic grid-connected five-level cascaded
H-bridge multilevel inverter. For the unity power factor, the
proportional and integral current controller with the duty ratio
feed-forward compensation method is used. And in order to
track the maximum power point and to reduce the partial
shading due to stacked photovoltaic modules, each DC voltage is
stably controlled to their maximum power points by dedicated
voltage controllers of each H-bridge module. The modeling
approach and the control loop design method are provided in
this paper. The proposed control schemes are validated from
experimental results of the 2-kW prototype hardware.
Index Terms—Cascaded H-Bridge, Multilevel, Photovoltaic
II.
I. INTRODUCTION
The multilevel converter has several advantages such as
the reduced device voltage stress, the staircase output
waveform, a low electromagnetic emission [1], [2]. Thus the
use of the multilevel schemes has been increased in the
industrial applications which require the high voltage and
high output quality [3]-[5]. Recently, in the photovoltaic (PV)
application, the studies of multilevel topologies with the high
efficiency, low EMI and low core losses have been
progressed. Among them, because isolated DC sources are
naturally obtained from the PV arrays and the PV system can
be easily modularized compared to other multilevel
topologies, the PV system using the cascaded H-bridge
multilevel converter have been introduced [6], [7].
In grid tied PV systems, the single stage structure requires
many PV modules for high voltage. However, stacked PV
modules result in the partial shading when the PV operates
under non-uniform irradiation. In this case, the maximum
power point tracking (MPPT) algorithm is apt to fall into
local maximum points and the output power is decreased
considerably [8], [9]. However, this problem can be reduced
through the cascaded H-bridge multilevel inverter. Using this
topology, PV modules are divided by the number of H-bridge
modules, and each PV array operating voltage can be
controlled to their maximum power points using an individual
MPPT algorithm. Thus the control loop design should be
taken into account in order to achieve the each PV array
voltage control and unity power factor control. In [10], the
individual DC voltage control and PWM modulation
technique are proposed in order to achieve the
aforementioned objectives.
978-1-4244-2893-9/09/$25.00 ©2009 IEEE
MODELING AND CONTROL METHOD
A. Modeling of five-level cascaded H-bridge multilevel
inverter
The single-phase five-level cascaded H-bridge multilevel
PV system is shown in Fig. 1. In order to design the control
loops a small signal model is developed. The small signal
modeling technique based on the state space averaging is
used. The input currents and output voltages of each H-bridge
module are defined as (1)-(4) through switching states as
shown in Fig. 2.
Fig. 1.
43
Single-phase photovoltaic cascaded H-bridge multilevel inverter
vsw1 = s11vdc1 − s31vdc1
(1)
vsw2 = s12 vdc 2 − s32 vdc 2
(2)
idc1 = s11iL − s31iL
(3)
idc 2 = s12iL − s32iL
(4)
⎡
⎢
0
⎢
⎡ iˆL ⎤
⎢ ( 2 D − 1)
d ⎢
⎥
11
vˆdc1 ⎥ = ⎢ −
⎢
dt ⎢
C
⎢
1
⎥
⎢
⎣ vˆdc 2 ⎦
D
2
(
12 − 1)
⎢−
⎢⎣
C2
The S11, S31, idc1 and Vsw1 are switching states of upper
switches of each leg and the input current and the output
voltage in the upper H-bridge module. Similarly, the S12, S32,
idc2 and Vsw2 are switching states of upper switches of each leg
and the input current and output voltage in the lower Hbridge module.
Assuming that the switching frequency is higher than that
of the modulating signals in the phase-shifted carrier
technique [11], the switching states can be represented as
duty ratios, and averaged state equations are derived as (5)(7).
di
L L = ( 2d11 − 1) vdc1 + ( 2d12 − 1) vdc 2 − vg
dt
(6)
C2
dvdc 2
= iin 2 − idc 2
dt
(7)
2Vdc 2 ⎤
⎥
L ⎥
⎥
0 ⎥
⎥
2I L ⎥
⎥
−
C2 ⎦⎥
L
L
0
0
0
0
⎡
⎢0
⎢
⎡ dˆ11 ⎤
⎢1
⎢ ⎥ + ⎢
ˆ
d
⎢ C1
⎣⎢ 12 ⎥⎦
⎢
⎢0
⎣⎢
⎥
⎥
⎥
⎥
⎥
⎥
⎥⎦
0
0
1
C2
⎡ iˆL ⎤
⎢
⎥
⎢ vˆdc1 ⎥
⎢
⎥
⎣vˆdc 2 ⎦
1⎤
− ⎥
L⎥
⎥
0 ⎥
⎥
⎥
0 ⎥
⎦⎥
⎡ iˆin1 ⎤
⎢ˆ ⎥
⎢iin 2 ⎥
⎢ vˆg ⎥
⎣ ⎦
(8)
B.
Control-loop design method
Because the PI current control in the AC system has the
steady state error and phase delay with respect to the current
reference, the duty ratio feed-forward scheme is employed to
improve the grid current control performance. The duty ratio
relationship for feed-forward can be derived as (9) from the
steady state condition of the averaged model.
(5)
dvdc1
= iin1 − idc1
dt
C1
⎡ 2V
⎢ dc1
⎢ L
⎢ 2I
+ ⎢− L
⎢ C1
⎢
⎢ 0
⎣⎢
( 2 D11 − 1) ( 2 D12 − 1) ⎤⎥
1 ⎛ Iin,i ⎞
D1i = ⎜1 +
⎟ , i = 1, 2
IL ⎠
2⎝
Through the perturbation and linearization process, small
signal state equations are represented as (8), from which
transfer functions, such as duty ratio to inductor current and
duty ratio to each DC voltage, can be obtained.
(9)
Because the generated power of PV array is generally
measured for the MPPT algorithm implementation, the
second term of (9) can be modified to the relationship which
is related to the PV array powers. Thus duty ratios of each Hbridge module are derived as (10).
Vc*
Pin,i ⋅ vg
1⎛
D1i = ⎜1 +
⎜
2 ⎝ Pin,tot ⋅ vdc,i
1 − Vc*
⎞
⎟ , i = 1, 2
⎟
⎠
(10)
where Pin1 and Pin2 are each input power of H-bridge module,
and Pin,tot is the sum of two PV array powers.
In order to design the control loops for the grid current and
each DC link (PV array) voltage, Fig. 3 shows the small
signal control block diagram. The power stage transfer
functions, such as GiLd1, GiLd2, Gvd1d1, Gvd1d2, Gvd2d1, Gvd2d2,
Gvg1, Gvg2 and Gig, are derived using numerical calculations
from (8). Each current loop is designed to have a high cutoff
frequency and a sufficient phase margin for the grid power
factor control.
The current loop closed system without voltage controllers
can be considered as the two-input two-output (TITO) of Fig.
4. The g11 is transfer function of Vc1 to Vdc1 and g12 is Vc2 to
Vdc1. The derived transfer functions are represented as (11)(12).
Fig. 2. Relationship of switching states and duty ratios.
44
Thus outer loops are designed to stabilize the whole
system through the following loop design approach. Without
the voltage loop T2, the voltage loop T1 is firstly designed. In
this condition, the transfer function of control voltage Vc2 to
DC voltage Vdc2 with closed T1 loop can be derived as (15).
vˆdc 2
vˆc 2
T1
cl
=
(
H i Gvdc 2d 2 (1 + Ti1 + Tv1 ) − H i Gvdc 2d1 Ti 2 + H i H v Gvdc1d 2
)
1 + Ti1 + Ti 2 + Tv1 + Tx + Ti 2Tv1
(15)
Where
Ti1 = H i GiL d1
Ti 2 = H i GiL d2
Tv1 = H i H v Gvdc1d1
Tx = − H i 2 H v Gvdc1d 2 GiL d1
Fig. 3.
.
The voltage loop gain T2 defined as (16) is designed to
achieve the desired cutoff bandwidth and the phase margin.
Small signal control block diagram
T2 = H v ⋅
vˆdc 2
vˆc 2
(16)
T1 , closed
Thus, using the sequential design approach, the control
objectives and stability can be achieved.
III. EXPERIMENTAL RESULTS
For the experimental set-up, two isolated power supplies
with series resistances for PV arrays are used as shown in Fig.
5 [12]. The output characteristics of each PV array can be
controlled such that unbalanced PV output case is shown in
Fig. 6 to verify the performance of the controller. The system
parameters are tabulated in Table I.
Fig. 4. Current-loop closed control block diagram for outer loop design
vˆdc1 H i Gvdc1d1 (1 + Ti 2 ) − Ti1H i Gvdc1d 2
=
1 + Ti1 + Ti 2
vˆc1
vˆdc1 H i Gvdc1d 2 (1 + Ti1 ) − Ti 2 H i Gvdc1d1
=
1 + Ti1 + Ti 2
vˆc 2
(11)
i in1
i dc1
R
s11
s31
iL
L
C1
Vin1
(12)
Where Hi is the PI current controller and Ti1 and Ti2 are the
current loop gains which are denoted as HiGiLd1 and HiGiLd2,
respectively.
i in2
i dc2
R
Vin2
Similarly, the g21 is Vc1 to Vdc2 and the g22 is Vc2 to Vdc2. The
transfer functions are derived as (13)-(14).
Vdc1
s12
C2
Vg
s32
Vdc2
s11 s31 s12 s32
vˆdc 2 H i Gvdc 2 d1 (1 + Ti 2 ) − Ti1 H i Gvdc 2 d2
=
1 + Ti1 + Ti 2
vˆc1
(13)
vˆdc 2 H i Gvdc 2 d2 (1 + Ti1 ) − Ti 2 H i Gvdc 2 d1
=
1 + Ti1 + Ti 2
vˆc 2
(14)
LPF
LPF
LPF
LPF
DSP
Fig. 5.
45
Advanced
InCond
Algorithm
Voltage
Controller
PWM
Current
Controller
+
sinθ
PLL
Prototype experiment hardware set and control scheme
TABLE I
SYSTEM PARAMETERS OF PROTOTYPE PV SYSTEM
DC power supply
Vin1 = Vin2 = 0 ~ 250V
Output filter inductor
L = 1mH
DC-link capacitor
C1 = 2200uF, C2 = 2200uF
Resistor
R = 14Ω
40
Magnitude (dB)
Grid voltage
Switching Frequency
DSP
Voltage Loop Gain Bode Diagram
60
Vg = 110Vrms
fsw = 5kHz
TMS320F2812
20
0
-20
-40
-60
-90
Phase (deg)
Each H-bridge module input power versus Each DC voltage
1200
1000
(a)
-180
-225
-270
-1
10
800
Power (W)
-135
10
0
1
10
10
Frequency (Hz)
2
3
10
4
10
Fig. 7. Voltage loop gain bode diagram.
600
(b)
400
200
0
0
50
100
150
200
250
Vdc (V)
Fig. 6. Each input power versus each DC voltage characteristics.
Two DC power supplies have an operating voltage range,
0-250V and two selected resistances are around 14Ω. In two
cases, the voltage loop gain T2 is shown in Fig. 7. The cutoff
frequency of voltage loop gain is 30-40Hz, and the phase
margin is around 45 degrees in both input conditions.
Fig. 8 and Fig. 9 show the experimental results of each DC
voltage and grid current control performance. Even though
two input conditions are different, maximum powers from
each input source are extracted through controlling the
individual operating voltage. In Fig. 8, because two input DC
supplies are 240V, both maximum power points are 120V. In
Fig. 9, because two input DC supplies are 240V and 200V,
maximum power points are 120V and 100V, respectively.
Also, the output voltage of two H-bridge modules shows a
stair-case waveform, 5-level. Fig. 10 shows an enlarged
waveform of Fig. 8. The grid current is controlled in phase
with the utility voltage and the summed power is stably
transferred to the utility grid.
Fig. 11 shows the maximum power point tracking
performance. After starting the operation, both DC voltages
are tracked to their maximum power points. In this work, the
DC voltage references are independently given from an
advanced incremental conductance MPPT algorithm [13].
The update period of MPPT algorithm is set to 2 seconds and
the maximum step size for changing the voltage references is
5V.
Fig. 8. Experimental results (Vdc1,MPP = 120V, Vdc2,MPP = 120V).
Fig. 9.
46
Experimental results (Vdc1,MPP = 120V, Vdc2,MPP = 100V).
[3]
Vdc1 (50V/div)
[4]
Vdc2 (50V/div)
[5]
[6]
[7]
5ms/div
IL (10A/div)
[8]
Vg (100V/div)
[9]
Fig. 10. Experimental results (Vdc1,MPP = 120V, Vdc2,MPP = 120V).
[10]
[11]
[12]
[13]
Fig. 11. Experimental results for maximum power point tracking.
IV. CONCLUSION
In this paper, the modeling and control for the individual
MPPT and the power factor control of the single-phase
cascaded H-bridge multilevel PV inverter is proposed. For
the unity power factor, the PI current controller with the duty
ratio feed-forward compensation method is employed. In
order to achieve the individual MPPT, the each DC link
voltage loop is designed to stabilize the current loop closed
system. The proposed control methods are validated from
experimental results from the 2-kW prototype hardware.
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