IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 2, MARCH 2008
635
A Unity Power Factor Correction Preregulator
With Fast Dynamic Response Based
on a Low-Cost Microcontroller
Diego G. Lamar, Student Member, IEEE, Arturo Fernández, Member, IEEE, Manuel Arias, Student Member, IEEE,
Miguel Rodríguez, Student Member, IEEE, Javier Sebastián, Member, IEEE, and
Marta Maria Hernando, Member, IEEE
Abstract—Low cost passive power factor correction (PFC)
and single-stage PFC converters cannot draw a sinusoidal input
current and are only suitable solutions to supply low power levels.
PFC preregulators based on the use of a multiplier solve such
drawbacks, but a second stage dc–dc converter is needed to obtain
fast output voltage dynamics. The output voltage response of PFC
preregulators can be improved by increasing the corner frequency
of the output voltage feedback loop. The main drawback to
obtaining a faster converter output response is the distortion of
the input current. This paper describes a simple control strategy
to obtain a sinusoidal input current. Based on the static analysis of output voltage ripple, a modified sinusoidal reference is
created using a low cost microcontroller in order to obtain an
input sinusoidal current. This reference replaces the traditional
rectified sinusoidal input voltage reference in PFC preregulators
with multiplier control. Using this circuitry, PFC preregulator
topologies with galvanic isolation are suitable solutions to design
a power supply with fast output voltage response (10 or 8.33 ms)
and low line current distortion. Finally, theoretical and simulated
results are validated using a 500 W prototype.
Index Terms—EN 61000-3-2 regulations, fast output voltage
dynamics, modified sinusoidal reference, power factor correction
(PFC).
I. INTRODUCTION
P
OWER factor correction (PFC) used to be synonymous
with sinusoidal input current and extremely low total harmonic distortion (THD). When IEC 61000-3-2 regulations came
into force in 2001, the PFC solutions with low power converters
became even more evident. A sinusoidal waveform is not needed
to comply with this regulation. The only requirement is for the
harmonic content of the input power to be measured at nominal
input voltage and for the input current to be below a limit set by
the regulation. In short, the philosophy of the PFC has changed.
Simple passive PFC solutions based on reactive devices are
robust and economical solutions. Some simple passive circuits
have already been presented in other papers: single-phase rectiManuscript received April 1, 2007; revised July 10, 2007. This paper was presented at the IEEE Applied Power Electronics Conference (APEC), Anaheim,
CA, February 27, 2007. This work was supported by the Spanish government,
under Project MEC04-TEC2004-02468. Recommended for publication by Associate Editor S. Pekarek.
The authors are with Grupo de Sistemas Electrónicos de Alimentación, Universidad de Oviedo, Gijón 33204, Spain (e-mail: gonzalezdiego@uniovi.es).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TPEL.2007.915657
fiers with an
filter [1]–[3], inductance or resistance between
the input rectifiers and the bulk capacitor [4], etc., all of which
are good solutions for low power levels. However, the input current harmonic content is very close to the limit and some solutions have many drawbacks with the universal input line voltage
range.
PFC preregulator circuits are widely considered the best solution for high power levels and the universal input line voltage
range [5]. The injection of current harmonics to the line is very
low due to the quasi-sinusoidal input current waveform. Moreover, an input current with a very low distortion guarantees compliance with international regulations even if regulatory limits
change in the future. The main disadvantage of these circuits
is their poor output voltage dynamics. This is due to the fact
that the output voltage regulator has a low pass-filter (10–20 Hz
bandwidth) needed to reduce the THD of the input line current. If the specification requires fast output voltage regulation,
a second stage is needed to improve output converter dynamics.
In fact, the dc–dc converter placed in cascade defines the twostage converter output voltage response. However, for low and
medium power levels, unity PFC topology dc–dc converter can
be an expensive and complex solution.
When a unity power factor is not needed, single-stage PFC
converters are a possible solution [6]–[11]. These topologies exhibit fast output voltage dynamics (more or less of the same
order as two-stage PFC converters) at relatively low cost and
small size. Their efficiency with narrow voltage ranges is very
high because most of the power is only processed once, or at
least only a small part is processed twice. However, these advantages are only valid for low power levels.
Nevertheless, there are many applications in which the load
remains more or less constant and no extremely fast output
voltage response is needed. In some of these applications,
PFC preregulator converters can be used without the cascade
connected dc–dc converters. The poor dynamic response of
standard PFC preregulators can be improved by increasing
the traditional output voltage regulator bandwidth from 10 Hz
to 1 kHz thereby allowing a moderate distortion of the input
current [12]. In this case, the design philosophy of the PFC
preregulator changes: the main objective is to improve the
output response instead of drawing a sinusoidal input current.
So PFC preregulators with fast dynamic response can be used
to design an ac–dc complete power supply in the hundred watts
range. In this case, PFC preregulators must have galvanic isolation (that is, is based on a dc–dc converter with a transformer,
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 2, MARCH 2008
Fig. 1. PFC preregulator.
i.e., Flyback PFC). Moreover, the output voltage must be sufficiently high and the output voltage ripple specification must be
not very restrictive. This is because the size of the bulk capacitor
of the PFC preregulator increases when the output voltage decreases or when the output voltage ripple decreases, for a given
power. Also the dynamic requirements of the power supply can
be achieved by a PFC preregulator. Finally, these kinds of converters are not available solutions when the converter must satisfy hold-up time specifications. The conclusion is that a complete power supply can be designed using the PFC preregulator
solution for both high power ( 600 W) and medium power
levels ( 600 W). It is also a cheaper circuit than the traditional
two-stage solution. However, this solution has the above mentioned limitations. The use of only a PFC preregulator as a complete power supply is an interesting option for some specific applications (i.e.,: analog loads, battery chargers, audio switching
amplifiers, etc ).
This paper presents a simple control strategy to achieve fast
dynamic response and sinusoidal input current. This control is
based on the use of a low-cost microcontroller ( C) as voltage
waveform reference. First the paper presents an analysis of
the PFC preregulator with fast dynamic response describing
the trade-off between input current distortion and dynamic response of the output voltage. It then describes a simple control
strategy based on a modified sinusoidal reference. Finally a
simple strategy with a low-cost microcontroller is proposed
using this modified sinusoidal reference to obtain a sinusoidal
input current compatible with a ‘relatively’ fast response (10 ms
if the line frequency is 50 Hz or 8.33 ms if the line frequency
is 60 Hz).
II. STATIC ANALYSIS OF POWER FACTOR CORRECTOR
PREREGULATORS WITH FAST DYNAMICS
PFC preregulators have an inner feedback loop, the current
loop, and an outer one, the voltage loop (Fig. 1). The current
loop makes the line current follow a reference signal. In general, the input current in PFC preregulators follows a sinusoidal
reference. The voltage loop regulates output voltage. This paper
will next review typical static analysis of the PFC preregulators
[13], [14].
Fig. 2. PFC preregulator waveforms: (a) traditional, with a 10 Hz corner frequency of the low-pass filter of the output voltage feedback loop and (b) with
fast dynamics, with a 1 kHz corner frequency of the low-pass filter of the output
voltage feedback loop.
Traditionally, a low-pass filter is included in the output
voltage feedback loop to eliminate 100–120 Hz output voltage
ripple. The output voltage of the voltage feedback loop is
. The input line current reference is
therefore a dc value
therefore a sinusoidal waveform and the input line current (t)
(assuming the current loop to be ideal) has no distortion
(1)
is the voltage peak of the input voltage
( ),
where
is the line angular frequency and K is a constant value.
PFC preregulators have a high efficiency (around 95%). So
output power before the output bulk capacitor (t) is equal to
()
input power
(2)
Moreover, the output bulk capacitor C is big enough to keep the
constant, so the output current expression is
output voltage
(3)
As can be seen in Fig. 2(a) and in (3), the output current has a
dc value and a second harmonic. This second harmonic is processed through the bulk capacitor. A voltage ripple thus appears
at the output voltage and is transmitted into the output voltage
feedback loop. For this reason, a low-pass filter is needed in
order to attenuate and quasi-eliminate this distortion and keep
the input line current sinusoidal, as can be seen in (1). However, the low pass-filter decreases the feedback bandwidth of the
output voltage, causing a poor dynamic response of the output
voltage in PFC preregulators.
This paper will next consider the situation in which the corner
placed in the output voltage
frequency of the low-pass filter
feedback loop is increased in order to improve the response of
output voltage in PFC preregulators. The PFC preregulators priorities change: the main objective is to improve the output response instead of drawing a sinusoidal input current to obtain
PFC preregulators with fast dynamics. The output voltage ripple
LAMAR et al.: UNITY POWER FACTOR CORRECTION PREREGULATOR
637
Fig. 3. Static analysis of the second harmonic of the output current to obtain the ripple characteristics of v (t): V
of double line frequency value 2
2
2 is transferred into the output voltage feedback loop. Thus, the voltage
is not a constant
of the output voltage feedback loop
value
(4)
where
is the second harmonic amplitude of
( ) and
is the phase lag with respect to
of the second harmonic
( ) [see Fig. 2(b)].
of
The input line current can be easily calculated by substituting
for
( ) in (1)
he value of
and .
In this study, the influence of the fourth harmonic of the output
( ), is not included in the calculations to simplify the
current,
static study because is strongly attenuated by the output filter.
In consequence, only the second harmonic of ( ) is processed
through the PFC preregulator power stage and the output voltage
feedback loop in order to calculate the ripple characteristics of
( ). Its value can be obtained from (6b)
(5)
(8)
The input line current, therefore, is not sinusoidal. The second
( ) is transformed into the third harmonic of the
harmonic of
input line current. Furthermore, input line current distortion is
defined by the ripple characteristics of the output voltage of the
and ). The ripple of
( ) can
voltage feedback loop (
be calculated from (t), from the power stage characteristics
of the PFC preregulator and from the transfer function of the
output voltage feedback loop.
Substituting (5) in (2) and supposing an output bulk capacitor
constant, the input
big enough to keep the output voltage
current is
The second harmonic of the output current passes through the
output filter (composed of the bulk capacitor and the load ),
the output voltage divider and the output voltage regulator in
order to obtain the voltage ripple of the voltage feedback loop
(6)
(6a)
(9)
It should be noted that the output voltage remains constant due
to the large value of the bulk capacitor and influence of in the
output filter disappears, as it shown in Fig. 3. The value of the
output capacitor needed for a specific output voltage ripple of
the PFC preregulator is
(10)
(6b)
(6c)
Moreover, can be easily calculated as a function of averaged
power processed by the PFC preregulator ( ) from (6a)
(7)
is the amplitude ripple of the output voltage exwhere
pressed as a percentage of the output voltage.
The output voltage divider scales the output voltage ripple
. Finally, the output voltage regulator processes the
of 2
( ). As a result,
output voltage ripple in order to obtain
and its
the voltage regulator characteristics, (i.e., dc gain
2 ) also define the
( ) ripple
corner frequency
characteristic. Therefore, if the transfer function between ( )
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 2, MARCH 2008
and
( ) is studied, then the expressions of
and can
be easily calculated following the above mentioned process:
(11)
Fig. 4. Averaged model described in [12] with its output voltage feedback loop.
(12)
where
is the voltage regulator gain at 2
corner angular.
and
is its
III. NEW CONTROL STRATEGY BASED ON A MODIFIED
SINUSOIDAL FIXED REFERENCE IN THE MULTIPLIER
CONTROL OF PFC PREREGULATORS
WITH FAST DYNAMICS
This section will study the expressions calculated above to
obtain quantitative and qualitative conclusions about ( ) dis( ) dependence analysis will be described
tortion. First, a
which will lead to further conclusions.
As can be seen in the input current expression (5), ( ) dis, the
tortion is defined by the amplitude of the ripple
and the dc value
of the output voltage
ripple phase lag
and
terms are merged
of the voltage feedback loop.
to simplify
into a single term called relative ripple
distortion analysis. This relative ripple of the output voltage of
( ) amplitude ripple
the voltage feedback loop is defined as
divided by its dc value. Furthermore, if the expression of (7)
is substituted in the input current expression (5), the result highlights the proportionality between the averaged input power P
and the input current ( ) and also the inverse proportionality
and ( ), as (13) shows
between the input voltage peak
(13)
This equation shows that the shape of the input current only
and the ripple phase
depends on the relative ripple
and ) are
lag . The values of these quantities (
shown in (11) and (12). As these expressions show, the output
power does not determine the values of above mentioned quanand
tities. The non-dependence of relative ripple
on the averaged input power is of greater significance, because
and determines the shape of the input current,
as has been previously explained. Therefore, the shape of the
input current does not depend on the power processed by the
PFC preregulator with fast dynamics. In other words, the relationship between the amplitude of the first and third harmonic
and the relative position of these harmonics are independent of
the power processed for a PFC preregulator design.
The previous conclusions can be applied when a load step occurs. The shape of the input current will be the same at the beginning and at the end of the load step, because the only difference
between them will be the different power processed by the PFC
preregulator. The large-signal averaged model described in [12]
(Fig. 4) is proposed to simulate a load step and to check what the
shape of the input current is like. It is a simple averaged model
which can be easily implemented with simulation software (e.g.,
Pspice) to obtain the real distortion of the input line current.
Fig. 5 illustrates the results of the simulation of two load steps
of the PFC preregulator with different designs of the output
voltage feedback loop. As can be seen, the shape of (t) remains constant at the initial and the final stage of the load step
level changes, as has already been shown, and the harbut
monic content of both stages are proportional.
One simplification was made in the PFC preregulator static
study: the second harmonic is the only output voltage ripple
component which introduces distortion in ( ). In fact, higher
order harmonics cause distortion in the input line current in a
real PFC preregulator with fast dynamics. However, theoretical
and simulation results are very close, demonstrating that the
paper’s earlier hypothesis that was used to simplify the static
study was correct.
As has already been pointed out, if the shape of ( ) does
not change in the initial and final stages of a load step, then a
new control strategy can be implemented in the PFC preregulator with multiplier control. This new solution draws a sinusoidal input current and it keeps the dynamic response of the
output voltage fast. A new properly modified sinusoidal reference as a fixed pattern is introduced in the multiplier in spite
of the traditional sinusoidal reference sensed from the rectifier
input voltage.
This modified sinusoidal reference must first be calculated
in order to obtain a sinusoidal input current (Fig. 6). The static
( ) waveform is like, so
study has already shown what the
it is easy to calculate this properly modified reference as a si( ) divided by
( ). A simple and low cost cirnusoidal
cuitry must thus be implemented and inserted into the multiplier control to generate the fixed pattern at 2
frequency. In
LAMAR et al.: UNITY POWER FACTOR CORRECTION PREREGULATOR
639
Fig. 7. Waveforms of the load step from 1/3P
ulator with fast dynamics for proposed solution.
to P
of the PFC prereg-
Fig. 5. Waveforms and harmonic content of i (t) of the load step from 1/3
P to P and the harmonic content of the PFC preregulator with two different output voltage feedback loop designs: (a) A
40 y f
10 Hz; (b)
A
40 y f
1 kHz.
=
=
=
=
Fig. 8. PFC preregulator with fast dynamics with the non sinusoidal reference
strategy generated by a low cost C.
IV. LOW COST MICROCONTROLLER GENERATING
THE MODIFIED SINUSOIDAL REFERENCE
Fig. 6. New control strategy based on a non sinusoidal reference in PFC preregulators with fast dynamics in order to obtain a sinusoidal input current.
this case, a sinusoidal input current is drawn without a low-pass
filter using this control strategy. Finally, if a load step occurs,
( ) remains sinusoidal because the shape of the input
then
current does not change so the fixed pattern previously calculated should be the same.
In Fig. 7, a load step has been simulated using this new control strategy. As can be seen, the input line current is sinusoidal
after and before the load step. Furthermore, dynamic response,
at around 10 ms, is fast.
As previously stated, simple circuitry is needed to generate
the properly modified sinusoidal reference, which can easily be
calculated using the earlier static analysis. Mathematical software (e.g., Mathcad) can be used for waveform calculation, enabling the reference waveform to be easily normalized to its
peak value. Finally, a fixed and normalized reference pattern can
be used as a properly modified sinusoidal reference.
This pattern can be generated by a pulse width modulation
(PWM) module of a low-cost microcontroller ( C), as can be
seen in Fig. 8. The microcontroller reference voltage is smaller
than the traditional reference sensed from the rectifier input
voltage. However, traditional multiplier control chips (e.g.,
reference as a current reference.
UC3854B) sense the
Therefore, if the value of the current limit resistance [15] used
in the traditional control is substituted by the adequate value
then the chip levels are maintained. A low-cost microcontroller
(PIC 16F627) working at 20 MHz was used to implement the
new control strategy. This is a simple circuit, costing around
1 .
repetitive pattern of the modified sinuThe fixed and 2
soidal reference also has to be synchronized. This reference and
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 2, MARCH 2008
Fig. 9. Experimental harmonic content of the PFC preregulator with fast dynamics with traditional sinusoidal reference and with a C modified sinusoidal
reference.
Fig. 11. Prototype dynamic response: (a) with traditional sinusoidal reference
and traditional voltage loop bandwidth design; (b) with traditional sinusoidal
reference and increased voltage loop bandwidth design; and (c) with a C modified sinusoidal reference and increased voltage loop bandwidth design.
=
p
Fig. 10. Prototype input current at V
230 2 and P = 500 W: (a) with
traditional sinusoidal reference and (b) with a C modified sinusoidal reference.
the rectifier input voltage have to be “in phase” so a synchronization circuit has to be implemented (Fig. 8). This kind of
circuits usually detects significant points of the input voltage.
( ) were chosen. When these points
Zero voltage points of
are detected, the microcontroller launches the fixed waveform
of the modified sinusoidal reference. As a result, the reference
signal is synchronized every 10 ms (or 8.33 ms if the line frequency is 60 Hz).
The microcontroller algorithm is based on a look-up table
with normalized values of the duty cycle. The program goes
through the table from top to bottom when the synchronized
point is detected. Apart from generating the reference, the
microcontroller can also perform other functions: protection
system, supervision system, soft start of the converter, etc.
V. EXPERIMENTAL RESULTS
A 500 W PFC preregulator prototype, based on a boost
topology, was developed in order to test the averaged and
theoretical models. The main specifications of the PFC boost
converter are the following: input voltage: 85–265 V, output
voltage: 400 V; output voltage ripple: less than 1% and 100 kHz
switching frequency.
Fig. 9 shows the experimental harmonic content when the
40 and
output voltage feedback loop is designed as
1 kHz, with traditional sinusoidal reference and with a C
modified sinusoidal reference. A sinusoidal input current can be
obtained by using this new control strategy. In contrast, with the
traditional control strategy the input current distortion is defined
by the third harmonic, so the higher harmonic content can be
ignored as it was said previously.
Fig. 10 shows the input current when the design of the feed40 and
1 kHz with traditional sinuback loop is:
soidal reference [Fig. 10(a)] and with a C modified sinusoidal
Fig. 12. Prototype waveforms of the load step with a C modified sinusoidal
reference.
reference [Fig. 10(b)]. The input current is sinusoidal with the
C modified sinusoidal reference. However, the distortion of
( ) is appreciable with the traditional sinusoidal reference. Standard regulations such as IEC 61000-3-2 cannot be complied at
high power levels.
Fig. 11 shows a prototype load step from 1/3 of full load to full
load. This test was run with the previous output voltage feedback
40 and
1 kHz with
loop design [Fig. 10(b) and (c)]:
traditional sinusoidal reference and with a C modified sinusoidal reference. The dynamic responses of both control strategies are similar: around a 10 ms output voltage response. In this
case, the C control strategy response is faster than the traditional response of the unity PFC of around 100 ms [Fig. 10(a)]
keeping a sinusoidal input current.
Finally, Fig. 12 shows a prototype load step from full load
to 1/3 of full load for the proposed control strategy. The input
current remains sinusoidal after and before the load step, as was
deduced in the previous static analysis. Moreover, the dynamic
response of the output voltage is fast (around 20 ms), so PFC
LAMAR et al.: UNITY POWER FACTOR CORRECTION PREREGULATOR
preregulators with galvanic isolation (e.g., Flyback PFC preregulator) can be implemented as sometimes as ac-dc power supplies without using a second stage dc–dc to obtain a sinusoidal
input current.
VI. CONCLUSION
PFC preregulators are traditionally used as first stage in ac–dc
power supply designs. A second stage is needed to improve
output voltage dynamics, reduce output voltage and provide galvanic isolation. However, a relatively high output response can
be achieved by increasing the corner frequency of the low-pass
filter of the output voltage feedback loop (PFC preregulators
with fast dynamics). In contrast, the output voltage ripple of the
voltage regulator distorts input line current.
This paper shows that the relative ripple at the output of the
voltage feedback loop does not depend on the power. A new
control strategy is presented: if a properly modified sinusoidal
reference (based on the static analysis presented) is employed
as a fixed pattern in spite of the traditional sinusoidal reference,
then a sinusoidal current can be drawn in PFC preregulators with
fast dynamics. The fixed pattern can be generated in a low cost
microcontroller. Moreover, the microcontroller ( C) circuitry
can be easily used with commercial chips of PFC preregulators
with multiplier control.
Therefore, sinusoidal input current ac-dc power supplies
based on PFC preregulators with fast dynamic response and
galvanic isolation (e.g., Flyback PFC preregulator) can be
designed without using a second stage dc–dc. They provide
unity power factor correction solutions with a 10 ms (8.33 ms)
maximum dynamic response of the output voltage. So the use
of only PFC preregulator is another option to design a complete
power supply for some specific cases. However, some restrictions must be considered in this application: hold-up time must
not be required, the output voltage must be sufficiently high
due to the real bulk capacitor characteristics and the dynamic
requirements can be achieved by the PFC preregulator.
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[13] H. Dixon, “Average current mode control of switching power supplies,”
presented at the Unitrode Switching Regulator Power Supply Design
Seminar (SEM 700), 1990.
[14] L. H. Dixon, “High power factor pre-regulators for off-line power supplies,” presented at the Unitrode Switching Regulator Power Supply
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Diego G. Lamar (S’05) was born in Zaragoza, Spain,
in 1974. He received the M.Sc. degree in electrical
engineering from the University of Oviedo, Gijón,
Spain, in 2003.
In 2003, he became a Research Engineer at the
University of Oviedo and since September 2005, he
has been an Assistant Professor. His research interests are switching-mode power supplies, converter
modeling, and power-factor-correction converters.
Arturo Fernández (M’98) received the M.Sc. and
Ph.D. degrees in electrical engineering from the Universidad de Oviedo, Gijón, Spain, in 1997 and 2000,
respectively.
In 1998, he joined the Universidad de Oviedo as
an Assistant Professor and became an Associate Professor in 2003. Since 2007, he has been a Contractor
at the European Space Agency and is currently
working at the Power and Energy Conversion Division. He has been involved in around 20 power
electronics research and development projects since
1997 and he has published over 50 technical papers. Regarding Power Factor
Correction issues, he has been involved in the development of high power factor
rectifiers for Alcatel and Chloride Power Protection. His research interests are
switching-mode power supplies, low output voltage, converter modeling, high
power factor rectifiers, and power electronics for space applications.
Dr. Fernández is a member of the IEEE-PELS Spanish Chapter.
Manuel Arias (S’05) was born in Oviedo, Spain, in
1980. He received the M.Sc. degree in electrical engineering from the University of Oviedo, Gijón, Spain
in 2005 where he is currently pursuing the Ph.D. degree.
Since February 2005, he has been a Researcher
in the Electrical and Electronic Engineering Department, University of Oviedo, developing electronic
systems for UPSs and electronic switching power
supplies. Since February 2007, he has also been
an Assistant Professor of electronics in the same
University. His research interests include dc–dc converters, HF inverters, UPSs,
and motor control.
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 2, MARCH 2008
Miguel Rodríguez (S’06) was born in Gijón, Spain,
in 1982. He received the M.S. degree in telecommunication engineering from the University of Oviedo,
Gijón, in 2006 where he is currently pursuing the
Ph.D. degree.
His research interests include dc–dc conversion,
high frequency power conversion and power supply
systems for RF amplifiers.
Javier Sebastián (M’95) was born in Madrid, Spain,
in 1958. He received the M.Sc. degree from the Polytechnic University of Madrid, in 1981 and the Ph.D.
degree from the University of Oviedo, Gijón, Spain,
in 1985.
He was an Assistant Professor and an Associate
Professor at both the Polytechnic University of
Madrid and at the University of Oviedo. Since 1992,
he has been with the University of Oviedo, where
he is currently a Professor. His research interests
are switching-mode power supplies, modelling of
dc-to-dc converters, low output voltage dc-to-dc converters, and high power
factor rectifiers.
Marta María Hernando (M’94) was born in Gijón,
Spain, in 1964. She received the M.S. and Ph.D. degrees in electrical engineering from the University of
Oviedo, Gijón, Spain, in 1988 and 1992, respectively.
She is currently an Associate Professor at the
University of Oviedo. Her main interests include
switching-mode power supplies and high-power
factor rectifiers.