A. Barkley, D. Michaud, E. Santi, A. Monti
University of South Carolina
EE Dept – 301 S. Main St
Columbia, SC, 29208, USA
Email: santi@engr.sc.edu
D. Patterson
University of Nebraska, Lincoln
EE Dept, 209 N WSEC, PO Box 880511
Lincoln NE 68588-0511, USA
Email: patterson@ieee.org
Abstract— This paper proposes a single stage topology suitable for small to medium power systems with high inertia loads such as home appliances. This approach features a single controlled power stage which implements both conventional brushless DC motor speed control and a novel power factor correction strategy. This approach eliminates the Boost Unity Power
Factor (UPF) stage and bulk electrolytic capacitor typically used for single phase applications. With an appropriate current modulation strategy, the input current can be shaped and high input power factor can be obtained. Design equations are derived, a comparison with the conventional two-stage approach is performed and simulation and experimental results are presented.
Fig. 1: Conventional approach with Boost UPF and large electrolytic energy storage capacitor
I.
INTRODUCTION
Traditionally, single phase input brushless DC motor drives feature two cascaded closed-loop switching converter stages in the power path as shown in Fig. 1. First, a diode bridge supplies rectified line voltage to a boost converter, which is closed-loop controlled to provide input power factor correction. The boost converter charges a bulk energy storage capacitor to a voltage higher than the peak line voltage.
Finally a voltage-fed, step-down inverter is used to drive the brushless DC motor.
While this topology simplifies the design problem by breaking it up into two parts, it has some inherent drawbacks.
Overall system cost is increased by the need for two actively controlled conversion stages and a dedicated controller is needed for each power converter. Additionally, bulk energy storage capacitors are needed to provide decoupling between the two closed-loop converters and store 120Hz ripple energy. These capacitors are typically electrolytic and are physically large, expensive and failure prone, limiting the lifetime of the drive. Under certain conditions efficiency may be improved by the elimination of the boost stage.
This paper proposes a single stage topology [1-3] (Fig. 2) suitable for small to medium power systems with high inertia loads such as home appliances. This approach features a single controlled power stage which implements both conventional brushless DC motor speed control and a novel power factor correction strategy. With an appropriate current modulation strategy, the input current can be shaped and high input power factor can be obtained. Several current modulation schemes are presented and their benefits and limitations are analyzed.
Fig. 2: Proposed single stage approach with small switching-frequency capacitor filter
II.
S INGLE S TAGE A PPROACH
The power section of the brushless DC drive presented herein consists of three distinct elements as shown in Fig. 2.
A passive full-wave bridge rectifier is used to rectify incoming single phase line voltage. A small high frequency bus capacitor, which is used to reduce input current ripple at the switching frequency, stores negligible line frequency energy. Therefore, the rectified voltage is basically a rectified sine wave. Finally, a three-phase voltage source inverter unit modulates the bus voltage applied to the motor. A six-step commutation sequence is used with two active phases and one idle phase at any given time. As a result of phase commutation, the motor presents an approximately constant back-emf at the terminals corresponding to the active phases.
This system is equivalent to a Buck converter with a constant voltage load as shown in Fig. 3, where the inductor L represents the motor equivalent inductance. The Buck converter can be controlled to act as a power factor corrector and draw a quasi-sinusoidal current from the voltage bus. A
Buck converter is a non-ideal power factor corrector [4] because it cannot draw any input current whenever the input voltage is smaller than the output voltage. Therefore the input current waveform will have zero-current regions around the zero crossings of the bus voltage as in Fig. 4. Waveforms for two possible control strategies are shown: in Fig. 4a a sinusoidal-current reference is used and in Fig. 4b a

constant-current reference is used.
A block diagram of the proposed system is shown in Fig. 5.
The power stage with the diode bridge rectifier and the three-phase inverter is shown. The control is actually quite similar to a conventional brushless dc motor speed control with an inner current control loop. The motor Hall-effect sensor signals are used to determine the motor speed and to select the appropriate sector of operation. The speed error signal is the input to a PI compensation block. The output of this block is current reference i ' . The actual current ref reference is different for the two control strategies of Fig. 4: for the case of constant-current reference signal i ' is the ref actual current reference, whereas for the case of sinusoidal-current reference this signal is multiplied by the rectified bus voltage. Current i is the reference signal for ref the current loop. The current modulation block determines the switch command signal as a function of reference current i ref
and sensed current i s
. The sector selection logic block outputs the actual gate signals for the six switches of the inverter as a function of the switch command signal and of the
Hall effect signals.
+ v s
i s
L i b v b
+
-
Fig. 3: Simplified equivalent circuit for the single stage drive
Fig. 4: Rectified voltage and current waveforms for sinusoidal-current reference (a) and constant-current reference (b)
Fig. 5: System block diagram for the single stage drive
Idealized waveforms for the case of constant-current reference and sinusoidal-current reference are shown in
Fig. 6a and Fig. 6b respectively. The notation used in the analysis is as follows: a capital letter denotes the peak value of a variable, a small letter denotes the instantaneous value, average and rms values are denoted by subscripts. For example, v is the instantaneous rectified input voltage, s
V s is its peak value, V s _ avg
is the average value of the waveform and V s _ rms
is the rms value.
In Fig. 6 the rectified input voltage v is a rectified sine s wave v s
( γ ) = V s sin( γ ) (1)
At a given speed the motor back-emf voltage v is b constant. The input current i is controlled to follow either a s constant reference or a rectified sinusoidal reference. In both cases the waveform exhibits zero-current notches corresponding to the zero crossings of the rectified input voltage v . This happens because the Buck converter of s
Fig. 3 cannot draw any current if the input voltage is smaller than the output voltage V b
. The conduction angle ϑ is given by sin( ϑ )
V
=
V s b
(2)
The output current i can be easily calculated under the b assumption of negligible stored energy in the system. Under this assumption the instantaneous input power must be equal to the instantaneous output power and the input current is i b
= v s v b i s
(3)
Experimental and simulation results presented in a later section will show that this assumption is only approximately valid, because there is significant energy stored in the motor inductance.
For the case of constant-current reference, the output current is i b
( γ ) =



V
V b s I s sin( γ )
0
ϑ < γ < ( π / 2 elsewhere
− ϑ )
(4)
For the case of sinusoidal current reference the output current is i b
( γ ) =



V
V b s I s sin
2
0
( γ ) ϑ < γ < ( π / 2 elsewhere
− ϑ )
(5)
We can now derive formulas for several quantities of interest at a desired operating point characterized by peak input voltage V , output power P , and conduction angle s
ϑ .
III.
A NALYSIS OF S INGLE -S TAGE D RIVE W AVEFORMS
It is of interest to examine the waveforms of the single-stage drive. For simplicity the analysis is performed on the simplified Buck equivalent model shown in Fig. 3.

v s
V s
V b v s
V s
V b i s
θ
I s
θ v b
V b
ωt
I b i b
ωt
(a) v b
V b
ωt
ωt
ωt
I b i b
ωt i s
θ
I s
θ
ωt
(b)
Fig. 6: Idealized waveforms for the single stage drive
ωt
A.
Constant-Current Reference Case
For the constant-current reference case the peak input current is
P
I = s
V s
π
2 cos( ϑ )
(6)
I
The average input current is s _ avg
= I s



1 −
2
π
ϑ 


The rms input current is
(7)
I s _ rms
= I s
1 −
2 ϑ
π
The peak output current is
1
I b
= I s sin( ϑ )
The average output current is
2 cos( ϑ )
I b _ avg
= I b
π
The rms output current is
(8)
(9)
(10)
I b _ rms
=
I b 1 −
2 ϑ
π
+ sin( 2 ϑ )
π
(11)
2
The input current before the rectifying diode bridge is a three-level square wave with peak harmonic currents given by
I n _ for peak
=
4 I s cos( n ϑ n π n odd integer.
) (12)
B.
Sinusoidal-Current Reference Case
For the sinusoidal-current reference case the peak input current is
I s
=
2 P
V s 1 −
2 ϑ
+
1 sin( 2 ϑ
π π
The average input current is
)
2 cos( ϑ )
I s _ avg
= I s
π
The rms input current is
I s _ rms
=
I s 1 −
2 ϑ
π
+ sin( 2 ϑ )
2
The peak output current is
I = b
I s
1 sin( ϑ )
π
I
The average output current is b _ avg
=
I
2 b 


1 −
2
π
ϑ
+ sin(
π
2 ϑ ) 


I
The rms output current is b _ rms
=
I b ∆
2 π with
∆ =
3
2


π
2
− ϑ


+ sin( 2 ϑ ) + cos( 4 ϑ ) − 1
8
(13)
(14)
(15)
(16)
(17)
(18)
(19)
The input current before the rectifying diode bridge is a truncated sine wave with a peak fundamental current given by
I
1 _ peak
= I s
1 −
2 ϑ
π
+ sin(
π
2 ϑ )
(20)
The peak harmonic currents are given by
I n _ peak
=
2 I s
π sin
[
( n n
+ 1 ) ϑ
+ 1
] sin
[
−
( n n −
−
1
1 ) ϑ
] for n odd integer.
(21)
IV.
D ESIGN I SSUES FOR S INGLE -S TAGE D RIVE
In this section we discuss design issues related to the proposed single-stage drive. All design quantities calculated in the previous section are functions of only three variables: peak input voltage V , output power P , and conduction s angle ϑ . Typically the design requirements specify a nominal desired operating point: peak input voltage V , s output power P , and motor speed ω . The main design decision is to choose the motor torque constant K
T
, which determines the motor back-emf
V = b
K
T
ω
(22) which in turn determines the conduction angle ϑ according to (2). In conclusion, the main design decision is the choice of the conduction angle ϑ . This choice is dictated by two frequently conflicting requirements:

1.
The input current i must meet harmonic content s requirements
2.
The overall system efficiency is strongly affected by the choice of conduction angle ϑ .
Typically the input current harmonic content decreases as the conduction angle ϑ decreases. For example, in reference
[4] Spiazzi plots in Figs. 4-5 the maximum input power as a function of sin( ϑ ) in order to meet IEC 1000-3-2 Class A for both constant-reference current and sinusoidal-reference current. These plots can be used as a design guideline for the single-stage drive to determine the maximum conduction angle for which the standard limits are not exceeded. For different harmonic requirements, similar plots can be developed.
Regarding system efficiency it is important to understand the impact of conduction angle ϑ on the output (motor) current i . For a large value of b
ϑ the conduction interval becomes smaller and smaller and consequently the input and output currents must increase in magnitude in order to deliver the same average power to the motor. In the limit of
ϑ → π / 2 the input and output currents tend to infinity.
Therefore, for large values of ϑ the rms output current
I b _ rms
becomes large and the motor and inverter switch losses increase. On the other hand, for a small value of ϑ the motor back-emf V is small (see equation (2)) and the motor b current must become large in order to deliver the required power to the load. This also causes large motor and inverter switch losses. In the limit of ϑ → 0 the load current tends to infinity. It turns out that there is an optimal value of conduction angle ϑ that minimizes the rms load current
I b _ rms
. However, the minimum occurs at impractically large values of conduction angle ϑ . A normalized plot of rms output current I b _ rms
as a function of sin( ϑ ) for the sinusoidal-current reference case is shown in Fig. 7. The minimum occurs between 0.8 and 0.9, which is not a viable operating point. The plot for the constant-current reference case is similar. In conclusion a possible design strategy is to choose the maximum possible value of conduction angle ϑ that satisfies the input current harmonic requirements.
20
18
16
14
12
10
8
6
4
2
0
0 0.1
0.2
0.3
0.4
0.5
sin( θ )
0.6
0.7
0.8
0.9
1
Fig. 7: Plot of normalized rms output current as a function of sin( ϑ ) for the sinusoidal-current reference case
V.
D ESIGN E XAMPLE
A design example is described in this section for both constant-current reference and sinusoidal-current reference.
Input voltage
Motor speed
Load torque
Output power
220 Vrms
100 rad/s
4.0 Nm
400W
Table 1: Design example specifications
The design figures 4-5 in reference [4] (discussed in the previous section) show that the maximum input power for the constant-current reference case is less than 500W, whereas for the sinusoidal-current case it is significantly larger. The maximum input power actually tends to infinity as ϑ → 0 , because the input current becomes a pure sine wave. From these figures a value of sin( ϑ ) = 0 .
5 ( ϑ = 30 o
) is chosen for the constant-current reference case and a value of sin( ϑ ) = 0 .
6 ( ϑ = 37 o
) for the sinusoidal reference case.
Notice that a smaller value is required for the constant-current reference case. Once the conduction angle has been selected, quantities of interest can be calculated from equations
(6)-(21) and are shown in Table 2. The average and rms input currents I s _ avg
and I s _ rms
are comparable for the two cases.
In the sinusoidal-current reference case a larger value of motor back-emf V b
is allowable, which results in smaller average and rms output currents I b _ avg
and I b _ rms
, which would result in a 25% reduction in conduction losses in the motor. For the same values of conduction angle the output currents would be similar for the two cases.
Constant current reference case
Sinusoidal current reference case sin( ϑ ) 0.5 0.6
ϑ 30 ° 37 °

V [V] s
311 311
I s
[A]
2.33 2.87
I s _ avg
[A]
1.55 1.46
I s _ rms
[A]
1.90 1.92
V b
[V]
155.5 186.6
I b
[A]
4.66 4.78
I b _ avg
[A]
2.57 2.14
I b _ rms
[A]
3.20 2.78
Table 2: Calculated voltages and currents for design example
VI.
C OMPARISON TO C ONVENTIONAL T WO -S TAGE
A PPROACH
It is not easy to compare the proposed single-stage approach to a conventional two-stage solution using a Boost power factor preregulator. Reference [1] attempts such a comparison in terms of cost and efficiency for a specific design, but acknowledges the difficulty in making a fair comparison. In the proposed solution the Boost stage with its large electrolytic output capacitor is eliminated, but at the cost of higher stresses in the inverter switches, which result in the use of higher-rating, more expensive switches. Quantifying the cost connected to the higher switch stresses is difficult.
The conclusion was that there is a reduction in cost, corresponding to approximately 20% of the cost of the Boost stage.
Regarding efficiency, the losses in the Boost stage are eliminated, but the losses in the inverter stage and in the motor increase due to the increased rms currents. The conclusion of
[1] was that total losses are 25% larger in the proposed solution.
In order to compare losses in the single-stage drive and in a conventional two-stage drive we examine the rms motor current I b _ rms
for three different cases: two-stage drive, single-stage drive with constant-current control and single-stage drive with sinusoidal-current control.
For the two-stage case we examine the second stage only, the three-phase inverter stage. The three-phase inverter stage can be simplified to an equivalent Buck stage as in Fig. 3. In this case input voltage V is the output voltage of the Boost s stage and it is constant and larger that the peak input ac voltage. The input current is I , the motor back-emf voltage s is V and the motor current is b
I . All terminal quantities are b constant. Assuming for simplicity zero losses, we have
P = V s
I s
= V b
I b
(23)
In order to be able to compare the different cases, a base current is defined as
I b _ base
P
=
V s
(24)
This current represents the minimum possible value of the rms output current.
For the two-stage case, we have from (23)
I b _ rms
= I b _ base
V s
V b
(25)
For the constant-current case, substituting equations (6) and (9) into (11), we obtain
I b _ rms
= I b _ base
π
1 −
2 ϑ
π
+ sin( 2 ϑ )
π
(26)
2 sin( 2 ϑ )
For the sinusoidal-current case, substituting equations (13) and (16) into (18) we obtain
I b _ rms
I b _ base
2 ∆
=
π sin( ϑ )
1 −
2 ϑ
π
+ sin( 2 ϑ )
π
(27) with ∆ defined in (19). This is the equation that was actually plotted in Fig. 7.
Normalized plots of the rms output currents given by equations (25), (26), (27) are shown in Fig. 8 as a function of the ratio of output voltage to input voltage, which is equal to sin( ϑ ) for the single-stage case as shown in (2). Notice that the input voltage V represents the voltage stress on the s inverter switches. For the same value of the voltage ratio, the two-stage case exhibits a lower rms current, because the load current is constant for that case. The normalized load currents decrease as the voltage ratio approaches unity. The big advantage of the single-stage design is that it is possible to operate with a voltage ratio close to unity, where the normalized rms current approaches its minimum value of unity. On the other hand, in the case of the single-stage approach the voltage ratio is limited to values significantly smaller than unity, in order to satisfy input current harmonic content requirements, which may cause the normalized current to be significantly larger than unity. Fig. 8 provides a way to quantify the penalty in term of rms current as compared to the two-stage case. These losses can offset the
Boost stage losses eliminated in the single-stage approach.
Values of the normalized output current are tabulated in Table
3 for the single-stage case. Notice that, for the two-stage case, in order to minimize the output rms current, a small voltage ratio, say 0.9, can be chosen, which gives a normalized output current of 1.11. This value should be compared with the values in Table 3.

15
10
5
Two stage
Single-stage, constant current
Single-stage, sinusoidal current
0
0.1
0.2
0.3
0.8
0.9
0.4
0.5
0.6
sin( θ ), V b
/ V s
0.7
Fig. 8: Plot of normalized rms output current as a function of sin( ϑ ) ,
V b
/ V s
for three different cases
0.50
0.55
0.60
0.65
0.70
0.75
0.80
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45 sin( ϑ ) I b _ rms
/ I b _ base
Constant reference
11.16
7.48
5.65
4.57
3.85
3.35 current Sinusoidal reference
12.35
8.26
6.21
4.98
4.16
3.57
2.98
2.70
2.49
2.32
2.19
2.09
2.02
1.97
3.13
2.80
2.53
2.33
2.16
2.03
1.93
1.85
1.96 1.82
Table 3: Normalized rms output current current cycles larger than 50% [5]. Looking at Fig. 4a it is clear that to command a square-wave input current the motor current reference should be a sine wave, i.e., it should be proportional to the rectified input voltage. Similarly Fig. 4b shows that, in order to command a sinusoidal input current, the reference motor current should be proportional to the square of the rectified input voltage.
The second implementation directly controls the average input current utilizing charge control [6], which uses the one-cycle-control approach of controlling the integral of the quantity of interest, in this case the input current [7]. As shown in Fig. 9, the state of the active switch is controlled by a flip-flop, which is set by a clock at a constant frequency.
The reset is determined by a comparator, which compares the integral of the input current i s
with quantity i ref
T , where T is the switching period. The reset of the flip-flop causes the reset of the integrator. This control approach forces the average input current to be equal to reference current i . ref
Both implementations provide constant frequency operation and fast dynamic response. Experimental results presented in a later section show that the charge control method gives better performance.
Fig. 9: Block diagram of charge (one-cycle) control
VII.
C URRENT M ODULATION S TRATEGY
The implementation of the current modulation strategy block of Fig. 5 is now discussed. The purpose of this block is to make average input current i equal to reference current s i . Notice that the input current is actually a square wave. ref
Two possible implementations are briefly discussed.
The first implementation controls the input current indirectly by controlling the motor current. With no significant energy stored in the drive itself and assuming a very small motor stator inductance, there is very little electrical energy stored in the system at any time. Thus, electrical power must be balanced throughout the system at each instant in time. With this assumption, controlling the power on the motor side of the inverter indirectly controls the power taken from the line. Peak current mode control (PCM) may be used provided that the appropriate motor current reference is used. An artificial ramp may be needed to prevent instability of peak current mode control for duty
VIII.
S IMULATION R ESULTS
A SPICE circuit simulation was performed on the simplified equivalent circuit of Fig. 3. Commutation of phase current was ignored. Both desired input current shapes were simulated with each of the modulation strategies described above. Peak Current Mode modulation results are shown first. Fig. 10 shows the case of i ref
proportional to v s
, which corresponds to square wave input current. It can be seen that i b
is well controlled and proportional to v s
. Since the stator inductance L was included in this simulation, the input current i s
is distorted. Less current is taken from the line in the region where v s
is decreasing, because energy stored in the inductance is delivered to the motor shaft. This clearly shows the limitations of the modulation strategy to produce a square shaped input current. Fig. 11 shows the case of i ref proportional to v s
2
, which corresponds to a sinusoidal input current. This shows that i b
is a sinusoid with a minimum value at zero. The input current i s
resembles a rectified sine wave with less current taken in the region of decreasing v s
.

Fig. 10: Simulation Results (PCM, iref α vs) Fig. 12: Simulation Results (One-Cycle i ref
constant)
Fig. 11: Simulation Results (PCM i ref
α v s
2
)
Fig. 12 and Fig. 13 show the same desired input current shapes as above using a One-Cycle current modulation strategy. Fig. 12 is the square input current case where i ref is constant. It is seen that i s is essentially square and that the peak of i b
has been delayed into the region of decreasing v s
.
This modulation strategy clearly rejects the disturbance of energy recovery from the motor inductance. Fig. 13 further demonstrates the effectiveness of this modulation method.
Here i ref
is proportional to v s
, forcing i s
to track v s
. Again, the peak of i b
is seen to be forced into the region of decreasing v s
.
This case provides the best case input power factor.
Fig. 13: Simulation Results (One-Cycle i ref
α v s
)
IX.
E XPERIMENTAL R ESULTS
Experimental testing of input current shapes and modulation strategies were performed using a test platform developed at the University of South Carolina. This platform consists of a custom made axial flux brushless dc motor, an
IRAMY20UP60B IGBT-based inverter, and a Xilinx
VirtexII FPGA control board. This pre-packaged inverter module limits instantaneous maximum switch current to 25 amps. The brushless dc (BLDC) motor used for the experiment has a motor constant of 0.14 N-m/A, resulting in v b
= 22V @ 1500 rpm. This yields small values of θ within the speed range tested. The effects of phase current commutation are visible in all waveforms below. Peak
Current Mode modulation strategy results are shown first for each input current shape, and the One-Cycle results follow. A

DC-50MHz current probe was attached to a single motor phase to acquire i b
and the incoming AC line to acquire i s
.
Fig. 14 and Fig. 15 show experimental results for the case of i ref
proportional to v s
using PCM modulation. Fig. 14 confirms that the phase current tracks v s
well. Several sectors are visible in the phase current waveform. From left to right: the measured leg becomes an active source, return leg changes, measured leg becomes idle, measured leg becomes an active sink. In this way, a six-step rotating magnetic field is established in the machine and a torque is generated.
Fig. 15 clearly shows that the PCM controller is unable to enforce a constant input current in the region of decreasing v s as expected from simulation.
Fig. 16: PCM i ref
α v s
2
, i b
(blue) and v s
(red)
Fig. 14: PCM i ref
α v s
, i b
(blue) and v s
(red)
Fig. 15: PCM i ref
α v s
, i s
(blue) and v s
(red)
Fig. 16 and Fig. 17 show the case of i ref
proportional to v s
2 with PCM modulation. The phase current is clearly a sinusoid with minimum value of zero. The input current tracks v s
when v s
is increasing and is distorted in the region of decreasing v s
.
Due to this effect, the input current zero regions are asymmetric.
Fig. 17: PCM i ref
α v s
2
, i s
(blue) and v s
(red)
The following experimental results show the same desired input current wave shapes repeated using a One-Cycle current controller. Fig. 18 and Fig. 19 show the case where i ref
is a constant. The input current is shown to be approximately square, significantly improved with respect to the PCM case, but this control is also unable to maintain a constant current in the region of decreasing v s
. Note that this implementation does not account for propagation delay of the switch commands and for the turn off time of the slow IGBT switches. As a result, more input current is taken from the line than expected by the controller and complete rejection of the inductive energy recovery disturbance is not achieved.
Fig. 18: v s
and i s
(One-Cycle i ref
= constant)

Fig. 19: v b
and i b
(One-Cycle i ref
= constant)
Fig. 20 and Fig. 21 show the case of i ref
proportional to vs.
Here, it can be seen that the input current closely follows the input voltage, resulting in a good power factor. The regions of zero input current are symmetric. Fig. 21 shows that the peak of the phase current is delayed into the region of decreasing v s
as expected from simulation. using a sinusoidal input current wave shape. This comes at the expense of decreased power throughput. For the first four odd harmonics, the percentages of harmonic content vs. fundamental current in the constant i ref
case were found to be
29.1%, 13.4%, 10.1% and 4.9%. The same percentages in the i ref
proportional to v s
case were found to be 3.5%, 4.8%, 3.5% and 3.1%.
2250 1
2000
1750
0.9
0.8
0.7
1500
1250
1000
0.6
0.5
0.4
750
0.3
500
250
0.2
0.1
0
1 3 5
0
Fig. 22: Input Current Harmonic Content (One-Cycle i ref
= constant)
2000
1800
1600
7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
Harm onic Order
1
0.9
0.8
1400
1200
1000
800
600
400
200
0
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
Harm onic Order
Fig. 23: Input Current Harmonic Content (One-Cycle i ref
α v s
)
Fig. 20: v s
and i s
(One-Cycle i ref
α v bus
)
Finally, experiments were performed to test the behavior of the speed control loop. A Magtrol HD-810-6N dynamometer and DSP6001 dynamometer controller were used to provide a shaft load and to extract speed and torque waveforms. Fig. 24 shows the shaft speed and mechanical torque generated for a system startup under light load. 25% overshoot was observed and the system settles in approximately 5 seconds. The bandwidth of the control is currently limited due to a problem in the hall-effect sensor to FPGA interface circuitry.
Intermittent speed detection errors result. This causes jitter in the shaft speed and prevents the system from reaching a true steady state. Fig. 25 shows the shaft speed response to a load torque step. The response, though slow, indicates proper operation of the speed control loop and good steady-state rejection of a step load torque disturbance.
Fig. 21: v s
and i s
(One-Cycle i ref
α v bus
)
Harmonic content of the input current was extracted using a
Fast Fourier Transform performed on a LeCroy 6100A 5GS/s oscilloscope. Fig. 22 shows the case of constant i ref
and
Fig. 23 shows i ref
proportional to v s
. As these figures show, the first few odd harmonics are attenuated significantly by

Fig. 24. Speed Response at Startup (N ref
= 500rpm) as future work.
In the proposed drive the input current presents zero-current notches around the ac voltage zero crossings. It is possible to add extra circuitry in order to reduce these notches. A possible approach is shown in Fig. 26. A bidirectional Buck-Boost converter is added after the bridge rectifier. During the zero-current intervals, when the rectified input voltage dips below the motor back-emf, the converter can be controlled to draw a current from the input. The corresponding energy is stored in the output capacitor. When the rectified input voltage becomes larger than the motor back-emf, the three-phase inverter can deliver power to the motor. In this period the bidirectional Buck-Boost converter can be operated to return the stored energy to the inverter.
The Buck-Boost converter can be designed to handle only a small energy as necessary to meet input current harmonic requirements. As a result the cost of this converter can be smaller than the cost of a conventional Boost power factor corrector. See [4] for details.
Fig. 26: Drive with added bidirectional Buck-Boost converter
Fig. 25. Speed Response to Torque Step (N ref
= 500rpm)
X.
D ISCUSSION AND C ONCLUSION
The viability of the proposed approach has been demonstrated through simulation and experimental results. A number of observations can be made.
Regarding the speed control loop, the achievable bandwidth is ultimately limited by the 120Hz torque ripple present on the motor. However, for the proposed target applications in low-cost home appliances with high inertia loads, this limitation does not appear to be a serious problem.
The charge (one-cycle) modulation method appears superior to conventional peak current mode control, because it compensates for the energy stored in the motor inductance providing a more ideal input current waveform.
Experimental results show the effects of sector commutation. During sector commutations the inverter input current temporarily drops to zero. The effect of this on the ac side current is somewhat filtered by the high-frequency capacitor placed after the diode bridge, but current glitches are clearly discernible. In general sector commutations are asynchronous with respect to line frequency. At specific speeds sector commutations may become synchronous with the 120Hz line frequency commutations, but this has no adverse effect on the system. It is possible to reduce or eliminate these glitches by energizing all three phases during sector commutation, so that the motor draws an approximately constant current. Implementation of this is left
A CKNOWLEDGMENT
This work was supported by the National Science
Foundation under grant ECS-0348433. The support of
National Rectifier is gratefully acknowledged.
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