A Critical-Conduction-Mode Single-Stage Power-Factor-Correction Electronic
Ballast*
Fengfeng Tao and Fred C. Lee
Center for Power Electronics Systems
Virginia Polytechnic Institute and State University
Blacksburg, VA 24061-0111
ABSTRACT
A critical-conduction-mode single-stage power-factorcorrection (PFC) electronic ballast is presented in this paper.
The proposed ballast combines the power-factor-correction
stage with a conventional half bridge DC/AC inverter into a
single-stage to reduce the cost. The power factor correction
stage is a boost-like converter operating in critical conduction
mode so that a high power factor is achieved naturally. By
exploiting voltage divider, the ratio of line voltage to dc-bus
voltage can be chosen as a large value of near one yet achieves a
good power factor. Theoretical analysis and experimental
results for two 45-watt fluorescent lamps are presented.
I.
INTRODUCTION
High-frequency electronic ballasts for gas discharge lamps
are used widely in lighting systems today because of their
merits of small size, light weight, high light luminous
efficiency, no flicker, no audible noise, and long life [1].
Currently, the electronic ballast has to meet the regulation of
IEC 1000-3-2 class C to reduce the line rms current and linecurrent harmonic distortion. The power line then can be
utilized more efficiently. Usually, a two-stage approach with
a PFC stage followed by a DC/AC inverter stage is used. The
two-stage approach has good performances such as a nearunity power factor and wide range of line input voltage
variation. Besides, the design procedure is relatively easy.
The main problem of the two-stage approach is that it has
more components and, thus, a high cost. This is not good for
cost-sensitive products. Several single-stage PFC electronic
ballasts, aimed at reducing the cost, have been proposed
previously [4-10]. In the single-stage approach, the PFC stage
is combined with the DC/AC inverter stage into one single
stage; one switch and its controller can be saved, and
consequently the cost is reduced. The most commonly used
method is to combine a boost converter with the DC/AC
inverter stage by sharing a common switch [4-7]. A high
power factor can be achieved by deliberately operating the
boost inductor in the discontinuous conduction mode (DCM)
with constant duty-cycle control. However, there exist several
problems for the DCM operation. It draws pulsating input
current and requires a relatively large input filter. Second, the
*
peak switch current of the PFC stage is much higher, so that a
high-current rating device has to be used. In addition, the bus
voltage has to be designed high enough to avoid the nonlinear term of the averaged line current [12]. High-voltage
rating devices may be required. J. Alonso et al. presented a
DCM flyback semi-stage as the PFC stage to solve the third
problem [9]. However, a DCM flyback converter needs a
gaped transformer and usually has a lower efficiency. M. A.
CÏ et al. proposed a good topology where the PFC stage
operates in critical conduction mode to solve the abovementioned problems [10]. The problem is that a transformer
is necessary to couple the bus voltage. Taking into account
the transformer ratio, the peak switching current of the PFC
stage is even bigger than that of DCM boost at the same
power factor condition. Four fast recovery diodes are also
necessary to rectify the boost inductor current. Component
counts increase, which may increase the cost.
In this paper, a critical-conduction-mode single-stage PFC
ballast is presented and analyzed. The presented single-stage
electronic ballast employs two small capacitors as a voltage
divider to half the rectified line voltage so that three-level
voltage is obtained. The boost inductor is arranged in such a
way that the inductor current naturally operates in criticalconduction-mode. Because of voltage divider, the effective
ratio of the bus voltage to line peak can be doubled to reduce
the line current distortion [12]. The magnitude of the dc-link
current is the same as that of [10]. Like in [10], the dc-link
current frequency is twice the switching frequency and the
switching ripple currents are removed with a small input
filter, and the two voltage-divider capacitors also function as
filter capacitors. Compared with [10], the presented circuit
only adds one boost inductor with a smaller value (about onefourth), two fast recovery diodes, and two small capacitors to
the non-PFC electronic ballast. It has a good performance and
a low cost. In the next section, the critical-conduction-mode
single-stage PFC electronic ballast is first derived. The
operation principle is analyzed in Section III. Based on the
steady-state analysis, design equations are derived. Section
IV provides the simulation and experimental results to verify
the theoretical analysis. The paper is concluded in Section V.
This work was sponsored by Matsushita Electric Works (MEW), Ltd, JAPAN, and supported in part by the ERC Program of the National
Science Foundation under Award Number EEC-9731677.
CIRCUIT DERIVATION
LB
DB
S1
Cd
SB
S2
DCM Boost PFC
PRINCIPLE OF THE CIRCUIT
In order to simplify the analysis, some assumptions are
made as follows.
1) MOSFETs M1 and M2 operate complementarily with a
fixed frequency of 0.5 duty ratio.
2) The bus capacitance, CB, is large enough to be
considered a voltage source.
3) Bus voltage, VB, is always higher than the line peak.
4) The voltages across the filter capacitor, Cf, and voltage
divider capacitors, Cd1 and Cd2, keep constant during a
switching cycle since switching frequency is high
enough that capacitor impedance is much lower than
load.
5) The lamps are modeled as a resistor, Rla, at steady state.
Based on the above assumption, the proposed circuit can
be de-coupled as two independent circuits, as shown in Fig. 3
and Fig. 4. The circuit shown in Fig. 3 is a series-resonant
parallel-load inverter and was well analyzed in [2]. The
circuit shown in Fig. 4 is the PFC converter. Based on the
assumption 4), the voltage Vin1 equals Vin2, half of the
rectified line voltage, Vin. This paper will focus on the
steady-state analysis of the circuit in Fig. 4.
Cr
DC/AC Inverter
(a)
DD1
SB1
V in1
DB2
S1
LB
Cd
Lr
CB
DB1
V in2
SB2
S2
Cr
DD2
Critical-conduction-mode Boost PFC
(b)
DC/AC Inverter
Fig. 1 Two-stage power-factor-correction electronic ballast
DD1
C d1
Lf
M1
LB
Vg
Cc
Lr
CB
Cf
M2
C d2
III.
Lr
CB
Lamp
Vg
Lamp
Fig. 1(a) shows a conventionally used two-stage PFC
electronic ballast with a boost converter followed by a seriesresonant parallel-loaded inverter. The boost converter usually
operates in DCM for low power applications and in CCM for
high power applications. If the PFC stage is split into two
cells and shares a common boost inductor, a criticalconduction-mode boost converter is obtained, which is shown
in Fig. 1(b). Two diodes, DD1 and DD2, are inserted in series
with the voltage source to ensure unidirectional input current.
Two switches, SB1 and SB2, operate in 1800 out of phase so
that the boost inductor current never stays at zero. This makes
the critical conduction mode operation for the rectified boost
inductor current. However, two more switches are used,
which is not desirable for low-power applications. In the
literature, researchers have proposed a systematic strategy to
integrate a two-stage approach into a single-stage approach to
save a switch and control [4-10].
Actually, two
complementary switches already exist in the inverter stage. It
is easy to combine the two boost cells with the inverter stage.
Fig. 2 shows the proposed circuit. MOSFETs M 1 and M2
perform the switching function of SB1 and SB2. The function
of boost diode, DB1 and DB2, is performed by the body diodes
of M2 and M1. Two capacitors, Cd1 and Cd2, function as the
two rectified voltage source, Vin1 and Vin2. So, with this
configuration, adding two capacitors and one boost inductor
can obtain a critical-conduction-mode boost converter to
achieve PFC to the electronic ballast.
Cr
Lamp
II.
DD2
Fig. 2 Critical-conduction-mode single-stage power-factorcorrection electronic ballast
In steady stage, four topological stages exist in one
switching cycle, as shown in Fig. 5. Key waveforms are
shown in Fig. 6. The operation principle is as follows.
[t0, t1]linear charging LB :
Before t0, switch M2 is off and body diode D1
conducts the inductor current, iLb. The gate drive
voltage for M1 has already been applied when D1
conducting current. At t0, iLb becomes zero. The
diode DD1 is turned on by the voltage Vin1, and the
diode DD2 is turned off by the negative voltage
(Vin1+Vin2-VB). The inductor current iLb linearly
increases by the voltage Vin1. Fig. 5(a) shows the
equivalent circuit.
[t1, t2]linear discharging LB :
Switch M1 is turned off at t1. The positive inductor
current forces the diode DD2 and the body diode D2
turn on. The negative voltage (VB-Vin1) is applied
to the inductor, causing the current of iLB to
i in
DD1
M1
Cc
S1
V in1
Lr
LB
VB
D1
i LB
VB
M2
Lamp
V in
Cr
S2
V in2
D2
DD2
i LB2
Fig. 4 Simplified critical-conduction-mode powerfactor-correction converter
Fig. 3 Half-bridge series-resonant parallel-load
inverter
i in
DD1
i in
DD1
V Lb
1
(2VB - Vin )
2
S1
V in1
D1
VB
V in
LB
D2
1
− (2VB - Vin )
2
i Lb
(b)
i in
S1
D1
S2
S1
LB
VB
D2
I Lm
DD1
V in1
i LB
V in
V in2
D2
t
1
Vin
2
DD2
DD1
LB
−
i LB
S2
V in2
DD2
V in1
1
Vin
2
VB
LB
(a)
i in
D1
V in
i LB
S2
V in2
S1
V in1
-I Lm
i LB
VB
V in
S2
V in2
t
1
TS −
2
D1
D2
i in
I Lm
|i Lb|
I in_m
DD2
(c)
DD2
(d)
Fig. 5 Topological stages within one switching cycle
decrease linearly. At time t2, the inductor current
becomes zero, and ends this mode.
[t2, t3]linear charging LB :
The inductor current becomes zero at time t2. The
switch M2 is turned on at ZVS. The diode DD1 is
turned off by the negative voltage (Vin1+Vin2-VB).
The inductor current linearly increases by the
voltage Vin2. The equivalent circuit is shown in Fig.
5(c).
[t3, t4]linear discharging LB:
Switch M2 is turned off at t3. Due to the negative
inductor current iLB, the body diode of M1 is forced
to turn on, and diverts the inductor current from M2
to diode D1. The voltage source (VB- Vin2) is
t0
t1
t2
t3
t4
t
Fig. 6 Key switching waveforms of the circuit
applied to the boost inductor, LB, and inductor
current linearly decreases. The equivalent circuit is
shown in Fig. 5(d). This mode ends at t4, where a
new switching cycle begins.
From the above analysis, it can be seen that the boost
inductor current iLB operates bi-directionally. The charging
voltage is half of the rectified line voltage and the
discharging voltage equals the bus voltage minus half the
rectified line voltage. The peak inductor current naturally
follows the sinusoidal line voltage waveform. Because the
ratio of charging voltage to discharging voltage is small
compared with the DCM boost PFC converter at the same
bus voltage, the non-linear term of the line current will be
small. Due to the rectifier-bridge composed with DD1, DD2,
D1, and D2, the dc-link current frequency is twice the
switching frequency. The ripple current can be removed with
a smaller input filter than that for a DCM boost PFC
converter. In the following, the equations of line current,
power factor, THD, and circuit parameters are derived.
A. Input Current, power factor, and THD
From Fig. 6, the boost inductor peak current, Ipk, during
one switching cycle is given by
1
⋅ Vin
1
⋅ ( TS − τ )
I pk = 2
Lb
2
(1)
1
(VB − ⋅ Vin )
2
=
⋅τ
Lb
where TS is the switching period, and τ is the linear
discharging time.
From (1), the linear discharging time is given by
Vin
TS
4 ⋅ VB
The peak current Ipk can be obtained as
T
V
I pk = S ⋅ (1 − in ) ⋅ Vin
4 Lb
2VB
τ=
(2)
(3)
The dc-link current iin equals to half of the iLB. Due to the
input filter and rectifier, the instantaneous line current equals
the average dc-link current over one switching cycle, which
is given by
1
1
| iG |= iin ,ave = ( iLB ) ave = [ I pk + 0]
2
4
TS
Vin
=
[1 −
]Vin
16 Lb
2VB
(4)
=
TSVB
V
V
⋅ (1 − in ) ⋅ in
8Lb
2VB 2VB
1
v g ⋅ i g dθ
π 0
∫
π
=
1
V p sin θ ⋅ [ K (1 − α ⋅ sin θ ) ⋅ α ⋅ sin θ ]dθ
π 0
∫
= V p Kα
y
π
(6)
1
4
where y ≡ π − α
2
3
The power factor is defined as the ratio of real power to
appearance power, and is given as
Pin
2 y
PF =
=
⋅
(7)
V g , rms ⋅ I rms
π
Z
If displacement is assumed unit, the THD can be obtained
by
1
⋅ 1 − PF 2
THD =
PF
(8)
2y2
π
Z
=
⋅
1−
πZ
2 y
Fig. 7 and Fig. 8 show the power factor and THD curve as
a function of α. The curves are the same as those in [10]
because the boost inductor operates in the same conduction
mode if seen from the line input.
B. Circuit parameters
The main circuit parameters of the proposed circuit are
boost inductance, LB, resonant inductance, Lr, and resonant
1
0.997
0.994
PF
j
0.991
= K ⋅ (1 − α ⋅ sin ω l t ) ⋅ α ⋅ sin ω l t
where
0.988
Vp
TS V B
, and α ≡
.
8Lb
2V B
Equation (4) shows that line current will contain certain
distortion due to the non-linear term of (1 − α ⋅ sin ω l t ) .
The line rms current is given by
line voltage v g = V p sin ω l t , K ≡
π
I rms
π
Pin =
∫
∫
3
0.1
0.2
0.3
0.4
0.5
j
Fig. 7 Power factor as a function of α
15
12
9
(5)
THD
j
6
Z
π
3
where Z ≡ π − 8 α + 3π α 2
2
0
α
π
1 2
1
=
ig dθ =
K (1 − α ⋅ sin θ ) ⋅ α ⋅ sin θ ]dθ
π 0
π 0
= Kα ⋅
0.985
8
The input real power is given by
0
0
0.1
0.2
0.3
α
j
0.4
0.5
Fig. 8 Total harmonic distortion as a function of α
capacitance, Cr.
Based on the power balance between the input and output,
or
Po = η ⋅ Pin
(9)
where Po is the output power, and η is the conversion
efficiency, the boost inductance, LB, can be obtained by
η ⋅ y ⋅ TS 2
LB =
Vp
(10)
16π ⋅ Po
By using the fundamental component approximation [2],
the series-resonant parallel-load circuit can be described by
1
• The corner frequency: ω o =
Lr C r
1
1− 2
QL
•
the resonant frequency: ω r = ω o
•
the characteristic impedance: Z o =
Lr
Cr
quality factor:
Vla =
2 ⋅ VB
⋅
π
I la =
2 ⋅ VB
⋅
π
QL =
1
ω
1 ωS 2
[1 − ( S ) 2 ] 2 + [
⋅ ( )]
ωo
QL ω o
The rms lamp current is given by
1
(11)
(12)
ωS 2 2 ωS 2
Z o ⋅ Q ⋅ [1 − ( ) ] + ( )
ωo
ωo
The peak value of the switch current (only the inverter
stage is considered) is given by
ω
1 + (Q L ⋅ S ) 2
ωo
2V
I Spk = B ⋅
(13)
π
ωS 2 2 ωS 2
2
Z o ⋅ Q L ⋅ [1 − ( ) ] + ( )
ωo
ωo
The resonant tank should provide high starting voltage to
start up the lamp and current limiting to stabilize lamp
operation after start-up. From equation (11), the output
voltage will be sufficiently high due to the very high quality
factor before the fluorescent lamps are turned on. At the
steady state, the resonant tank provides lamp current
specified by equation (12). The lamp voltage is described by
equation (11). Choose an operation frequency slightly greater
than ωo, say ω S = k S ⋅ ω o ; the quality factor, QL, and the
characteristic impedance, Zo, can be obtained from equation
(11), which are given by
2
L
kS
2 ⋅ VB 2
(
) − (1 − k S2 ) 2
πVla
(14)
Rla
(15)
QL
The resonant inductance and capacitance is obtained as
Z ⋅k
Lr = o S
(16)
ωS
Zo =
Cr =
kS
Zo ⋅ωS
(17)
For a given bus voltage, VB, switching frequency, ωs, lamp
power, and kS, the resonant parameters can be calculated
from (14) to (17).
IV.
Rla
Zo
The rms lamp voltage (output voltage) is given by
•
QL =
SIMULATION AND EXPERIMENTAL RESULTS
The proposed critical-conduction-mode single-stage PFC
electronic ballast was simulated using Pspice to verify circuit
operation with 200-Vrms line input and 85 watt lamp power.
The simulated waveforms are shown in Fig. 9. The line
current is sinusoidal with non-linear distortion. The switching
waveforms are in good agreement with the waveforms in Fig.
6. A prototype was built based on the above analysis. The
lamp voltage for two lamps in series is about 230 Vrms, and
lamp resistance is 620 Ω. If the switching frequency is
selected to be 52 kHz, V B =1.1VP =311 V, kS = 1.05, and η =
85%, the boost inductor, LB, resonant inductor, Lr, and
resonant capacitor, Cr, can be calculated using equations (10)
and (14 –17)
LB =323 µH Lr =1.14 mH
Cr =9.2 nH
The parameters of the input filter and voltage divider are
Lf =3mH
Cf =0.22 µH
Cd1 =Cd2 =0.33 µH
Fig. 10 shows the measured line current waveform with a
0.969 power factor and 21.2% THD. The THD is worse than
that of calculated results because there exists a severe reverse
recovery problem near line zero crossing for diodes DD1 and
DD2. However, each measured harmonic component still
meets the IEC1000-3-2 Class C requirement. The rectified
line voltage and boost inductor current waveforms are shown
in Fig. 11. The envelope of the boost inductor current follows
the line voltage. The measured switching-current waveform
is shown in Fig. 12. It is seen that the ZVS is ensured over
the line cycle. The maximum switching current is about
2.83A. The lamp current envelope is shown in Fig. 13 with a
flat envelope of 1.48 crest factor. The measured efficiency is
83.7% except for filament loss.
v in
vg
i Lb
ig
(a)
t: 2 ms/div
v in: 100 V/div
i : 2 A/div
Fig. 11 Measured boost inductor current envelope
V Lb
i Lb
vg
iS
|i Lb|
ig
i in
(b)
Fig. 9 (a) Simulated line voltage and current waveforms
and (b) switching waveforms
t: 2 ms/div
v g: 100 V/div
iS : 2 A/div
Fig. 12 Measured switching-current envelope
vg
ig
t: 2 ms/div
v g: 100 V/div
i g: 0.5 A/div
Fig. 10 Measured line voltage and current waveforms
V.
CONCLUSION
A critical-conduction-mode single-stage PFC electronic
ballast was proposed, analyzed, and implemented in this
t: 2 ms/div
i la: 0.2 A/div
Fig. 13 Measured lamp current waveform
paper. The proposed circuit has features of simple structure,
critical-conduction line current, and high power factor with
low harmonic distortion. The circuit also features low lamp
current crest factor, and simple structure with potential low
cost.
[7]
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