14
JOURNAL OF ELECTRONIC SCIENCE AND TECHNOLOGY, VOL. 13, NO. 1, MARCH 2015
Efficient Slew-Rate Enhanced Operational
Transconductance Amplifier
Xiao-Peng Wan, Fei-Xiang Zhang, Shao-Wei Zhen, Ya-Juan He, and Ping Luo
Abstract⎯Today, along with the prevalent use of
portable equipment, wireless, and other battery
powered systems, the demand for amplifiers with a high
gain-bandwidth product (GBW), slew rate (SR), and at
the same time very low static power dissipation is
growing. In this work, an operational transconductance
amplifier (OTA) with an enhanced SR is proposed. By
inserting a sensing resistor in the input port of the
current mirror in the OTA, the voltage drop across the
resistor is converted into an output current containing a
term in proportion to the square of the voltage, and then
the SR of the proposed OTA is significantly enhanced
and the current dissipation can be reduced. The
proposed OTA is designed and simulated with a 0.5 μm
complementary metal oxide semiconductor (CMOS)
process. The simulation results show that the SR is 4.54
V/μs, increased by 8.25 times than that of the
conventional design, while the current dissipation is only
87.3%.
Index Terms⎯Efficient, gain-bandwidth product,
operational transconductance amplifier, slew rate.
1. Introduction
It is well known that the amplifier is the fundamental
module in most analog and mixed circuits. And the
operational transcondutance amplifier (OTA)[1] is one of the
most widely used, which is usually used to drive a
capacitive load or a pass transistor in a low dropout
Manuscript received May 4, 2014; revised August 8, 2014. This work
was supported in part by the National Natural Science Foundation of
China under Grant No. 61274027 and the National Key Laboratory of
Analog Integrated Circuit under Grant No. 9140c90503140c09048.
X.-P. Wan and F.-X. Zhang are with the School of Microelectronics and
Solid-State Electronics, University of Electronic Science and Technology
of China, Chengdu 610054, China (e-mail: wxp316@163.com;
fx.zhang@foxmail.com).
S.-W. Zhen is with the School of Microelectronics and Solid-State
Electronics, University of Electronic Science and Technology of China,
Chengdu
610054,
China
(Corresponding
author
e-mail:
swzhen@uestc.edu.cn).
Y.-J. He and P. Luo are with the School of Microelectronics and
Solid-State Electronics, University of Electronic Science and Technology
of China, Chengdu 610054, China (e-mail: yajuan.he@gmail.com;
pingl@uestc.edu.cn).
Digital Object Identifier: 10.3969/j.issn.1674-862X.2015.01.004
regulator (LDR). But due to the limitation of tail current,
the driving capability of conventional OTA is weak. And
improving the slew rate (SR) is inevitably at the cost of
more static power consumption. Today, along with the
prevalent use of portable equipment, wireless, and other
battery powered systems, the demand for amplifiers with
high gain-bandwidth product (GBW), SR, and at the same
time very low static power dissipation is growing.
Slew rate enhancement (SRE) techniques have been
developed in recent years to solve the problem. Different
techniques have been suggested. For example, the dynamic
biasing technique[2]−[4] was used to enhance the SR by
increasing the bias current of the input differential pair
when the differential-mode input voltage was large.
Another differential pair was added to sense the input
voltage. In [5]−[8], auxiliary branches carried the extra
current required by charging/discharging the load during
slewing and the core operational amplifier (op amp) would
remain unaffected. Both the main amplifier and SRE op
amp sensed the same input signal. The SRE amplifier then
needed to detect the slewing condition and inject an extra
current to the output node. In [9] and [10], the class-AB
input stage was used to produce a larger dynamic output
current compared with a common differential input pair.
In this paper, a SR enhancement structure is proposed,
which transforms a conventional OTA into an efficient one
without the static power dissipation or input capacitance
increase. To increase the SR, a sensing resistor in series
with the diode connecting the metal oxide semiconductor
(MOS) transistors of the current mirror is applied. Unlike
the diode configured MOS transistor of which the voltage
drop is in proportion to the square root of current, it is a
linear relationship between the voltage across the resistor
and the current through it. Therefore, the voltage drop
across the resistor is converted into an output current
containing a term in proportion to the square of the voltage
by the single-transistor amplifier in the current mirror. The
proposed structure, which will be shown below, leads to the
essential SR and GBW improvements.
The paper is organized as follows. Section 2 briefly
describes the performance of the conventional OTA and the
limitation. The proposed SRE technique with the details of
its circuit implementation is brought in Section 3. Section 4
presents the simulation results. The paper is concluded in
Section 5.
15
WAN et al.: Efficient Slew-Rate Enhanced Operational Transconductance Amplifier
2. Conventional OTA
The conventional OTA is shown in Fig. 1. The
p-channel differential input stage comprised of M3L and
M3R converts the input voltage into currents. Mirrors
consisting of M1L, M2L and M1R, M2R mirror the currents to
the output stage. The current generated by the mirror of M1L
and M2L is then mirrored to the output port via the mirror
formed by M4L and M4R. The mirror gain factor, K,
indicates the current gain in the mirrors formed by M1L, M2L
and M 1R, M 2R with the following relations:
K = I 2 I1 = β 2 β1 = (W2 L2 ) (W1 L1 )
(1)
where subscripts 1 and 2 indicate that the parameters are
corresponding to M1L or M1R and M 2L or M 2R, respectively.
And β=μCoxW/L, where μ is the electron mobility and Cox is
the unit-area capacitance of gate oxide, and W/L is the
aspect ratio of the MOS transistor.
M 4L
flowing through each branch from the power supply to the
ground, which is given by
Pstatic = Vdd I bias (1 + K )
(5)
where Vdd is the power supply voltage.
It is obvious that increasing the mirror gain factor K
will enhance the SR and GBW at the cost of increasing the
static power dissipation. Hence, a trade-off between the
driving capability and static power dissipation in the
conventional OTA design is required.
3. Proposed SRE OTA
As shown in Fig. 2, the common current mirrors in the
conventional OTA are modified by adding two resistors and
a bias current sink to each one. This structure reinforces the
SR, which will be hereinafter referred to as the SR
enhanced structure or SRE mirror.
M 4R
M 4L
I bias
M 4R
I bias
M 3L M 3R
VN
VP
Vout
IM4L = IM2L
M 3L M 3R
VN
VP
Vout
M 2L
M 1L M 1R
R2 L
M 2R
I bias , L
The conventional OTA is differentiated from other
amplifiers by the fact that its only high impedance node is
located at the output terminal. The conventional OTA does
not employ an output buffer and is, therefore, only capable
of driving capacitive loads. The voltage gain of the OTA is
given by
AV = Kg m3 ( ro2 ro4 )
(2)
where gm3 is the transconductance of the differential pair;
ro2 and ro4 are the small signal output resistance of M2R and
M4R, respectively;
indicates that ro2 and ro4 are in
parallel. The GBW is given as
GBW = Kg m3 Cload = K β3 I bias Cload
(3)
where Cload is the load capacitance and Ibias is the bias
current of the differential pair. Then the SR can be
expressed as
SR = KI bias Cload .
(4)
It can be seen that for a certain bias current, the GBW
and SR increase linearly with the scaling factor K of the
current mirror.
The static power dissipation Pstatic is the sum of the
product of the power supply voltage with the currents
R1R
R2 R
M 1L M 1R
M 2L
Fig. 1. Conventional OTA.
R1L
M 2R
I bias , R
Fig. 2. Proposed SRE operational transconductance amplifier.
In a common current mirror, the output current depends
linearly on the input current simply because the
non-linearity of the amplifying MOS transistor M2L is
compensated by the non-linearity of the diode-connected
MOS transistor M1L. In order to take advantages of the
non-linearity of the amplifying MOS transistor M2L to
generate more output current, the non-linearity of the
diode-connected MOS transistor must be broken.
Take the SRE enhanced mirror 1 for example. The
resistor R1L in series with the diode-connected MOS
transistor M1L is applied to sense input current and convert
it into a voltage including a term linearly depending on the
input current. And the output current will include a term
containing the square of input current because of the square
law characteristic of the amplifying MOS transistor M2L.
The current sink Ibias,L provides a constant bias current
to R2L and produces a voltage drop across it. Eventually, the
static voltage drop across R1L can be canceled out by the
voltage drop across R2L with an appropriate bias current,
whereas the dynamic performance will not be affected.
Then, we will analyze the characteristic of the SRE
OTA quantitatively. The gate voltage of M2L is the sum of
the voltage across R1L and the drain-to-source voltage of
JOURNAL OF ELECTRONIC SCIENCE AND TECHNOLOGY, VOL. 13, NO. 1, MARCH 2015
16
M1L minus the voltage across R2L, and can be given as
Vgs,M2L = 2 I M1L β M1L + Vth, N + I M1L R1L − I bias,L R2L
(6)
where IM1L is the current generated from the differential
pair minus the bias current Ibias,L. And then, the
single-transistor amplifier M2L converts the gate voltage
into a current which is in a square law relationship with the
voltage and is given as
I M2L = β M2L [ 2 I M1L β M1L + I M1L R1L − I bias,L R2L ]2 2
and exceeds the output current of the common mirror when
the input current is over a certain value. And the quiescent
operating point has not been affected. Moreover, increasing
βM1L and βM2L simultaneously, the output current also
increases more quickly with the input current, of which the
effect is similar to increasing R1L. Decreasing the value of
m/n, the quiescent operating point will be moved upwards,
and the output current of SRE mirror exceeds that of the
common mirror more easily with the increasing of input
current, vice versa.
= K ( I M3L − I bias,L ) +
SRE mirror R1L=R2L=50kΩ
2β M2L K ( I M3L − I bias,L )[ I M3L R1L − I bias,L ( R1L + R2L )] +
β M2L [ I M3L R1L − I bias,L ( R1L + R2L )] 2 .
2
R2 L
M 2L
SRE mirror R1L=R2L=25kΩ
SRE mirror R1L=R2L=0kΩ
Common mirror
(7)
R1L
M 1L
I bias
I bias , L
Fig. 4. Normalized current transmission characteristic of the SRE
mirror with different sensing resistances vs. the common mirror
(m/n=1/4, βM1L=βM2L).
Fig. 3. Bias circuit schematic for SRE mirror.
As shown in Fig. 3, the bias current of R2L, which is
Ibias,L, is realized by mirroring the tail current. It can be seen
that Ibias,L=(m/n)Ibias, where m/n<1/2.
As mentioned before, the bias current of R2L is properly
chosen to set the voltage drop across R2L to be the same as
that across R1L at the static stage. So, R2L=(n/m−2)R1L/2.
Substitute it into (7), the result is
I M2L = K [ I M3L − I bias (m n)] +
2β M2L K [ I M3L − I bias (m n)]( I M3L − I bias 2) R1L +
β M2L [( I M3L − I bias 2) R1L ]2 2 .
(8)
As a result, the relationship between the quiescent
M2L
and
M1L
is
IM2L,static=
current
of
K[IM3L−Ibias(m/n)]=KIM1L, just like the common current
mirror. But the value of the quiescent output current is
[(n−2m)/2n]Ibias, which is less than the common mirror. And
by adjusting the value of m/n, the quiescent operating point
can be adjusted. Assuming R1L=R2L, m/n=1/4, and
βM1L=βM2L, Fig. 4 shows the normalized current
transmission characteristic of the SRE mirror with different
sensing resistances versus the common mirror. It can be
seen the quiescent output current of SRE mirror is half of
that of the common mirror. And when R1L=R2L=0, the SRE
mirror is similar to the common mirror, so the curve of IM2L
versus IM3L is linear. When R1L=R2L≠0, the output current
increases non-linearly with the input current just as
predicted qualitatively before. And the larger R1L is, the
more significant (IM3L−Ibias/2)2 term in (8) is. Therefore, the
output current increases more quickly with the input current,
As the positive input voltage Vp is much larger than the
negative input voltage Vn, the tail current of the differential
pair flows entirely through the transistor M3L. Then (8) can
be rewritten as
I M2L,max = ( ( n − m ) n ) KI bias + β M2L R1L 2 I bias 2 8 +
(n − m)
12
32
2n β M2L
R1L K 1 2 I bias
(9)
which is the maximum output current of SRE mirror and
also the maximum charging current of the SRE OTA. So
the SR can be given as
2
SR = ⎣⎡( ( n − m ) n ) KI bias + β M2L R1L2 I bias
8+
(n − m)
12
32 ⎤
2n β M2L
R1L K 1 2 I bias
C
⎦ load .
(10)
Obviously, the SR of the SER OTA can be much larger
than the conventional one with the same bias current, as
long as the values of R1L and βM2L are large enough and m/n
is small (the quiescent operating point moves upwards).
Additionally, when the bias current is improved, the SR
2
term while the
increases more quickly because of the I bias
conventional one increases linearly with Ibias.
Then, the static power dissipation of SRE OTA can be
expressed as
Pstatic = Vdd I bias ⎣⎡1 + K + 2 (1 − mK ) n ⎦⎤ .
(11)
As can be seen, when m=1/K, the static power dissipation is
the same as the conventional one’s for any value of n.
17
WAN et al.: Efficient Slew-Rate Enhanced Operational Transconductance Amplifier
AV = ( K + R1L g m2L ) g m3L ( ro2R ro4R ) .
(12)
The dominated pole is at the output terminal and given
as Pd=1/[(ro2R||ro4R)CL], where ro2R and ro4R are the small
signal output resistance of M2R and M4R, respectively.
Eventually, GBW is given by
GBW = ( K + R1L g m2L ) g m3L Cload .
(13)
It is obvious that voltage gain and GBW are boosted as
well in the SR enhanced structure.
But the added resistors, R1L and R2L, make the internal
pole move towards the low-frequency. This degrades the
AC small-signal performance. Fig. 5 depicts the AC
small-signal model of the part from the drain of M3L to the
gate of M2L in Fig. 2. The translation function can be given
as
Vgs,M2L (1 + g m1L )(1 + sC1 g m1L )
=
I M3L
g m1L + As + Bs 2
≈
(1 + g m1L )
g m1L ⎡⎣1 + ( R1L + R2L ) C2 s ⎤⎦
(14)
the value of R1L+R2L is very large, this pole will make the
GBW and phase margin (PM) deteriorate. To avoid the
deterioration, a compensation resistor is used in series with
the load capacitor Cload to generate a zero 1/RCCload to
cancel the pole out. The resistance of Rc can be given as
RC = ( R1L + R2L ) C2 Cload .
4. Simulation Results
A proposed SRE OTA and a conventional OTA are
designed with a power supply voltage of 5 V in a 0.5 μm
CMOS process to compare their performance. Fig. 6 shows
the curves of the unit gain frequency (UGF) and SR versus
the resistance of R1L (R1L=R2L=R1R=R2R), and Fig. 7 shows
the parameters versus the bias current.
From Fig. 6, it can be seen that the SR of SRE OTA
increases with the increase of the resistance as analyzed
before. The UGF also increases with the increase of the
resistance at first, but tends to be saturated and even
decreases when the resistance continues increasing. This
can be explained as follows. When the resistance increases,
the GBW increases whereas the non-dominant pole, which
is the internal pole, moves towards the low-frequency. At
first because the resistance is not so large, the internal pole
is still at the high-frequency far beyond GBW, which does
not affect the UGF. Therefore, the UGF increases with
GBW. But when the resistance continues increasing, the
internal pole moves towards GBW and even becomes lower
than it. So, the effect of the internal pole becomes more
significant and makes the UGF be saturated and even
decreases.
10.0
A = C1 + C2 + g m1L ( R1L + R2L ) C2
I M 3L
R2L
Vgs,M2L
C2
C1
UGF (MHz)
UGF
(MHz)
C2 = Cgs,M2L .
7.5
1.4
1.2
5.0
1.0
2.5
0.8
0.0
0.6
R1L
1
gM1L
Fig. 5. Small signal analysis of the internal poles and zeros.
It can be seen that this new structure produces two
poles and one zero. When the sum of R1L and R2L are much
larger than 1/gm1L, the pole 1/[(R1L+R2L)C2] becomes the
most significant one. The high-frequency pole and the zero
are very close, which cancels each other’s effect out. So,
the structure actually produces one pole 1/(R1L+R2L)C2. If
Slew rate (V/μs)
C1 = Cgs,M1L + Cdb,M1L
Conventional OTA UGF
Proposed SRE OTA UGF
Conventional OTA SR
Proposed SRE OTA SR
1.6
where
B = ( R1L + R2L ) C1C2
(15)
Slew rate (V/µs)
When m>1/K, the static power dissipation is less than
the conventional one’s. By increasing m and decreasing n,
where n should be larger than 2m, Pstatic decreases. When m
approaches to infinity and n to 2m, Pstatic will become the
minimum value VddIbias(1+K/2).
When m<1/K, the static power dissipation is larger than
conventional one’s. Increasing n could decrease the
dissipation as much as possible, and the limitation is
VddIbias(1+K).
The SR enhanced structure also changes the small
signal voltage gain and GBW. The voltage gain is easy to
be deduced from small signal analysis and given by
-40
0
40
80
120
160
200
240
Resistance
=R
Resistance of
of RR1L1L
=R
(kΩ)
2L=R
1R
2R (kO)
2L=R
1R=R
2R=R
Fig. 6 UGF and SR vs. different resistances R1L=R2L=R1R=R2R
(Ibias=5.32 μA, RC=0, Cload=10 pF, m=1, n=4).
From Fig. 7, we can see that the SR of the SRE OTA
increases much more quickly with the increase of the bias
current than the conventional OTA, because it increases
non-linearly with the bias current as analyzed in (10),
whereas the SR of conventional OTA increases linearly
with the bias current. The UGF of SRE OTA also increases
more quickly than the conventional one. The reason is that
JOURNAL OF ELECTRONIC SCIENCE AND TECHNOLOGY, VOL. 13, NO. 1, MARCH 2015
18
the transconductance gm of the MOS transistor increases
with the bias current as is well-known, and gm2L and gm3L
both contribute to the increasing of the GBW of the SRE
OTA whereas only gm3L contributes to the increasing of the
conventional one according to (3) and (13).
Table 1: Simulation results comparison
(Ibias=5.32 μA, R1L=R2L=R1R=R2R=150 kΩ, Rc=7 kΩ, CL=10 pF,
m=1, and n=4)
Parameter indicators
DC Gain (dB)
UGF (kHz)
Maximum
charging/discharging
current (μA)
Average SR (V/μs)
25
14
20
12
Slew rate (V/μs)
10
15
8
10
6
5
4
0
2
0
4
8
12
16
20
24
Fig. 7. GBW and SR with different bias currents
(R1L=R2L=R1R=R2R=150 kΩ, RC=7 kΩ, Cload=10 pF, m=1, and n=4).
Voltage gain (dB)
The AC small-signal characteristic is shown in Fig. 8. It
can be seen that the low-frequency gain and UGF of the
SRE OTA are both higher than those of the conventional
one, agreeing with the small signal analysis in Section 3.
The output settling time simulation results are shown in
Fig. 9. The output of the SRE OTA settles much faster than
the conventional OTA.
80
60
40
20
0
-20
-40
-60
-80
Conventional OTA
47.8
741
45.4/−41.5
5.5/−5.2
4.35
0.54
Settling time (μs)
0.9
7.4
Static power dissipation
(μW)
48
55
FOM1 (MHz·pF/mA)
3252
1392
FOM2
8.53
1.03
FOM3
4.74
0.50
Simulation results are summarized in Table 1. The
figures of merit (FOMs) shown in Table 1 are important
quality factors reflecting the driving capability and power
dissipation of an amplifier. And FOM1[1], FOM2[10], and
FOM3[10] are defined as follows:
FOM1 = GBWCL I bias
(16)
FOM 2 = I Lmax I bias
(17)
FOM 2 = I Lmax I supply
(18)
where ILmax is the maximum output current provided to the
load and Isupply is the total quiescent current of the supply
voltage. In this work, these factors have been greatly
improved. FOM1, FOM2, and FOM3 have been improved
134%, 728%, and 848% respectively.
Conventional OTA
SRE OTA
5. Conclusions
0
Phase (deg)
Proposed SRE
OTA
66.9
1730
-50
-100
Conventional OTA
SRE OTA
-150
-200
100
101
102
103
104
105
106
107
Frequency (Hz)
Fig. 8. Frequency response of the SRE OTA and conventional
OTA (Ibias=5.32 μA, R1L=R2L=R1R=R2R=150 kΩ, RC=7 kΩ, Cload=10
pF, m=1, and n=4).
5
5
4
4
3
3
2
2
1
1
0
0
10
15
20
25
30
35
40
45
In this study, a sensing resistor in series with the diode
configured MOS transistor of the current mirror is applied
to increase the SR. Therefore, the voltage drop across the
resistor produces a term containing the square of the input
current in the output current of the SRE current mirror. As a
result, the op amp has a greater SR which has been
improved by 8.25 times. And at the same time, the UGF is
improved by 2.33 times, whereas, the static power
dissipation is reduced 12.7%. Compared with some
common methods of SR enhancing, this method does not
lead to more power dissipation and even reduces it, which
is a great merit. Especially for today, the use of portable
equipment, wireless, and other battery powered systems are
prevalent, improving the driving capacity with no more
power dissipation has great significance. But, the SR of this
method is still not high enough, and it is necessary to
improve it more for further study.
50
Fig. 9. Output settling time simulation of the SRE OTA and
conventional OTA (Ibias=5.32 μA, R1L=R2L=R1R=R2R=150 kΩ,
RC=7 kΩ, Cload=10 pF, m=1, and n=4).
References
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WAN et al.: Efficient Slew-Rate Enhanced Operational Transconductance Amplifier
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Xiao-Peng Wan was born in Shanxi, China
in 1984. He received the B.S. degree from
the Northwest University, Xi’an in 2007 in
electronic science and technology. He is
currently pursuing the M.S. degree with the
School of Microelectronics and Solid-State
Electronics, University of Electronic
Science and Technology of China (UESTC),
19
Chengdu. His research interests include high speed photocoupler
designing and power system managing.
Fei-Xiang Zhang was born in Anhui, China
in 1988. He received the B.S. degree from
the Anhui University, Hefei in 2012 in
microelectronics. He is currently pursuing
the M.S. degree with the School of
Microelectronics and Solid-state Electronics,
UESTC. His research interests include high
speed photocoupler designing and power
system managing.
Shao-Wei Zhen was born in Hebei, China,
in 1982. He received the B.S., M.S., and
Ph.D. degrees from the UESTC in 2005,
2008, and 2013, respectively. He is now a
lecturer with UESTC. His research interests
are analog and mixed signal integrate circuit
design technology, including power manager
integrate circuit, single chip digital power
supply circuit, high speed optical receiver chip.
Ping Luo was born in Sichuan, China in
1968. She received the B.S. and M.S.
degrees from the Chongqing University,
Chongqing in 1990 and 1993, respectively.
She received the Ph.D. degree in electrical
circuit and system from UESTC in 2004.
She is now a professor with UESTC. As a
scholar, she visited the Georgia Institute of
Technology from 2002 to 2003. Her research interests include
power management circuit for SoC/CPU and LED driver.
Ya-Juan He received her B.S. degree from
East China Normal University, Shanghai,
China in 2001, and the Ph.D. degree from
Nanyang
Technological
University,
Singapore in 2008. Since 2009, she has been
working
with
the
School
of
Microelectronics and Solid-State Electronics,
UESTC, where she is now an associate
professor. Her current research interests include digital integrated
circuits, low-power techniques, and power management IC design.