PFD1K Preliminary Datasheet
6 GHz Phase Frequency Detector IC
with Dual 40Ghz Prescalers
Product Highlights
Model Number: PFD1K
40 pin Quad Flat Leadless (QFN)
6x6 mm pkg, 0.5 mm pad pitch
JEDEC MO-220 Compliant
Hermetic Option Available
Marking Information:
PFD1K = Device Part Number
XXXX = Lot Code
• 40 GHz Maximum Frequency
• 1-127 Variable Modulus Prescalars
• DC-6GHz Phase Detector
Operation
• Single +3.3V Supply
• Single-Ended or Differential inputs
and outputs
• Charge Pump digital control
• Charge Pump invert pin
• 6x6 Ceramic Leadless QFN
• Low Power Dissipation
Description
The PFD1K is a high frequency phase frequency detector with fully differential inputs and outputs on both RF and
charge pump outputs. It features dual 7 bit programmable high speed pre-scalars which allow the PFD1K to
operate up to 40GHz for the reference and oscillator input frequency. The 6Ghz phase detector operation allow
operation at higher reference frequencies with concurrent lower phase noise and figure or merit. The PFD1K
operates with a single positive or negative 3.3V supply, and is packaged in a 32-pin, 5mm x 5mm ceramic lead-less
surface mount package.
Pad Metallization
The QFN package pad metallization consists of a 500-1000 micro-inch Sn63 automated solder dip process.
Applications
The PFD1K can be used as a general purpose phase frequency detector with integrated prescalars which make it
perfect for phase locked loop applications. The pre-scalars can be programmed at a rate greater 100MHz which
make it an excellent choice for fractional-N digital frequency synthesizers.
Key Characteristics @ 25°C
Vcc=+3.3V, Icc=400mA, Zo=75Ω
Centellax • www.centellax.com • Email: sales@centellax.com • Tel: 866.522.6888 • Fax: 707.568.7647
Specifications subject to change without notice. © 2013 Centellax, Inc. 8 Aug 2013. SmD-00191 Rev A.
Page 1
PFD1K Preliminary Datasheet
Figure 1: Down Charge Pump Output with 2.5G PFD input
Figure 2: Up Charge Pump Output with 2.5G PFD input
Centellax • www.centellax.com • Email: sales@centellax.com • Tel: 866.522.6888 • Fax: 707.568.7647
Specifications subject to change without notice. © 2013 Centellax, Inc. 8 Aug 2013. SmD-00191 Rev A.
Page 2
PFD1K Preliminary Datasheet
Functional Block Diagram
VCC
DN_p
DVO
VCO_p
Div V
D
Q
CLR
Q
Charge
Pump
A[3:0]
DN_n
VCO/V
VCO_n
V[6:0]
UP_p
D
CLR
REF_p
DRO
REF_n
Div R
Charge
Pump
Q
A[3:0]
Q
UP_n
REF/R
R[6:0]
Figure 3: Functional Block Diagram
DC & RF Pin Description
Port Name
Description
Notes
REF_P
Reference RF input, positive terminal
CML signal levels (1)
REF_N
Reference RF input, negative terminal
CML signal levels (1)
VCO_P
VCO RF input, positive terminal
CML signal levels (1)
VCO_N
VCO RF input, negative terminal
CML signal levels (1)
UP_P
Up Charge Pump output, positive terminal
CML output level set by charge pump gain
UP_N
Up Charge Pump output, negative terminal
CML output level set by charge pump gain
DN_P
Down Charge Pump output, positive terminal
CML output level set by charge pump gain
DN_N
Down Charge Pump output, negative terminal
CML output level set by charge pump gain
DRO
Divided Reference Output ( single ended )
CML output level, requires DC pullup (3)
DVO
Divided VCO Output ( single ended )
CML output level, requires DC pullup (3)
Centellax • www.centellax.com • Email: sales@centellax.com • Tel: 866.522.6888 • Fax: 707.568.7647
Specifications subject to change without notice. © 2013 Centellax, Inc. 8 Aug 2013. SmD-00191 Rev A.
Page 3
PFD1K Preliminary Datasheet
Figure 6: Simplified Charge Pump Output Circuit
Pin and Package Diagrams:
Pin 1
Pin 1
z
Figure 6: Pin and Package Diagrams
Note: Package paddle is floating. Tie to
heat sink (typically ground).
Centellax • www.centellax.com • Email: sales@centellax.com • Tel: 866.522.6888 • Fax: 707.568.7647
Specifications subject to change without notice. © 2013 Centellax, Inc. 8 Aug 2013. SmD-00191 Rev A.
Page 5
PFD1K Preliminary Datasheet
Theory of Operation
Overview
The functional block diagram for the PFD1K consists two parallel programmable pre-scalars which divide the
reference and VCO inputs to the phase frequency detector. The phase frequency detector is the traditional Dflip-flop design with an AND gate clearing the flip-flops. The core phase frequency detector can be operated up
to a 6GHz reference frequency. The output of the phase frequency detector drives a programmable charge
pump. The charge pump has a digital control and an analog adjustment to control the amplitude of the UP and
DOWN pulses. Most of the inputs and outputs of the PFD1K are fully differential CML compatible levels so that
they are easy to interface with other logic.
Charge Pump Control
The PFD1K charge pump outputs are differential CML outputs with a 75ohm termination. With this design the
charge pump pulse width can be as szmall as 100ps. The charge pump output pulses are digitally
programmable with a 4 bit parallel interface . The maximum current output of the charge pump is 12mA which
will produce a pulse of 1200mVpp into the internal 100ohm termination resistor. When the charge pump outputs
are terminated with a 50ohm load the parallel impedance of 100ohms and 50hms results in a 33ohm load which
reduces the output to 400mVpp. In addition to the digital control there is an analog charge pump control voltage
VADJ which can be used for fine control of the charge pump current. The maximum charge pump output of
12mA occurs when VADJ is set to VCC ( which is the normal mode of operation ).
ESD Sensitivity
Although SiGe IC’s have robust ESD sensitivities, preventive ESD measures should be taken while storing,
handling, and assembling. Inputs are more ESD susceptible as they could expose the base of a BJT or the
gate of a MOSFET. For this reason, all the low frequency inputs are protected with ESD diodes. These inputs
have been tested to withstand voltage spikes up to 400 V. For performance reasons the RF inputs are not
protected with ESD diodes and the ESD sensitivity is higher.
The information contained herein is believed to be accurate and is provided “AS IS, WHERE IS”, with all faults and the entire risk associated with its use being
entirely with the user. Centellax makes no representation with respect to the merchantability of the products or their suitability or fitness for any particular
purpose of use. The information contained herein or any use of such information does not grant, explicitly or implicitly, to any party any patent rights, licenses,
or any other intellectual property rights, whether with regard to such information itself or anything described by such information. The information contained
herein is confidential and proprietary to Centellax. Centellax reserves the right to only disclose such information under the terms and conditions of a NonDisclosure Agreement between Centellax and the user and it is then to be treated accordingly.
Centellax • www.centellax.com • Email: sales@centellax.com • Tel: 866.522.6888 • Fax: 707.568.7647
Specifications subject to change without notice. © 2013 Centellax, Inc. 8 Aug 2013. SmD-00191 Rev A.
Page 6