2013 8th International Conference on Communications and Networking in China (CHINACOM)
Chip Design of 10 GHz Low Phase Noise and Small
Chip Area PLL
J. F. Huang1, W. C. Lai1, J. Y. Wen2, and C. C. Mao1
National Taiwan University of Science and Technology, Taipei 10672 Taiwan
2
National Communications Commission, Taipei, 10672 Taiwan
1
Abstract-This design describes one of the lowest phase noise an
integer-N phase-locked loop (PLL) below 10 GHz offset region
using and fabricated in TSMC 0.18-um CMOS technology. The
proposed PLL with a complementary crossed-couple LC-tank
voltage- controlled oscillator (VCO) and true single phase
clock (TSPC) logic in the frequency divider achieves a tuning
range of 1460 MHz from 9.6 to 11.06 GHz with a mixed
provide of current mode logic (CML) and according an offset
frequency of 1 MHz to obtain lower phase noise performance
of -113.47 dBc/Hz from the carry frequency of 10.087 GHz.
The locking time is smaller than 3.0 us as simulation. Sum of
pads (bonding) and an on-chip third-order low-pass filter, thus
makes the chip area occupies only 0.818×0.678 mm2 (0.555
mm2). The power consumption is 39 mW at a supply voltage of
1.8V.
power consumption, phase noise and chip area, a high
performance of PLL under 1.8 V supply voltage is proposed
and fabricated with 0.18 μm CMOS process. The
contributions of our proposed PLL are in three aspects. First,
complementary crossed-couple LC- tank VCO is used to
improve phase noise. Second, since the frequency divider
dominates the overall power consumption [3], a
combination of CML and TSPC in the frequency divider is
adopted to relieve this effect. Deliberate and compact layout
to reduce the chip area is the third contribution. Measured
results achieve a tuning range of 9.6 GHz to 11.06 GHz, a
locked phase noise of -113.47 dBc/Hz at 1 MHz offset
frequency from 10.087 GHz, a power consumption of 39
mW at a supply voltage of 1.8 V and a chip area of 0.555
mm2.
Keywords-PLL, phase-locked loop, phase noise, integer-N, multimodulus frequency divider, MMFD.
I.
INTRODUCTION
II.
In a CMOS RF transceiver front-end, PLL is a critical
component especially for high speed receiving circuits.
Numerous designs of 10 GHz PLLs are found in standard
CMOS process and performed much growth in recent years
[1]-[4]. In [1], the authors concentrate on jitter performance
by using a low-jitter clock multiplier to generate a 10 GHz
output, but it results in high power consumption of 100 mW.
A calibration technique added to reach efficient search for
an optimum VCO discrete tuning curve was proposed in [2],
but at the expense of a degraded phase noise of -102 dBc/Hz
at 1 MHz offset and a bigger chip area of 1.34 mm2.
Recently a mixed design of CML and TSPC logic to reduce
the power consumption is published and attractive, but it
suffers from a bigger chip area of 0.94 mm2 and more
expensive 0.13 um MOS process [3]. In [4] the authors
achieve a smaller chip area of 0.43 mm2, but it needs high
power consumption up to 77 mW and results in a degraded
phase noise of -99 dBc/Hz at 1-MHz offset. A new method
of an injection-locked frequency divider for 5 GHz WLAN
applications to reduce power consumption is illustrated in
[5], but its VCO operates only at 5 GHz band with a
degraded phase noise of -104 dBc/Hz at 1 MHz offset and a
narrow output tuning range of 740 MHz. Hence, after
considering those factors of supply voltage, tuning range,
ARCHITECTURE AND PHASE-LOCKED LOOP
The architecture of PLL mainly consists of a phase/
frequency detector (PFD), a charge pump (CP), a third-order
loop filter and a VCO in the feed-forward path and a
frequency divider in the feedback path, as shown in Fig. 1.
The PFD detects the phase error between the reference
signal FREF and the feedback signal FDIV. The digital output
signals of PFD control the VCO circuit through the CP
circuit and the loop filter. The VCO is proportional to the
filter output level and then connected to both frequency
divider and output terminal.
Fig. 1 Architecture of the proposed PLL.
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978-1-4799-1406-7 © 2013 IEEE
III.
A.
CIRCUIT IMPLEMETATION
MN10 will be off, MP8 is always on, and the gates of MN8 and
MN9 will be pulled high. The start-up circuit will inject
currents into the bias loop, which will start-up the circuit.
Once the loop starts up, MN10 becomes on sinking all of the
currents from MP8. The gates of MN8 and MN9 will be pulled
low, and thereby turned them off so they no longer affect on
the bias loop.
Phase/Frequency Detector (PFD)
Important techniques to design a PFD working at high
frequency with minimum dead-zone are to reach minimum
phase offset and to reduce blind-zone in the circuit. For
these considerations, a new domino-logic PFD in Fig. 2 is
presented [6]. The operating speed is dominated by the gate
delays. Delay cell has added on the reset path to improve the
dead zone.
C.
The low-pass filter is necessary to eliminate noise from the
tuning voltage. The VCO output signal is altered in respect
to the control data inputted into the filter. The filter design
must follow some parameter specs in the PLL, including
reference frequency (FREF), divide ratio (N), loop
bandwidth, charge pump current (ICP), slope of VCO (KVCO)
and phase margin. The filter suppresses spurs introduced by
the reference frequency. Figure 4 shows the schematic of the
third-order low-pass filter which provides more attenuation
of spurs by placing a series resistor R2 and a shunt capacitor
C3. The filter transimpedance, VCTRL (s)/I cp (s) can be
expressed as
Fig. 2 The proposed dynamic PFD circuit with minimum dead-zone.
B.
The 3rd order Low-Pass Filter
Z (s) =
Chare Pump (CP)
sR1C1 + 1
. (1)
s 3 R1 R3 C1C 2 C 3 + s 2 ( R1C1C 2 + R1C1C 3 + R3 C 2 C 3 + R3 C1C 3 ) + s ( C1 + C 2 + C 3 )
Resistor R1 and capacitor C1 in the filter generate a pole at
the origin and a zero at 1/(R1C1). Capacitor C2 and the
combination of R2 and C3 are used to generate extra poles at
frequencies higher than frequency synthesizer bandwidth of
interest to reduce the feedthrough at reference frequency and
decrease spurious sidebands at harmonics of the reference
frequency. All component parameters used in this thirdorder low-pass loop filter with considerations of reference
frequency of 40 MHz, CP current of 275 uA, VCO tuning
range gain of 1430 MHz/V, frequency divider ratio of 240,
loop filter bandwidth of 750 kHz and phase margin of 62o,
are summarized as follows; R1=2.56 kΩ, R2=5.12 k Ω ,
C1=22.14 pF, C2=332.04 pF, and C3=1.87 pF.
With reference to Fig. 3, the charge pump consists of a
current steering charge pump circuit, a bias circuit and a
start-up circuit [6]. The differential UP and DN signals from
the PFD steer the current one way or the other in the
differential pair in the charge pump. The transistors MN4 and
MP4 are used to assure that in case of switching transistors
MP3 and MN3, their sources are already pre-charged,
reducing current peaks during the switching time.
Fig. 4 The third-order low-pass filter circuit.
Fig. 3 The schematic of CP with start-up and bias circuits.
D.
The bias transistors MP1 and MN1 are designed to ensure
CP current working smoothly and Rb in the circuit is an offchip resistor. The start-up circuit contains transistors MP8,
MN8, MN9 and MN10. If all currents in the bias loop are zero,
Voltage-Controlled Voltage (VCO)
The cross-coupled VCO in CMOS has attracted
considerable interest due to its easy start-up and good phase
noise characteristics. The complementary LC-tank VCO is
chosen to lower phase noise performance. With reference to
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E. Current-Mode Logic (CML) Divider
Fig. 5 which shows the complementary LC-tank VCO
circuit, which consists of a PMOS cross-coupled pair, a
NMOS cross-coupled pair, a symmetric spiral inductor and
two varactors [7]. The differential VCO is formed by two
complementary NMOS (M3, M4) and PMOS (M1, M2) to
generate the negative transconductance. The negative
resistance -2/gmp,n where gmp,n denotes the transconductance
of each P-channel or N-channel transistor generated by the
cross-coupled PMOS transistors M1 and M2 or PMOS
transistors M3 and M4 is designed to compensate for the loss
associated with the LC-tank. In order for the oscillation to
be sustained, the tail current of the cross-coupled transistor
pair should be increased to a level high enough for the
negative resistance to be smaller in absolute value than the
equivalent loss of the tank. A tail-current NMOS transistor
M5 adjusts the current of VCO.
The CML divider also referred as SCL (source-coupled
logic) divider is shown in Figure 6 [7]. Each of the two Dlatches consists of a cross-coupled pair connected in a
positive feedback configuration to provide negative
transconductance to maximize the operation frequency. The
CML works under lower power supply and higher frequency
without tail current. Through properly adjusting the CML
transistors aspect ratio, the divider can operate even beyond
13 GHz with 0.18 um CMOS process.
Fig. 6 The proposed CML divider circuit.
F. True Single Phase Clock (TSPC) Divider
The proposed TSPC DFF (D Flip-Flop) circuit designed to
resolve the charge distribution and reduce the chink of
output waveform is shown in Fig. 7[6]. Comparing with the
traditional TSPC DFF circuit, this circuit only contains eight
transistors, excluding the output inverter.
Fig. 5 A complementary VCO circuit with push-pull inverting amplifiers.
The capacitor Cvar in parallel with the inductor forms the
LC-tank resonator. The accumulation-mode MOS varactors
are used for tuning the VCO output frequency. The
oscillation frequency is expressed as
fo =
1
2π L1Cvnet
,
(2)
where Cvnet is the effective capacitance of the balanced VCO
across the inductor shown in Fig. 5. The designed circuit
using only two-pair crossed coupled MOS transistors in the
signal path to generate a differential negative resistance
makes the circuit very attractive for 10 GHz applications
where low noise with low power consumption at GHz range
become key performance indices.
Push-pull common source amplifiers are inserted to
enhance the VCO output signals. The voltage gain of this
output stage can be approximately expressed as
g mp,n (rop // ron ) where g mp ,n means PMOS or NMOS
transistor transconductance and rop and ron are output
resistors for PMOS and NMOS transistors respectively.
Fig. 7 The proposed TSPC divider circuit with eight transistors.
G. Multi-Modulus Frequency Divider (MMFD)
Figure 8(a) shows the programmable MMFD circuit which
contains 2/3 TSPC divider and traditional logic gate circuits.
Figure 8(b) illustrates the 2/3 TSPC divider architecture
which contains two traditional DFFs [6]. The MMFD has
the ability to treat frequency division over large continuous
range and can be programmable.
DN = 16 + 23 i MC 4 + 22 i MC 3 + 21 i MC 2 + 20 i MC1 .
(3)
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(a)
(b)
Fig. 8 The proposed MMFD structure, (a) containing 2/3 TSPC divider and
logic gates, (b) 2/3 TSPC divider with DFFs.
Fig. 10 Die micrograph of the fabricated PLL with a chip area of 0.818 x
0.678 (0.555) mm2.
In this design, the 16-modulus divider is chosen to deal with
all of integer divide ratio values from 23 to 26 defined in (3).
When the frequency synthesizer oscillates is 10 GHz, the
divided number (DN) must be 25, then the controlled code,
MC1-MC4, is set to be (1, 0, 0, 1).
IV. Simulation and Measurement Results
The simulation result of free running locking time of the
proposed PLL is only about 2.4 us. Figure 9 shows the
frequency hopping simulation to verify the locking function.
This result indicates the PLL can lock first in 10 GHz, then
hops to 9.6 GHz, and finally hops to 10 GHz.
Fig. 11 Measured output spectrum of the proposed PLL with the supply
voltage VDD=1.8 V and VCO tuned voltage, Vtune=0.5 V.
Fig. 9 PLL locking time simulation.
Figure 10 shows the die micrograph of the fabricated
PLL chip. Including pads and an on-chip third-order lowpass filter, the chip area is 818.2 um × 678.3 um (0.555
mm2). A two-layer commercial FR4 glass-epoxy doublesided laminate ( ε r =4.4) is used for chip function testing.
Measurements have been performed with a HP 8593A
spectrum analyzer and an Agilent E5053A signal source
analyzer. At VCO tuned voltage equal to 0.5 V and supply
voltage VDD=1.8 V, the measured output power spectrum
is -5.59 dBm at 10.4214 GHz as shown in Fig. 11.
Fig. 12 Tuned range from 9.6 to 11.06 GHz with a tuned voltage of 0-1.7 V..
Figure 12 shows the tuned range of the VCO versus the
tuned voltage from 0 to 1.7 V. The VCO output frequency is
tunable from 9.6 GHz to 11.06 GHz, corresponding to
14.6% by varying the controlled voltage from 0 to 1.7 V.
Figure 13 shows the measured phase noises of phase-locked
VCO. According to our measurement results, the phase
noise of the locked phase noise is -113.47 dBc/Hz at 1 MHz
offset frequency from the frequency of 10.087 GHz.
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MMFD circuit is also used to change the frequency channel by
different input digital code. The locking time can be reduced
by carefully designing system parameters, such as charge
pump current, VCO gain and loop bandwidth. In this work, the
simulated locking time is lower than 3 us.
With a supply voltage of 1.8 V, measured results illustrate
that the proposed PLL covers the frequency range from 9.6
GHz to 11.06 GHz and the phase noise is lower than -113.47
dBc/Hz at 1 MHz offset frequency locked at 10.087 GHz. The
chip area is 0.555 mm2 including pads and an on-chip thirdorder low-pass filter. The power consumption is 39 mW from
a 1.8V supply voltage with an output power spectrum of -5.59
dBm at 10.4214 GHz.
ACKNOWLEDGEMENTS
Fig. 13 Measured phase noise of the locked PLL versus offset frequency at
f=10.087 GHz.
The authors would like to thank Prof. Ron-Yi Liu for his
layout guidance and thank the National Chip
Implementation Center (CIC) for the chip fabrication and
technical supports.
Table I summarizes the measured performance of the
proposed PLL in comparison with some other reported PLL
papers. Obviously, our design achieves the highest output
frequency. Except [3] which using advanced process of 0.13
um, the proposed PLL accomplishes the best phase noise of 113.47 dBc/Hz and smallest power consumption of 39 mW,
with a chip area of 0.555 mm2, much smaller than 0.94 mm2
found in [3]. Except [4], the proposed PLL achieves the
smallest chip area of 0.555 mm2.
REFERENCES
[1] C.-H Remco, C.-S. Vaucher, D. M.W. Leenaerts, E.-A.-M. Klumperink
and B. Nauta (2004), A 2.5-10-GHz clock multiplier unit with 0.22-ps
RMS jitter in standard 0.18-μm CMOS, IEEE Journal of Solid-State
Circuits 39 (11), 1862–1872.
[2] T.-H. Lin and Y.-J. Lai (2007), An agile VCO frequency calibration
technique for a 10-GHz CMOS PLL, IEEE J. Solid-State Circuits 42 (2),
340-349.
[3] I.-W. Tseng and J.-M. Wu (2009), An 18.7mW 10-GHz phase-locked
loop circuit in 0.13-µm CMOS, VLSI-DAT ’09, 227-230.
[4] N. Pavlovic, J. Gosselin, K. Mistry and D. Leenaerts (2004), A 10 GHz
frequency synthesizer for 802.11a in 0.18 μm CMOS, Solid-State
Circuits Conference 2004, 367-370.
[5] P.-Y Deng and J.-F Kiang (2009), A 5-GHz CMOS frequency
synthesizer with an injection-locked frequency divider and differential
Switched Capacitors, IEEE Transactions on Circuits and Systems 56 (2),
320-326.
[6] J.-F. Huang, C.-W. Shih and R.-Y. Liu (2011), A 5.8-GHz frequency
synthesizer chip design for worldwide interoperability for microwave
access application, Microwave and Optical Technology Letters 53 (12),
2931-2935.
[7] R.-L. Bunch, and S. Raman (2003), Large-signal analysis of MOS
varactors in CMOS-Gm LC VCOs, IEEE J. Solid-State Circuits 38 (8),
1325-1332.
TABLE I Performance Comparison of Proposed PLL with Previously
Reported Papers.
Design
This
Work
[1]
2004
[2]
2007
[3]
2009
[4]
2004
Process (um)
(TSMC CMOS)
0.18
0.18
0.18
0.13
0.18
Supply voltage (V)
1.8
1.8
1.8
1.2
1.8
10.08
9.953
10
9.613
10
40
2488
40
N/A
10
<3**
N/A
<3
N/A
4
N/A
300
200
330
N/A
8.67-10.1
7.5-9.6
-108
-102
-117.43
-99
39
100
44/70*
23.94
77
0.555
0.71
1.34
0.94
0.43
Center frequency
(GHz)
Reference
frequency (MHz)
Locked time (us)
VCO gain (MHz/V) 1430
Tuning range
9.6-11.06
(GHz)
Phase noise
-113.47
@ 1MHz (dBc/Hz)
Power (mW)
2
Chip area (mm )
10-11.8
* With calibration of the power is 70 mW/without calibration of the power is
44 mW.
** Post-simulation value.
V. Conclusions
The proposed 10 GHz PLL chip is presented and fabricated in
TSMC 0.18-um CMOS technology. The complementary LCtank VCO is chosen to lower phase noise performance. The
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