A D S A N T E C
A d v a n c e d
S c ie n c e
a n d
N o v e l
T e c h n o lo g y
27 Via Porto Grande, Rancho Palos Verdes, CA, 90275.
Ph. # 1-310-377-6029.
Fax # 1-310-377-9940.
ASNT1012
Reconfigurable MUX CMU
•
•
•
•
•
•
•
•
•
•
•
Reconfigurable 16:1 Serializer with CMU (clock multiplication unit).
On-chip PLL with two selectable VCOs centered at 12.5GHz and 8GHz.
Possibility to switch the PLL off and use an external high-speed clock.
LVDS-compatible Input Data and Reference Clock Buffers.
CML Output Data Buffer for a 50Ohm external single-ended termination to VCC.
Selectable Clock Output Buffer with the CML interface.
Clock-divided-by-16 LVDS Output Buffer with 90°-step phase selection.
Single +3.3V power supply.
Industrial temperature range.
Low power consumption of 550mW at 12.5Gbps.
100-pin MLF package
Rev. 03;
December 2007.
1
ASNT1012
A D S A N T E C
A d v a n c e d
S c ie n c e
a n d
N o v e l
T e c h n o lo g y
27 Via Porto Grande, Rancho Palos Verdes, CA, 90275.
Ph. # 1-310-377-6029.
Fax # 1-310-377-9940.
DESCRIPTION
d00
d01
…
d15
LS DATA
IB
MUX
16:1
CML OB
qcml
offcho
C
phs1,2
DIVIDER-BY-16
C16
offpll
PLL
LS
cr16
CLOCK
IB
PFD
/CP
I
C16S
HS
CLOCK
OB
cho
LVDS
CLOCK
OB
clo
12.5
8.0
off12g
lol
ce
ASNT1012 is a high-speed reconfigurable 16:1 serializer featuring an internal CMU with
selectable operational frequencies of 8GHz or 12.5GHz. The primary application of ASNT1012
is to provide a high-speed output data channel for point-to-point data transmission over a
controlled impedance media of 50Ohm. The transmission media can be a printed circuit board or
copper coaxial cables. The functional distance of the data transfer is dependent upon the
attenuation characteristics of the transportation media and the degree of noise coupling to the
signaling environment.
During normal operation, the serializer’s low-speed input buffer (LS DATA IB) accepts external
16-bit wide parallel data words (“d00”-“d15”) through 16 differential inputs. The multiplexer
(MUX16:1) latches the data words with a low-speed clock generated by the internal CMU based
on a phase-locked loop (PLL) using an external low-speed clock (“cr16”) as a reference. The
parallel input words are then serialized and transmitted as a 2-level signal (“qcml”) by a
differential CML output buffer (CML OB). In this case, a full-rate (C) high-speed clock is
transmitted by the CML Clock Output Buffer as the “cho” signal in parallel with the high-speed
data.
The serializer uses a single +3.3V power supply and is characterized for operation from −25°C to
125°C of junction temperature.
Rev. 03;
December 2007.
2
ASNT1012
A D S A N T E C
A d v a n c e d
S c ie n c e
a n d
N o v e l
T e c h n o lo g y
27 Via Porto Grande, Rancho Palos Verdes, CA, 90275.
Ph. # 1-310-377-6029.
Fax # 1-310-377-9940.
LS DATA IB
The Low-Speed Data Input Buffer (LS DATA IB) consists of 16 proprietary Universal Input
Buffers. The proprietary Universal Input Buffer (UIB) is designed to accept differential signals
with amplitudes higher than 60mV, DC common mode voltage variation between the negative
and positive supply voltages, and AC common mode noise with a frequency up to 5MHz and
voltage levels ranging from 0 to 2.4V. It can also receive single-ended signals with amplitudes of
more than 60mV and threshold voltages between the negative and positive supply rails. The
buffer outputs standard internal CML signals with amplitude of 220mV.
LS CLOCK IB
The Low-Speed Clock Input Buffer (LS CLOCK IB) is a single UIB that can run at a frequency
up to 1.6GHz. This reference clock signal is utilized by PLL to synchronize the activated VCO.
PLL
PLL contains a phase frequency detector (PFD), charge pump (CP), an on-chip integrator (I) and
an additional off-chip filter connected through the pins “ftr1” and “ftr2”, and two selectable
VCOs centered at either 12.5GHz or 8.0GHz. The proposed external filter schematic is shown
below.
100
ftr1
20p
1n
ftr2
100
20p
Fig. 1. External filter schematic.
The main function of PLL is to align the phase and frequency of the divided down clock signal
of the activated VCO to the externally applied low-speed reference clock signal (“cr16”). A logic
“1” output CMOS loss-of-lock (“lol”) signal is generated by PLL if the two clock signals are not
matching in phase and/or frequency.
Activation of the different VCOs is achieved by utilizing the CMOS control pin “off12g”. A
logic “1” chooses the 8GHz VCO while a logic “0” selects the 12.5GHz VCO (default state). The
unused VCO is turned completely off in order to save power.
PLL can be switched off by a logic “1” level applied to the input “offpll”. In this case, an
external high-speed clock “ce” should be used to substitute the VCO output signal.
HS CLOCK IB
The High-Speed CML Clock Input Buffer (HS CLOCK IB) accepts external differential signals
“ce” with frequencies up to12.5GHz. It can also accept a single-ended signal with a threshold
voltage applied to the “cen” pin. The buffer utilizes on-chip single-ended termination of 50Ohm
to the positive supply rail for each input line.
Rev. 03;
December 2007.
3
ASNT1012
A D S A N T E C
A d v a n c e d
S c ie n c e
a n d
N o v e l
T e c h n o lo g y
27 Via Porto Grande, Rancho Palos Verdes, CA, 90275.
Ph. # 1-310-377-6029.
Fax # 1-310-377-9940.
DIVIDER-BY-16
DIVIDER-BY-16 includes 4 divide-by-2 circuits connected in series. The high-speed clock (C)
generated by the selected on-chip VCO is fed into the first divide-by-2 circuit that generates an
output clock signal (C2) that is half the rate of the input clock. C2 is routed internally to the next
divide-by-two circuit and outside of the block to MUX16:1. C4, C8, and C16 are formed and
routed to MUX16:1 in a similar way.
In addition, C16 is passed onto the LVDS Clock Output Buffer (LVDS CLOCK OB) as the
C16S signal. By utilizing the CMOS control pins “phs1” and “phs2”, the phase of C16S can be
altered in accordance with the table below.
“phs1”
“phs2”
C16S phase
VEE (default) VEE (default)
270°
VEE
VCC
180°
VCC
VEE
90°
VCC
VCC
0°
MUX16:1
MUX16:1 utilizes a standard tree type architecture and latches the incoming data on the negative
edge of the C16 clock signal that is supplied by DIVIDER-BY-16. The 16-bit wide data word is
subsequently multiplexed by the tree structure and the present divided down clock signals and is
delivered to the high-speed CML Output Buffer (CML OB) as a serial data stream running at a
data rate up to 12.5Gbps. The latency of this circuit block is equal to roughly one period of the
low-speed input clock.
HS DATA OB
HS DATA OB receives high-speed serial data from MUX16:1 and converts it into the CML
output signal “qcml” with a single ended swing not less than 600mV. The buffer requires 50Ohm
external termination resistors connected between “vcc” and each output, and can operate at a
data rate up to 12.5Gbps.
HS CLOCK OB
The selectable HS CLOCK OB can be enabled or disabled by the external CMOS control signal
“offcho”. The logic “0” default state corresponds to an operational buffer. The buffer utilizes the
same termination scheme as HS DATA OB and can operate at a frequency up to 12.5GHz while
producing a single-ended CML output swing of 500mV.
LS LVDS CLOCK OB
The LVDS Clock Output Buffer (LVDS CLOCK OB) receives the C16S signal from DIVIDERBY-16 and converts it into an LVDS output signal.
Rev. 03;
December 2007.
4
ASNT1012
A D S A N T E C
A d v a n c e d
S c ie n c e
a n d
N o v e l
T e c h n o lo g y
27 Via Porto Grande, Rancho Palos Verdes, CA, 90275.
Ph. # 1-310-377-6029.
Fax # 1-310-377-9940.
The proprietary low-power LVDS output buffer utilizes NPN HBTs that are common to standard
BiCMOS technologies. It utilizes a special architecture that ensures operation at frequencies up
to 2GHz with a low power consumption level of 30mW. The buffer satisfies all the requirements
of the IEEE Std. 1596.3-1996 and ANSI/TIA/EIA-644-1995.
Terminal Functions
TERMINAL
Name
No.
Type
chop
chon
qcmlp
qcmln
lol
ftr1
ftr2
off12g
offpll
offcho
phs1
phs2
vcc
vee
nc
Rev. 03;
DESCRIPTION
High-Speed I/Os
37 Output CML differential high-speed clock outputs. Require external
SE 50Ohm termination to “vcc”. Can be disabled by
36
“offcho”.
43 Output CML differential high-speed data outputs. Require external
SE 50Ohm termination to “vcc”.
42
Controls
21 LS Out, PLL lock indicator (high: no lock; low: locked).
CMOS
22 I/O External PLL filter connection.
23
24 LS In., VCO frequency selection (active: high, 8GHz; default: low,
CMOS 12GHz).
26 LS In., PLL switch-off (active: high, PLL disabled; default: low, PLL
CMOS is on).
28 LS In., High-speed clock output disable (active: high, default: low).
CMOS
57 LS In., Low-speed output clock phase selection (default: both low).
56 CMOS
Supply and Termination Voltages
many
PS
Positive power supply
many
PS
Negative power supply
many
Unconnected pin.
December 2007.
5
ASNT1012
A D S A N T E C
A d v a n c e d
S c ie n c e
a n d
N o v e l
T e c h n o lo g y
27 Via Porto Grande, Rancho Palos Verdes, CA, 90275.
Ph. # 1-310-377-6029.
Fax # 1-310-377-9940.
DESCRIPTION
TERMINAL
Name
No.
Type
Low-Speed I/Os
cep
cen
clop
clon
d00p
d00n
d01p
d01n
d02p
d02n
d03p
d03n
d04p
d04n
d05p
d05n
d06p
d06n
d07p
d07n
d08p
d08n
d09p
d09n
d10p
d10n
d11p
d11n
d12p
d12n
d13p
d13n
d14p
d14n
d15p
d15n
Rev. 03;
31 Input CML differential high-speed clock inputs with internal SE
50Ohm termination to “vcc”.
30
48 Output LVDS low-speed clock outputs. Can transmit four different
clock phases as defined by “phs1” and “phs2” signals.
47
61 Input
62
64
65
67
68
70
71
76
77
79
80
82
83
85
86
Universal low-speed data inputs with LVDS internal
88
termination.
89
90
91
93
94
96
97
99
100
5
6
8
9
11
12
December 2007.
6
ASNT1012
A D S A N T E C
A d v a n c e d
S c ie n c e
a n d
N o v e l
T e c h n o lo g y
27 Via Porto Grande, Rancho Palos Verdes, CA, 90275.
Ph. # 1-310-377-6029.
Fax # 1-310-377-9940.
ELECTRICAL CHARACTERISTICS
PARAMETER
MIN
TYP
MAX
UNIT
COMMENTS
V
V
V
mW
°C
±5%
General Parameters
VCC
VEE
VECL
Power consumption
Junction temperature
3.14
-25
3.3
0.0
VCC-2.0
550
50
3.47
125
LS Input Data (d00-d15)
Data Rate
Logic “1” level
500 or 780
VCC
Logic “0” level
Mbps
V
VCC-0.25
V
Same for all types
of valid input data
Same for all types
of valid input data
LS Input Reference Clock (cr16)
Frequency
Logic “1” level
Logic “0” level
Duty Cycle
500 or 780
VCC
VCC-0.25
40%
50%
60%
Mbps
V
V
HS Output Data (qcml)
Data Rate
Logic “1” level
Logic “0” level
Jitter
8.0
Data Rate
Logic “1” level
Logic “0” level
Logic “0-” level
8.0
Frequency
Logic “1” level
Logic “0” level
Jitter
Duty Cycle
4.0
12.5
VCC
VCC-0.6
15
Gbps
V
V
pS
p-p @ 12.4Gb/s
Gbps
V
V
V
Standard level
Lower level (SS)
GHz
V
V
ps
p-p
HS Output Data (qml)
12.5
VCC
VCC-0.4
VCC-0.7
HS Output Clock (cho)
12.5
VCC
45%
VCC-0.6
14
50%
55%
LS Output Clock (clo)
Frequency
Interface
Rev. 03;
December 2007.
500
1600
LVDS
7
MHz
Meets the IEEE Std.
1596.3-1996
ASNT1012
A D S A N T E C
A d v a n c e d
S c ie n c e
a n d
N o v e l
T e c h n o lo g y
27 Via Porto Grande, Rancho Palos Verdes, CA, 90275.
PARAMETER
MIN
Ph. # 1-310-377-6029.
TYP
MAX
UNIT
Fax # 1-310-377-9940.
COMMENTS
CMOS Control Inputs
Logic “1” level
Logic “0” level
VCC-0.4
VEE+0.4
V
V
CMOS Control Outputs
Logic “1” level
Logic “0” level
VCC-0.1
VEE+0.1
V
V
Timing Parameters
“cho” to “qcml” delay
variation
Rev. 03;
December 2007.
±2.5%
8
Over the full
temperature range
ASNT1012