A 10 bit 12.8 MS/s SAR Analog-to-Digital
Converter in a 250 nrn SiGe BiCMOS Technology
Johannes DigeJ, Markus Grozing, Manfred Berroth
Institute of Electrical and Optical Communications Engineering
University of Stuttgart, Germany
Abstract-This paper presents a 10 bit 12.8 MS/s succes­
sive approximation register (SAR) analog-to-digital converter
(ADC) implemented in a 250 nm SiGe BiCMOS technology. An
energy-efficient switching algorithm with top-plate sampling is
applied which reduces the total input capacitance by 50%. High­
Dout
impedance inputs with emitter followers and internal reference
voltage generation make it suitable for applications that require
precise on-chip voltage monitoring.
For a low-frequency input signal, measured SNDR and SFDR
of the presented SAR ADC are 48.7 dB and 57.8 dB. The
effective resolution bandwidth (ERBW) is 19 MHz. The ADC
draws 17.4 rnA from a 2.6 V supply including reference voltage
Fig. 1.
Block diagram of the ADC (analog signals drawn single-ended for
simplicity)
generation, clock drivers and emitter follower buffers for input
and reference voltages. The die area is 2.1 X 0.7
ADC core occupying 1 X 0.5
mm2•
mm2
with the
A formula for relating static nonlinearity (INL) measure­
ments with dynamic SNDRIENOB measurements is derived.
From output codes recorded with constant input voltages, the
distortion power caused by nonlinearity and the noise of the
reference voltage source and the comparator are determined.
After adapting them to sinusoidal inputs, the expected impact
on SNDR and ENOB is derived.
I.
INTRODUCTION
Medium-resolution medium-speed ADCs are suitable for a
variety of applications. In wireless communication systems
an ADC digitizes the received signal before it is passed
on to a digital signal processor. Especially narrowband sub1 GHz wireless communication systems can be implemented
with the presented kind of converter. Other applications are
sensor systems where analog sensor measurements are to be
converted into digital domain to be sent via a bus system.
Furthermore such ADCs can be integrated into more sophisti­
cated circuits in an assistive manner, e.g. for calibration. In a
high-speed, low-resolution time-interleaved ADC a medium­
resolution, medium-speed sub-ADC can be applied to calibrate
each single channel. Another application is to monitor analog
voltages inside an integrated circuit.
High input impedance and internal reference voltage gener­
ation qualify the ADC to be used as an independent assistive
block inside complex systems. Its fully differential design
enables the integration together with CMOS logic without
being prone to supply or substrate noise. The extra amount
of supply power can be tolerated because assistive circuits
are usually not required permanently and can be switched off
when not needed.
978-1-4799-4994-6/14/$31.00 ©2014 IEEE
Section II introduces the applied SC-switching algorithm
and explains circuit implementation details. Measurement re­
sults with constant and sinusoidal input signals are given in
Section III, Section IV relates these results by investigating
the impact of noise and nonlinearity on the dynamic effective
resolution. Section V concludes the paper.
II.
CIRCUIT DESIGN AND LAYOUT
The proposed ADC works with successive approximation
based on a charge redistribution principle similar to the split
capacitor algorithm [1]. The block diagram in Fig. 1 shows the
components required for the successive approximation. The
bit values that are sequentially derived by the comparator are
stored in the SAR. They are fed back to a digital-to-analog
converter (DAC) and the generated analog corresponding volt­
age is subtracted from the input signal. Track-and-Hold circuit,
subtractor and DAC are included in a switched-capacitor (SC)
DAC composed of binary weighted capacitors and MOSFET
switches. The signal input is matched to 50 S1 (not shown)
and drives an emitter follower. Three reference voltages VCM,
1I;.ef+ and 1I;.ef- are generated on-chip and fed to the SC DAC.
The entire circuit is designed in a differential manner to reduce
distortion due to substrate or supply noise.
The differential input pins are connected to emitter followers
to drive the capacitive input impedance of the SC DAC. The
reference voltages are generated by an operational ampli­
fier (op-amp) with common-mode control [2] and resistive
feedback. Two resistor voltage dividers generate the desired
common-mode voltage and another voltage controlling the
reference voltage difference. The output impedances of the
common-mode and reference voltage generators are decreased
using emitter followers as output buffers.
AA
ISF
�
ISF
�
R
c
C
DO,a
D1,b
Fig. 2.
DO,b
Fig. 4.
Three-stage comparator
Successive approximation register
v;.ef+
to other capa­
r t- citors and
"-!l<mp"
(a)
. .m
(b)
Fig. 3. Capacitor topology of an N-bit SC DAC for the MSB with (a) split
capacitors forming a capacitive voltage divider [l] and (b) the implemented
structure with the common-mode voltage VCM as additional reference voltage
A. Successive approximation register
The SAR in Fig. 2 controls the temporal sequence of the
successive approximation process and switches the SC DAC
according to the determined bit values. The upper line of
delay-flip-flops (DFFs) is connected as a shift register which
is reset after each conversion cycle by an internally generated
signal. Each conversion cycle has a length of twelve clock
periods. The data register, i.e. the lower line of DFFs, stores
the bit values received from the comparator via the input C.
The ADC operates synchronously with the clock signal elk
having a frequency of twelve times the sampling rate. The
outputs Di,a and Di,b control the SC DAC. All components
are designed pseudo-differentially, i.e. for every logical signal
its inverse is generated, too.
B. Switched-capacitor digital-to-analog converter
The SC DAC is implemented with a differential array of
binary weighted capacitors. The capacitor weight is set by a
parallel connection of switched capacitor unit cells containing
a unit capacitor of Cu
5.3 fF and a three-input switch
connecting the bottom plate to one of three voltages. A metal­
insulator-metal (MIM) capacitor with a thin insulator layer is
used as unit capacitor, the three-input switch is composed of
two cascaded transfer gates.
The SC DAC uses top-plate sampling [3] which reduces
the input capacitance by 50% and operates similar to the
algorithm with split capacitors [1] where each capacitor can
be connected to a positive or a negative reference voltage
=
or v;.ef- as shown in Fig. 3(a). However the binary
weighted capacitors are not split but can be connected to
the common-mode voltage VCM
�(v;.ef+ + v;.ef-) instead,
Fig. 3(b). The voltage transition caused by the switching
operation after the MSB decision can be explained by Fig. 3.
It shows the unit cell array controlled by the MSB, N - 2
binary downscaled unit cell arrays and a reference capacitor
which are connected to the central node in parallel are not
shown. With split capacitors, either the upper switch toggles
to v;.ef- or the lower one to v;.ef+, depending on the MSB.
This causes the voltage across the serial capacitors to change
by ±(v;.ef+ - v;.ef-). Considering the voltage division by two
and the weight of the MSB capacitor array of 0.5 with respect
to the total capacitance, the central node voltage changes by
±:j(v;.ef+ - v;.ef-). In the proposed topology, the bottom
plate of the capacitor is switched between VCM and one of
the reference voltages, i.e. by ± �(v;.ef+ - v;.ef ) Taking
the capacitor weight of 0.5 into account, the central voltage
changes by ±:j(v;.ef+ - v;.ef ) as well, generating the :j and
� threshold levels for the second decision.
After reset, the bottom plates of all 512 unit capacitors are
connected to the common-mode voltage VCM. According to
the comparator decisions, the connections are changed to v;.ef+
to increase the DAC output voltage or to v;.ef- to decrease
it. The SAR outputs Di,a select either VCM or one of the
reference voltages, the outputs Di,b decide which of them is
connected to the bottom plate.
In the layout, the switched capacitor unit cells are placed in
periodic structures surrounded by unconnected dummy cells
for both of the differential arrays. This arrangement provides
the same environment for each cell which reduces mismatch
and distributes parasitics uniformly.
=
_
.
_
C. Comparator
The differential comparator shown in Fig. 4 determines one
bit per step. It has three-stages, the first of which is a pair of
PMOS source followers preventing a static current flow from
the capacitive DAC and shifting up the common-mode level.
The second stage is a current-mode-logic (CML) amplifier
with NPN HBT input transistors Ql and Q2. Its voltage gain
of 23.7 dB improves the comparator's sensitivity and isolates
the inputs from the regenerative nodes of the cross-coupled
p-channel MOSFETs P3 and P4 in the third stage. These
transistors drive the outputs of the third state regeneratively to
o
\.0
�
Fig. 5.
Chip photograph and layout
M r-----�----�--�
. . . . . . . . . . . . • . . . . . . . .j • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • �
',. .... ,ol
1
....... ..... ................."'"\/'''":..''�.< ......
.........
r'�""�J\/r\II'�\
• • • • • • • • • • • • •
• • • • • • • • • • • •
.
0
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\
:... ;/{\).�v�y:..
..
... ". ... -""'-
o L-____�____-L____�______�____-L____�
25
o
50
100
75
fin (MHz)
12.8 MS/s
Fig. 7.
SFDR, SNDR and ENOB at
frequency fin
150
over the input signal
s r-�--��--�-�--,
CD
o
Z
LJ.J
<0
.
. . . . . . . . . . .
:
. . . . . .
.. . . . . . . .
. ...
,
. . . . .
.
.. . . . .
:
.
Fig. 6.
INL at a sampling rate of
fs
=
12.8 MS/s
rail-to-rail levels after the inverted clock signal elk has become
low [4]. A NAND gate is connected to the latch outputs and
acknowledges the completed decision. Its output triggers a
clocked latch holding the comparator decision during the reset
phase.
D. Layout
N
.
. . . . .
.
. ...
;
.
.
. . . . . . . . . . .
:
. . . . . .
,
. . . . .
.
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...
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......
......... .... ,
oL--L__L-�__��__��__-L__L--L__L-��
o
2
4
6
8
10 12 14 16 18 20
26
fs (MSjs)
Fig. 8.
ENOB over the sampling rate
fs
for
fin"'" 2 MHz
48.7 dB. Near Nyquist frequency, the SFDR is 55.4 dB and the
SNDR is 49.5 dB. ENOB reaches 7.9 at DC and remains over
7 up to an input frequency of fin
80MHz. The effective
resolution bandwidth (ERBW) is 19 MHz which exceeds the
third Nyquist band.
Fig. 8 shows that the ADC can operate at higher sam­
pling rates than 12.8MS/s but its performance decreases.
For lower sampling rates and an input signal frequency of
fin ;::::; 2MHz, the ENOB reaches a maximum of 8.2 from
4 MS/s to 10MS/s. For sampling rates exceeding 13 MS/s,
the performance is limited by incomplete sampling due to
the bandwidth of the sampling switch resistance and input
capacitance.
=
A die photograph is shown in the upper half and the chip
layout in the lower half of Fig. 5. The die size is 2. 1 x 0.7 mm2.
The ADC core occupies approximately 0.5 mm2 in the left
half of the chip. Two differential arrays of unit capacitors and
switches in the upper and lower half form the SC DAC. SAR
and comparator are placed in the gap between these arrays,
the output register follows to the right. The reference voltage
generator and the emitter followers are placed in the left part
of the ADC core.
III.
MEASUREMENT RESULTS
This section presents the measured DC and AC character­
istics of the ADC. Measurements are performed with a DC
voltage source and a sinusoidal signal generator connected to
the ADC inputs and a clock source providing the twelvefold
sampling rate. The digital outputs are recorded by a logic
analyzer. At a conversion rate of 12.8MS/s, the ADC draws
17.4 mA from a 2.6 V supply.
Fig. 6 shows the integral nonlinearity (INL) at a sampling
rate of fs
12.8MS/s [5]. It is worse for negative differential
input voltages and approximately remains below ±1 LSB in
the positive range. For smaller sampling rates, e.g. 1MS/s, the
tracking period is 12.8 times longer and the INL is smaller than
0.6 LSB. This indicates that the sampling switches dominate
nonlinearity compared to capacitor matching at 12.8MS/s.
Assuming equal probability for all codes, the rms value of the
the INL is (}INL,eq
0.54 LSB.
The spurious-free dynamic range (SFDR), signal-to-noise­
and-distortion ratio (SNDR) and the effective number of bits
(ENOB) at fs
12.8MS/s are given in Fig. 7. For low­
frequency inputs, the SFDR and the SNDR are 57.8 dB and
=
=
=
IV.
REL ATIONSHIP OF
DC
AND
AC
MEASUREMENTS
Nonlinearity error and noise deteriorate the dynamic perfor­
mance of the ADC. In this section, the INL measurement is
analyzed and its expected value and variance, hence nonlinear­
ity and noise, are related to the maximum achievable SNDR
and ENOB.
The INL derivation is based on records of 200 samples
for a set of equidistant, constant input voltages Vi,D [5].
Subtracting the mean values of these records from an ideal
straight line representing an ideal transfer characteristic of
an infinite-resolution ADC yields the INL given in Fig. 6.
The standard deviations (}Code(Vi,D) given in Fig. 9 show
the amount of random variations of the output codes for a
constant input voltage Vi,D. For input voltages near zero, the
mean of (}Code(Vi,D) has a minimum and it increases towards
the edges of the voltage range. These random variations are
mainly caused by two sources: comparator noise and reference
voltage noise.
Comparator noise has the same impact on all comparator
decisions, hence its power (}�mp effects the conversion range
(4). Thus nonlinearity and random noise degrade the signal­
to-noise-and-distortion ratio by 10 19(O"� +O"fNL +O"�) jO"� dB.
With these results, the expected effective resolution from DC
measurements is
ENOBex = 10
Fig. 9.
Standard deviation
O"Code(Vi,D)
of codes in INL measurement
uniformly. Noisy reference voltages directly disturb the outer
edges of the input voltage range but have no influence on the
middle level. Thus the contribution of the differential reference
voltage noise to the standard deviation of measured codes
depends linearly on the differential input voltage magnitude.
The noise power O"�odeCVi,D) that appears for a constant input
voltage difference Vi,D is given by
)
Vi,D 2
O"2Code(Vi,D) = O"ref Vi
+ O"2cmp
1,D,max
(
(1)
where the maximum allowed input voltage magnitude Vi,D,max
is approximately 0.74 V. In Fig. 9, the mean value of O"Code(O)
gives the comparator's noise contribution O"cmp ;::::: 0.6 LSB.
From O"code(±Vi,D,max) the noise contribution from the ref­
erence voltage generator O"ref ;::::: 0.9 LSB can be determined.
For measuring the SFDR, SNDR or effective resolution of
an ADC, a sine signal is applied to the input. In this case,
the output codes of the ADC are not equally distributed but
follow the probability density function (pdt) of a sine signal.
The pdf of an unscaled sine wave is
Ix(x)=
1
�
-x
'IT
(2)
for x E (-1) 1) and Ix(x) = 0 elsewhere. This pdf can be
scaled to fit the input voltage range by replacing x by v; V;,D
I,D,lnax
The distortion power contained in the digitized sine signal
due to nonlinearity can be estimated by the INL values of
Fig. 6 weighted by a scaled version of Equ. (2). Summing up
the weighted nonlinearity distortion power yields
•
(3)
The amount of random excess noise can be estimated in a
similar way by weighting O"Code with Equ. (2) and determining
its mean square. For the measurement shown in Fig. 9 this
results in
(4)
The SNDR of an ADC with the signal power P, quantiza­
L
tion noise power O"� = �r and uncorrelated excess noise
and distortion power O"� = O"fNL + O"� is given by
P
P
SNDR = 10 19 2
= 10 Ig2
O"Q + O"E2
O"Q
- 10 19 0"2QO"+Q2 O"�
(5)
From the INL measurement, the distortion power and excess
noise O"� = O"fNL + O"� have been derived in Equ. (3) and
2
2
2
O'Q+O'INL +O'N
Ig
0'2
- --------'Q-- =
10
6. 02
8.07
(6)
which fits well to the ENOB measurements. The slightly worse
measured ENOB is mainly caused by additional nonlinearity
of the sampling switch for changing input voltages.
The ENOB could be improved by optimizing the noise
bandwidth of the reference voltage source and finding a better
compromise between comparator speed and noise.
V. C ONCLUSION
An ADC suitable for the application as an assistive circuit
is presented. Having high-impedance inputs and generating
its own reference voltages, it can be used to monitor an
internal voltage or for calibration of an analog or mixed-signal
circuit. The relatively large power consumption of 45.24 mW
is dominated by emitter follower buffers and the op-amp that
generates the reference voltages. It can be tolerated because
the ADC used as an assistive circuit can be turned off
during normal operation of the surrounding circuit. The clock
frequency determines the flexible conversion rate which only
has minor impact on the performance up to 12.8MSjs. Thanks
to the fully differential design, the ADC can be integrated
together with logical circuits without being prone to substrate
or supply noise.
At 12.8MSjs and low frequency input signals, the effective
resolution is 7.9 bit and remains over 7 bit up to 80MHz. For
lower sampling rates, the effective resolution near DC input
reaches 8. 4 bit. This agrees well with INL measurements at
lower sampling rates showing less nonlinearity distortion error.
A method to relate the results of DC-input measurements
to dynamic measurements of SNDR and ENOB is presented.
This method reliably predicts the ADC's dynamic performance
from nonlinearity measurements.
VI. A CKNOWLEDGEMENT
The authors thank J.-c. Scheytt and IHP for providing
chip area in IHP's 250 nm SiGe BiCMOS technology and
supporting the circuit design.
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