A High-Resolution Tail-Capacitor Based Tuning Scheme for LC -DCO
Zisong Wang, Lin He, Lu Yang, and Fujiang Lin
Department of Electronic Science and Technology
University of Science and Technology of China, Hefei, Anhui, 230027, China
Email: wangzs@mail.ustc.edu.cn
helin77@ustc.edu.cn
Abstract— This paper presents a high resolution tuning scheme
for the LC digitally-controlled-oscillator (DCO) based on desensitized tail capacitance tuning. The sensitivity of the oscillation
frequency to the tail capacitance is quantitatively analyzed. The
impact of the tail capacitance on the phase noise is qualitatively
discussed. Our analysis and simulation results show that both the
phase noise and the resolution can be improved simultaneously
if the tail capacitance value is properly designed. A 2.4 GHz
DCO designed in 65-nm CMOS technology is simulated for
demonstration. The tuning resolution can be improved by a factor
of 20, and the phase noise at 1 MHz offset can be improved by
2 dB.
Index Terms— CMOS, DCO, fine tuning resolution, phase
noise, tail capacitance.
I. I NTRODUCTION
With the evolution of sub-micrometer CMOS process, traditional phase-lock-loop (PLL) is being superseded by all digital
phase-lock-loop (ADPLL) [1]. Digitally-controlled oscillator
(DCO), with its crucial impact in phase noise and resolution,
is a vital block in ADPLL. The fine resolution of DCO, along
with the fine resolution of time-to-digital converter (TDC),
strongly affects quantization noise introduced in the ADPLL
band. However, despite the unremitting technology advancement, designing a high resolution LC-DCO in standard RF
COMS technology is still challenging.
A reliable dithering technique proposed in [2] shrinks
considerably the equivalent DCO frequency resolution by
changing the discrete capacitance at high rate. But this still
requires an intrinsic DCO resolution on a level of 10 KHz
or below. Otherwise, a high order Σ∆ converter is needed to
achieve a very fine frequency resolution, which will consume
more area and power.
Designing a DCO with an intrinsic resolution on a level
of 10 KHz is tough in practice. For instance, let us assume
we design a 2.4 GHz class-B DCO with a 3nH inductor
(topology is shown in Fig.1). Thus, changing only 1fF in
resonator will generate a difference of about 800 KHz in
output frequency. This indicates a unitary capacitance in the
order of atto-Farad should be implemented. Nevertheless, a
such small capacitance can be very sensitive to parasitics and
troublesome in layout matching. The difference between states
of a fine tuning NMOS varactor in standard RF CMOS process
is often in the order of femto-Farad, which is apparently far
from enough.
Popular solutions of shrinking intrinsic resolution are custom designs of the capacitive switchable components in tank
[3], [4]. However, in order to fully cover the tuning range,
more tuning components have to be employed by tank. All
Fig. 1. Classical NMOS class-B LC-DCO topology.
these components introduce more parasitic resistances into
LC tank. This will result in a degradation of tank Q-factor,
worsening the phase noise of DCO. Besides, the performance
of these customized units strongly depends on the accuracy of
fabrication process, which is not satisfying in reliability and
robustness.
In order to solve this problem, we present a new scheme
utilizing tail capacitance impacts on frequency and phase noise
in class-B LC-DCO. This method needs no additional active
device or customized unit, and will improve both fine tuning
resolution and phase noise performance.
This paper is organized as follows: Section II discusses
the impacts of tail capacitance in class-B DCO, not least
in frequency and phase noise. Section III proposed a high
resolution tuning scheme for DCO to verify our theory. Section
IV summarized this work’s important points.
II. T HE ROLE OF TAIL C APACITANCE IN CLASS -B DCO
Prior to proposing our new topology, we want to discuss
the impact of tail capacitance Ctail in class-B DCO on
frequency resolution and phase noise. The theoretical analysis
will provide insight to our design.
A. Diminution Effects of the Capacitance in Tail
The classical class-B DCO topology is shown in Fig.1.
For convenience of the capacitance analysis, we divide an
oscillation period into three intervals according to the working
status of cross-coupled pair M1 /M2 (shown in Fig.2.(d)). The
first interval, as shown in Fig.2 (a), is when the differential
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If A > VT H /2, M2 will get into triode region when output
voltage keeps increasing. In this third interval, we have
IDS =
1
1
2
2
β (VOV + A sin ω0 t) − β (2A sin ω0 t − VT H )
2
2
�
��
� �
��
�
M2,L
M2,R
(6)
From (6), we know M2 can be modeled as a pair of backto-back saturated device M2,L and M2,R as shown in Fig.2(c)
[5]. Concerning the equivalent capacitance Ceq that appears
across the tank, the equivalent circuits during (ϕ1 , ϕ2 ) and
(ϕ2 , π − ϕ2 ) are shown Fig.2(b) and Fig.2(c), respectively.
The effective impendence Z2 during (ϕ1 , ϕ2 ) and Z3 during
(ϕ2 , π − ϕ2 ) seen by the resonator are [6]
Z2 =
and
Z3 =
Fig. 2. Equivalent circuits concerning effective capacitance when (a) at
balanced point, (b) during (ϕ1 , ϕ2 ) , (c) M2 in triode region and (d) a sketch
of defined intervals in a period (−π, π).
pair is on, which can be denoted as
{
VDD − A sin ω0 t − VS > VT H
VDD + A sin ω0 t − VS > VT H
(1a)
(1b)
During (−ϕ1 , ϕ1 ), there is a balanced point where the DCO
output voltage equals to 0. As shown in Fig.2(a), the equivalent
capacitance at that point is
Cgs
2
(3)
where Cgs is parasitic capacitance between G and S of
M1 /M2 . From (3), we can see that when the oscillator is
working near the balanced point, the frequency influence
causing by tail capacitance is very small. That is to say,
∆C1 ≈ 0.
As the output voltage increase, one branch will be shut
down. Let us assume M2 is the active one and it works in
saturation region. This part of time can be denoted as
{
−A sin ω0 t < VDD − VS − VT H
(4a)
(4b)
2A sin ω0 t < VT H
(4b) can lead to a radius angle boundary defined as
ϕ2 arcsin
(
VT H
2A
)
1
2gm,M2,R ·Cgs
gm,M2,L
−
Ctail (gm,M2,L −2gm,M2,R )
2gm,M2,L
(7)
]
(8)
Assuming Cgs and Ctail is small, from (7) we can get an
equivalent capacitance as
Ctail
(9)
2
Thus, ∆C2 ≈ −∆Ctail /2. Similarly, from (8), we can get
)
(
1 gm,M2,R
∆Ctail
(10)
∆C3 ≈ − +
2 gm,M2,L
C2 ≈ −
where VS is the source voltage of the cross-coupled pair. And
we can define this time length in (1) as a conduction angle:
)
(
VDD − VS − VT H
(2)
ϕ1 arcsin
A
C1 =
s
[
2gm + 4sCgs + 2sCtail
2 + 2s2 C C
4s2 Cgs
gs tail − sCtail gm
(5)
At the peak amplitude, the triode device will behave like a
short circuit resulting in gm,M2,R = gm,M2,L , which leads
to ∆C3 = ∆Ctail /2. The frequency changed by DCO tail
capacitance can be denoted as
∆f
∆Ceq
≈
f0
2Ctank
(11)
where ∆Ceq is periodic average of ∆C1 , ∆C2 and ∆C3 .
Recalling that ∆C1 ≈ 0 and ∆C2 ≈ −∆Ctail /2, we
can conclude that the effective tail capacitance variation in
resonator will be remarkably diminished, which leads to the
frequency desensitization.
Although the above analysis based on small-signal models
may not sufficiently predict the large-signal behavior of an
oscillator, it still provides insight and theoretical base for our
design.
B. Impacts on Phase Noise
The tail current source M0 in class-B LC oscillator often
has a much larger size than cross-coupled pair M1 /M2 .
Even if we do not design Ctail intentionally, this large M0
will introduce a large tail parasitic capacitance Cpar . For
instance, Cpar is usually between 0.5 pF to 1 pF under 90-nm
CMOS [7]. This Cpar affects noise current behaviours of both
tail current source and differential pair. Thus, our following
discussions applies to all LC-oscillators in classical class-B
topology.
978-1-4799-1928-4/15/$31.00 ©2015 IEEE
Fig. 3. Impacts of tail capacitance in LC-DCO phase noise during (a)
(−ϕ1 , ϕ1 ) and (b) other time in a period.
During (−ϕ1 , ϕ1 ) defined in (2), the noise current flows are
shown in Fig.3 (a). The tank noise injected from the tail current
through M1 and M2 are relevant, and they will cancel each
other at the differential output in oscillator after going through
two paths. Thereupon, the tail current source contribute very
little noise during this time, even without Ctail . The noise
current (at ω0 ±∆ω) of cross-coupled pair, however, will inject
into tank directly generating phase noise during this interval.
Even if some of noise charges of M2 may charge onto Ctail ,
the discharging amount of noise charges which transfer from
Ctail to M1 will counteract this effect. Thus, the existence of
Ctail has little influence in (−ϕ1 , ϕ1 ).
When only one branch of the differential pair is on, the noise
current flows are shown in Fig.3(b). Assuming the active one
is M2 , the tail current MOSFET M0 and M2 just work like
the cascode topology [5]. The tail capacitance forms a path
for noise current i2n,M2 from LC-tank to ground. That is to
say, Ctail impairs the cascode effect which will increase the
noise contribution of M1 /M2 . However, this low impendence
path to ground formed by Ctail also diminishes the portion of
i2n,tail injected to tank. Therefore, it can be seen that Ctail is
friendly to us for tail current noise but bad for cross-coupled
pair noise.
Furthermore, if properly designed, the tail capacitance can
also enlarge the amplitude while keeping the power dissipation
constant, which lead to a better phase noise performance.
Actually, by adding a relatively large tail capacitance, the
current efficiency can be enhanced by one third [8].
With the discussions above, we can conclude that a trade-off
in designing Ctail truly exists when concerning phase noise,
and there must be an optimal point for its value. In Section
III, we will find this optimal point .
Fig. 4. Proposed DCO topology with a tail fine tuning bank.
Fig. 5. Simulation results in optimizing Cf ixed for phase noise.
phase noise. To find this optimal point, spectreRF simulations
on phase noise were run by sweeping the capacitance with
a 200 fF step. The results are shown in Fig.5. It can be
seen the optimal point is around 1 pF, which also verified
our theory in Section II reciprocally. A 2 dB phase noise
improvement can be achieved by this technique. Thus, we
choose the Cf ixed = 1pF to ensure our oscillator has a good
phase noise performance.
III. C IRCUIT I MPLEMENTATION AND S IMULATION
R ESULTS
The proposed DCO fine tuning scheme is shown in Fig.4.
A 2.4 GHz DCO is designed in standard 65-nm CMOS RF
technology for demonstration. A 1nH inductor in the thickmetal layer with a Q factor of 19 is used in LC tank. The
binary coarse tuning tank is designed with MIM capacitances.
A fixed capacitance Cf ixed is placed parallel to tail current
source M0 . The total tail capacitance Ctail = Cpar +Cf ixed +
Cf ine . By properly choosing the value of Cf ixed , Ctail can
be designed to ensure its value is around the optimal point of
Fig. 6. Fine tuning tank.
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TABLE I
S UMMARY R ESULTS AND C OMPARISON WITH S TATE - OF - THE -A RT
This work1
[9]
[3]
Center Freq. (GHz)
2.4
3
5.8
Tuning Range (GHz)
0.54 (24%)
0.78(26%)
0.62(11%)
Coarse Freq. Resolution (MHz)
1.5
24
2.4
Fine Tuning Range (MHz)
2
2∼12
2.75
Fine Tuning Resolution (KHz)
15
0.15∼1.5
14
Power Consumption (mW)
3.7
28.8
9.2
Phase Noise@1MHz (dBc/Hz)
-125.1
-127.5
-117.6
FoM
187
183
183
CMOS Technology
65nm
65nm
180nm
1
Fig. 7. Layout of Proposed DCO core.
Post-simulation results.
We implement the fine tuning capacitance tank with a 8×16
varactor matrix. The schematic is shown as Fig.6. Naturally,
each fine tuning unit has about a 1fF difference between
connection to VDD and Gnd. From post-simulation results,
the total fine tuning range is 2 MHz which can cover the
coarse frequency resolution. According to (11), the ∆Ceq of
each tuning unit is about 50 aF, which has been improved by
a factor of 20. This also substantiates our deduction.
The final layout of our DCO core and phase noise simulation
result are shown in Fig.7 and Fig.8, respectively. The summary
of performance is given in TABLE I, from which we can see
our design is comparable to state-of-the-art in all aspects.
IV. C ONCLUSION
This article has presented a high resolution tuning scheme
for LC-DCO, which is based on desensitized tail capacitance
tuning. The sensitivity of the oscillation frequency to the tail
capacitance is quantitatively analyzed. The impact of the tail
capacitance on the phase noise is qualitative discussed. Our
analysis and simulation results show that both the phase noise
and the resolution can be improved simultaneously if the
tail capacitor value is properly designed. A 2.4 GHz DCO
designed in 65-nm technology is simulated for demonstration.
The tuning resolution can be improved by a factor of 20, and
the phase noise at 1 MHz offset can be improved by 2 dB.
ACKNOWLEDGMENT
This work was partly supported by National Natural Science
Foundation of China, under Grant 61204033. The authors
would like to thank Mr. S. Diao at East China Normal
University, Shanghai, China, Dr. N. Chen, at Kunming Institute
of Physics, Yunnan, China, and Mr. L. Wu at ETH Zurich,
Zurich, Switzerland for helpful discussions and suggestions.
They are also grateful for the support by the Information
Laboratory Center of USTC on EDA tools, and they would
Fig. 8. Post-simulation result of DCO phase noise performance.
also like to acknowledge MediaTek for USTC students and
project sponsorship.
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