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IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 48, NO. 5, SEPTEMBER/OCTOBER 2012
Switched-Capacitor-Cell-Based Voltage
Multipliers and DC–AC Inverters
Ke Zou, Student Member, IEEE, Mark J. Scott, Student Member, IEEE, and Jin Wang, Member, IEEE
Abstract—In this paper, several modular converter topologies
based on a switched-capacitor-cell concept are introduced for
high-power applications. Two types of switched-capacitor cells,
including the full cell and the half-cell, are discussed. The full
cell can be used for dc–ac inversion, and the half-cell is utilized
in both dc–dc and dc–ac applications. A rotational charging
scheme is adopted for the half-cell-based dc–dc voltage multiplier
to eliminate the large output capacitor that exists in many traditional switched-capacitor topologies. A soft-switching scheme,
which does not require extra components, is adopted to reduce
the switching loss and electromagnetic interference. A variable
switching frequency control scheme is proposed to realize soft
switching for dc–ac inverters. The experimental results on a 2-kW
prototype are presented to verify the proposed topologies.
Index Terms—Soft switching, switched-capacitor converters,
variable frequency control.
I. I NTRODUCTION
S
WITCHED-CAPACITOR converters contain only capacitors and switching devices. The absence of magnetic
components helps to shrink the system volume and cost. For
this reason, they have been extensively used in low-power
applications. Various topologies and control methods have
been proposed and applied [1]–[5]. However, many classical
switched-capacitor topologies, such as the traditional chargepump circuit, require either large voltage stress on components
or huge input/output capacitors. Moreover, the traditionally
uncontrolled capacitor charging current generates large current
stress on semiconductor switches, reduces the efficiency of the
converter, and introduces a large amount of EMI noise, which
makes most classical switched-capacitor topologies and control
methods unsuitable for higher power applications.
Several topologies have been developed in recent years to
solve the aforementioned problems. For dc–dc conversion, a
switched-capacitor dc–dc converter based on the generalized
multilevel converter topology was presented in [6]. The 1-kW
prototype introduced in this paper can realize bidirectional
power conversion between a 42-V battery and 14-V or 42-V
Manuscript received June 18, 2011; revised November 9, 2011; accepted
February 9, 2012. Date of publication July 19, 2012; date of current version
September 14, 2012. Paper 2011-IPCC-357.R1, presented at the 2011 IEEE
Applied Power Electronics Conference and Exposition, Fort Worth, TX, March
6–11, and approved for publication in the IEEE TRANSACTIONS ON INDUSTRY
APPLICATIONS by the Industrial Power Converter Committee of the IEEE Industry Applications Society. This work was supported by the National Science
Foundation under Project 1054479.
The authors are with the Department of Electrical and Computer Engineering, The Ohio State University, Columbus, OH 43210 USA (e-mail:
zou.35@buckeyemail.osu.edu; scott.585@osu.edu; wang@ece.osu.edu).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TIA.2012.2209620
loads. In [7], a 3X (i.e., the output voltage is three times of
the input voltage) dc–dc multiplier/divider was proposed, and
a 55-kW prototype for hybrid electric vehicles was built. In
[8], a multilevel modular capacitor-clamped dc–dc converter
(MMCCC) topology was proposed with many benefits, including its modular structure, low current, and voltage stress of the
switches and its bidirectional operation capability. However, the
aforementioned topologies all require a large number of capacitors, which can significantly increase the physical size and the
cost of the converter. Moreover, normally, only one fixed output
voltage can be achieved for these topologies. Although special
control methods [7] can be adopted to realize several output
voltages, the controller complexity will be increased, and the
time response of the output voltage will be affected.
Charging current regulation is important for improving the
efficiency of switched-capacitor converters. Several methods
have been proposed to regulate the charging current by using soft-switching methods. In [9]–[11], the quasi-resonant
switched-capacitor converters are investigated, where an extra
inductor is added to form an oscillation loop with the capacitors
to achieve soft switching. In [12], a soft-switching scheme that
does not require extra inductive components is proposed. Since
the charging current can be controlled by using soft-switching
methods, both the conduction loss and switching loss can be
largely reduced. This soft-switching method has been successfully applied to the MMCCC switched-capacitor topology [13].
Peak efficiency of over 97% for a 630-W prototype has been
reported by further adopting an interleaving scheme [14].
For the dc–ac inversion, in [15], a Marx inverter was proposed, which is based on the Marx generator concept in highvoltage engineering. A Marx cell structure was generalized
from the Marx generator. By connecting several Marx cells in
series, multiple output voltage levels can be achieved. A similar
structure with the benefits of common input and output grounds
was presented in [16]. The benefits of Marx-cell-based inverters
include its multiple output voltage capability, the small number
of required capacitors, and its equal voltage stress on the
switches and capacitors. In [17] and [18], two other topologies
are provided that can realize multiple output voltage and can be
used for dc/ac inversion. However, since the capacitor charging
time in an inverter changes from cycle to cycle, the softswitching method aforementioned cannot be utilized. Therefore, the capacitor charging current in a switched-capacitor
inverter has an extremely large peak value, which generates large
power losses as well as electromagnetic interference (EMI).
To solve the aforementioned problems, this paper extends the
Marx cell concept and proposes two different cell structures—
the half-cell and the full cell. It can be seen that the Marx cell
0093-9994/$31.00 © 2012 IEEE
ZOU et al.: SWITCHED-CAPACITOR-CELL-BASED VOLTAGE MULTIPLIERS AND DC–AC INVERTERS
Fig. 1. Structure of switched-capacitor cells. (a) Full cell. (b) Half-cell.
(c) Series connection of switched-capacitor cells.
is equivalent to the half-cell. The half-cell-based dc–dc multiplier adopts a rotational charging scheme and a soft-switching
scheme. As a result, the large output capacitor can be eliminated, and the efficiency can be increased. For dc–ac conversion, both the half-cell-based and the full-cell-based inverters
are presented. To realize soft switching over the entire operation
range of the inverter and reduce the peak charging current, a
variable switching frequency control scheme is proposed.
The rest of this paper is organized as follows. in Section II,
the proposed half-cell and full-cell topologies are introduced.
The half-cell-based dc–dc multiplier, including its structure and
control scheme, is presented in Section III. Section IV shows
the half-cell-based and full-cell-based dc–ac inverter topologies. The multicarrier pulsewidth modulation (PWM) control
method and the variable frequency control method are also
presented. Finally, the experimental results on a 2-kW modular
converter prototype are presented in Section V.
II. BASIC S WITCHING C ELLS
A. Cell Structure
The full switched-capacitor cell is shown in Fig. 1(a). It is a
four-port system consisting of four switches and one capacitor.
The half-cell (Marx cell) is shown in Fig. 1(b), with only
three switches and one capacitor. The final converter is a series
connection of these cells, as shown in Fig. 1(c). Each cell is
charged by the cell of the previous stage and discharges to the
cell of the next stage. Here, the voltage source is placed before
the first cell, whereas an alternative method is to put the voltage
source in the middle of the series so that the current stress of
central cells can be reduced.
Fig. 2 shows the switching states of one full cell. In this
figure, C1 is the capacitor from the previous stage and has a
voltage of VC . Port 2 is assumed to have a voltage potential
of V2 . Among the four switches in Fig. 2(a), S1 and S2 form
one group and are switched together. S3 and S4 are independent
switches and cannot be turned on along with any other switches.
As a result, there are three switching states.
i) S1 and S2 are on [see Fig. 2(b)]. The two capacitors are
connected in parallel. Port 4 has the same potential as port
2. The potential of ports 1 and 3 is V2 + VC .
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Fig. 2. Operation states of a full cell. (a) Full switched-capacitor cell.
(b) State I. (c) State II. (d) State III.
ii) S3 is on [see Fig. 2(c)]. Ports 1 and 4 have the potential of
V2 + VC , and port 3 has a potential of V2 + 2VC .
iii) S4 is on [see Fig. 2(d)]. Port 3 has a potential of V2 . The
potentials of ports 1 and 4 are V2 + VC and V2 − VC ,
respectively.
In switching state I, two capacitors are connected in parallel,
and the one with higher voltage charges the other. In states II
and III, the two capacitors are connected in series; therefore,
various voltage levels can be achieved. For one single full
switching cell, there are three achievable voltage levels for
port 4: V2 , V2 + VC , and V2 − VC . Port 3 also has three
achievable voltage levels: V2 , V2 + VC , and V2 + 2VC .
By connecting N switching cells in series, there are 2N + 1
achievable levels between port 3 or port 4 of the last stage and
port 2 of the first stage. If port 2 of the first stage has zero
voltage potential, then for port 4 of the last stage, the achievable
voltage levels are i × VC , where i is an integer between −N
and N . Since both positive and negative voltage levels can be
generated in a symmetric manner, the full switched-capacitor
cell is suitable for dc–ac inverting applications.
For the half switched-capacitor cell, there are only two
switching states: State I, where S1 and S2 are on, and state II,
where S3 is on (see Fig. 2(b) and (c), respectively). The number
of achievable voltage levels for port 3 or port 4 in a converter
with N stages of half switched-capacitor cell is N + 1. If port 2
of the first stage has zero voltage potential, then for port 3 of the
last stage, the achievable voltage levels are (i + 1) × VC , where
i is an integer between 0 and N . The dc–dc voltage multiplier
can be realized by connecting the load to port 2 of the first stage
and port 3 of the last stage.
For the half-cell, negative voltage can also be achieved by
connecting the previous stage between ports 3 and 4. This
way, the dc–ac inverting operation can be achieved by employing half-cells, which is the Marx inverter topology presented
in [15].
B. Component Selection of Proposed Cells
For a half-cell, the diagonal switch S3 only conducts
forward current and blocks forward voltage. For the other
two switches S1 and S2 , however, in order to prevent the
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IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 48, NO. 5, SEPTEMBER/OCTOBER 2012
Fig. 3. Realization of switching cells using MOSFETs. (a) Half-cell circuit.
(b) Full-cell circuit.
shoot-through when S3 is closed, one switch has to block the
forward voltage and another has to block the reversed voltage.
As such, there are two forward-current-conducting–forwardvoltage-blocking switches such as an insulated gate bipolar
transistor (IGBT) or a MOSFET and one forward-currentconducting–reversed-voltage-blocking switch such as a diode.
To achieve bidirectional power flow capability of the converter,
all switches can be realized by MOSFETs, and some MOSFETs
operate in the third quadrant.
For a full cell, when it operates in state II [see Fig. 2(c)], the
diagonal switch S4 needs to block a voltage that equals to two
times the capacitors voltage VC . Similarly, the diagonal switch
S3 needs to block 2VC in state III. The other two switches need
to block both positive and negative voltages during states II and
III. As a result, the two diagonal switches S3 and S4 can be
realized by MOSFETs or IGBTs with a voltage rating of 2Vc
and a parallel free-wheeling diode, whereas each of the other
two switches, i.e., S1 and S2 , requires two MOSFETs or IGBTs,
with a voltage rating of VC . The realizations of the half-cell and
the full cell using MOSFETs are shown in Fig. 3(a) and (b),
respectively.
III. H ALF -C ELL -BASED DC–DC M ULTIPLIER
A. Structure
For half-cell-based dc–dc multipliers, port 3 of the last stage
and port 2 of the first stage are used as output ports to achieve
the largest voltage transfer ratio. Although N + 1 voltage levels
can be achieved between these two ports in an N -stage halfcell multiplier, it is not possible to have (N + 1):1 voltage
transfer ratio since there is only one switching state to achieve
(N + 1) × VC , and the capacitors in this state are all in the
discharging mode. As a result, the output voltage cannot be
maintained.
With this modular switching cell structure, a rotationally
charging scheme can be adopted to reduce the requirements
of the output capacitor. This is achieved by adding one extra
half-cell to the multiplier. By doing this, the multiplier has
N + 1 stages, and two switching states are available to achieve
an output of (N + 1) × VC . This extra available state makes
it possible to generate a stable output voltage by charging the
capacitors rotationally. At any time, except the dead time, there
will be one capacitor in the charging state, and other capacitors
are discharging to the load in series. The output voltage is
Fig. 4.
DC–DC voltage doubler based on half-cells.
Fig. 5.
Equivalent circuit when C1 is being charged.
stable, and only a small output capacitor is needed to filter
out the voltage ripple during the dead time. Another benefit of
the proposed topology is that multiple output voltages can be
achieved. For example, a three-stage multiplier with an input
voltage of Vin can output Vin , 2 Vin , and 3 Vin . This rotationally
charging scheme and multiple output voltage capability can
also be found in previous studies such as [17] and [18].
B. Soft-Switching Principle
One major problem of a switched-capacitor circuit is the
unregulated charging current during the capacitor charging
process, which generates large in-rush current and EMI noise.
In [12], a soft-switching scheme is proposed by utilizing the
stray inductance in the circuit to resonate with the main capacitors. This paper employs the same idea; however, due to
the particular structure of the proposed multiplier, the softswitching scheme has some unique features.
Fig. 4 shows a voltage doubler that consists of two half-cells.
The dc source is placed in the middle so that the switches of
the both cells experience the same charging current. In this
structure, when S4 and S5 are closed, the charging current of C2
flows from the source to the drain of S4 , instead of the normal
drain-to-source conduction mode. Therefore, S4 operates in the
third quadrant. S2 on the other cell has the same third-quadrant
operation mode. Other MOSFETs in the circuit operate in
the first quadrant. The stray inductance values, expressed as
Ls1 − Ls5 , mainly come from the stray inductance of cables,
the package inductance of the MOSFETs, and the equivalent
series inductance (ESL) of the capacitors. If the layout of each
cell is the same, the stray inductance difference among different
cells can be considered small; therefore, a single resonant
switching frequency works for both cells.
The equivalent circuits in the two switching states are shown
in Figs. 5 and 6. To simplify the analysis, the load current is
ZOU et al.: SWITCHED-CAPACITOR-CELL-BASED VOLTAGE MULTIPLIERS AND DC–AC INVERTERS
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Fig. 8. Charging current of capacitor C1 .
Fig. 6.
Fig. 7.
Equivalent circuit when C2 is being charged.
Equivalent circuit during the dead time.
assumed to be constant as Id . The capacitor charging currents
are named as IC1 and IC2 , which flow from the voltage source
to C1 and C2 , respectively. It can be seen that S1 and S5 , which
operate in the first quadrant, carry only the capacitor charging
current. On the other hand, S2 and S4 , which operate in the third
quadrant, carry both the capacitor charging current and the load
current Id .
The proposed soft-switching scheme involves choosing a
switching frequency such that the charging current drops to zero
at the time when S1 or S5 are turning off. As a result, zerocurrent switching is realized for S1 and S5 . For S2 and S4 , at
the moment when they are turning off, the remaining current is
Id . Due to the third-quadrant operation, their body diodes D2
and D4 will immediately take over the current. As a result, the
soft switching of S2 and S4 is achieved. After the dead time,
the current is shifting from diode D2 or D4 to the diagonal
MOSFETs S3 or S6 ; therefore, there will be reverse recovery
loss of diodes. However, if SiC diodes is used to replace D2
and D4 , this reverse recovery loss can be minimized.
During the dead time, the load current flows through the body
diodes D1 , D2 , D4 , and D5 . Assuming that the two half-cells
are made the same and that the dead time is long enough for any
oscillation transients to decay, the load current will be equally
split into two parts, as shown in Fig. 7. The only voltage across
these diodes is the diode forward voltage; therefore, when their
corresponding MOSFETs are turning on after the dead time,
they will experience a minimum voltage. Therefore, the zerovoltage turn-on can be achieved for S1 , S2 , S4 , and S5 .
It should be noted that this soft-switching scheme only applies to the MOSFETs that are used to charge the capacitors. For
the other two MOSFETs (S3 and S6 ), soft switching cannot be
achieved using this scheme. However, since the main purpose
of utilizing soft switching is to reduce the associated power loss
and EMI noise due to unregulated charging current, this soft-
switching scheme can still help the proposed topology in largepower applications.
If the equivalent resistance in the charging loop can be
neglected, the impedance of the capacitor charging loop can be
represented by a simple LC circuit. Under this assumption, the
capacitor charging current has a sinusoidal shape. The current
profile of IC1 is shown in Fig. 8. The initial current −I0 is
due to the load current conduction during the dead time before
S1 and S2 are turned on. Therefore, the charging current has
a negative initial angle −θ0 . The current reaches zero again at
the angle π, which is the soft-switching point. This means that
the charging process needs to be finished in more than half an
oscillation cycle to achieve soft switching.
After the charging process, the capacitor discharges to the
load with the load current Id . Therefore, the capacitor current
can be written as
Ipeak sin(ωosc t − θ0 ), 0 < t < DTS
iC1 (t) =
(1)
−Id ,
DTS < t < TS
where D is the duty ratio of S1 and S2 , and TS is the switching
cycle. Ipeak and ωosc are the amplitude and angular frequency
of the sinusoidal part of the charging current, respectively.
The relationship between ωosc and angular switching frequency
ωsw is
ωosc =
π + θ0
ωsw .
2πD
(2)
Assuming that, during the dead time, the free-wheeling load
current is evenly distributed into two branches, then the initial
value of the capacitor charging current I0 is
1
I0 = ic1 (0) = − Id
2
(3)
and θ0 can be found from the following relationship:
Id
= Ipeak × sin θ0 .
2
(4)
On the other hand, due to the current balance of the capacitor
in one switching cycle
DTS
π + θ0
π
(Ipeak sin θ)dθ = Id (1 − D)TS .
(5)
−θ0
Solving (5),
1 + cos θ0
= 2(π + θ0 )
sin θ0
D
1−D
.
(6)
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IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 48, NO. 5, SEPTEMBER/OCTOBER 2012
S3 carries only the load current during the second half cycle.
The three current can be written as
0)
1.75Id sin 2(π+θ
t−θ0 , 0 < t < TS /2
T
S
IS1 =
(11)
0,
TS /2 < t < TS
0)
1.75Id sin 2(π+θ
t−θ
+Id , 0 < t < TS /2
0
T
S
IS2 =
(12)
0,
TS /2 < t < TS
0,
0 < t < TS /2
IS3 =
(13)
−Id , TS /2 < t < TS .
Fig. 9. Current profiles for the switches in the left cell.
Equation (6) gives the relationship between θ0 and the duty
ratio D. For the dc–dc voltage doubler, since D = 0.5, θ0 can
be calculated to be 0.29◦ or 16.6◦ .
From (4), the peak value of the capacitor charging current
Ipeak can be calculated as
Ipeak =
Id
= 1.75Id .
2 × sin(θ0 )
(7)
π + θ0
Tosc
2π
0
(14)
= 0.833Id
T /2
2
1
2(π+θ0 )
IS2_RMS = t−θ0 +Id dt
1.75Id sin
T
TS
0
The capacitor charging time Tch can be calculated using
Tch =
The RMS value of the three currents can be calculated as
T /2
2
1
2(π+θ0 )
IS1_RMS = t−θ0
dt
1.75Id sin
T
TS
(8)
= 1.447Id
T /2
1
IS3_RMS = Id2 dt = 0.707Id .
T
(15)
(16)
0
where Tosc is the oscillation cycle of the charging current.
The soft-switching frequency fsw can be calculated as
follows:
fsw =
2πD
.
(π + θ0 )Tosc
(9)
For the switched-capacitor voltage doubler, D is 0.5. Thus,
fsw =
π
.
(π + θ0 )Tosc
(10)
C. Power Loss Analysis on the Proposed Voltage Doubler
The switching losses on switches S1 , S2 , S4 , and S5 of the
proposed voltage doubler can be neglected due to their softswitching operation. The switching loss analysis on the other
two switches (S3 and S6 ) is similar to the analysis in traditional
boost converters, which is not elaborated here.
There are three types of conduction losses: the conduction
loss on the switches, on two main capacitors, and on the input
capacitor. The conduction loss can be calculated from the RMS
value of their corresponding current.
RMS Current of Switches: Fig. 9 shows the current profiles
of the three switches in the left cell (i.e., S1 , S2 , and S3 ). S1 and
S2 only conduct in the first half cycle, and S3 only conducts
in the second half cycle. S1 carries the capacitor charging
current; therefore, it shares the same current as the charging
current of C1 . The third-quadrant-operated switched S2 carries
the capacitor charging current and the load current. The switch
Due to the symmetric structure of this doubler, the three
switches in the right cell have the same current profile and RMS
values as the corresponding switches in the left cell.
RMS Current of the Two Main Capacitors: The two main
capacitors experience the same current, as the current shown in
Fig. 8 when D is 0.5. The RMS value of the current on the two
capacitors can be calculated as
IC1_RMS
T /2
2
1
2(π + θ0 )
1
=
t−θ0
dt+ Id2
1.75Id sin
T
TS
2
0
= 1.093Id .
(17)
RMS Current of the Input Capacitor: The input current is
the sum of IS2 and IS4 . It has an average value of 2Id and
an ac ripple. The ac part of the input current flows into the
input capacitor and generates loss. The RMS value of the input
current ripple is
π
1
(1.75Id sin θ + Id − 2Id )2 dθ
ICin_RMS = π + θ0
−θ0
= 0.387Id .
(18)
Table I provides the RMS current and the conduction loss of
different components in the proposed voltage doubler. RS , RC ,
and RC_in represent the ON-state resistance of the switch, the
ZOU et al.: SWITCHED-CAPACITOR-CELL-BASED VOLTAGE MULTIPLIERS AND DC–AC INVERTERS
TABLE I
RMS CURRENT AND CONDUCTION LOSS OF DIFFERENT
COMPONENTS IN THE PROPOSED VOLTAGE DOUBLER
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In Fig. 4, the state equations can be written as
⎧
v̇C1 = 1 iLS1
⎪
⎪
⎪ v̇ = C1 (i
⎪
C2
⎪
C LS1 − iLS2 )
⎪
⎨
i̇LS1 = L1 ((iLS2 − iLS1 )R − vC1 − vC2 )
⎪
i̇LS2 = L1 (Vin + vC2 − (iLS2 − iLS1 )R)
⎪
⎪
⎪
⎪
⎪
⎩ i̇LS4 = 0
i̇LS5 = 0.
TABLE II
LOSS COMPARISON BETWEEN THE PROPOSED VOLTAGE DOUBLER
AND THE T RADITIONAL V OLTAGE D OUBLER W ITH
SOFT-SWITCHING CAPABILITY
Then, A1 and A2 can be obtained as
⎡
1
0
0
0
C
1
1
⎢ 0
−
0
C
C
⎢ 1
1
R
R
⎢−
−L −L −L
L
A1 = ⎢
R
1
⎢ 0
−R
⎢
L
L
L
⎣ 0
0
0
0
0
0
0
0
⎡
0
0
0 0 − C1
⎢ 0
0
0 0
0
⎢
⎢ 0
0
0
0
0
A2 = ⎢
⎢ 0
0
0
0
0
⎢ 1
⎣ L
0
0 0 −R
L
R
− L1 − L1 0 0
L
(21)
⎤
0
0⎥
⎥
0⎥
⎥
0⎥
⎥
0⎦
0
0
0
0
0
0
0
1
C
1
C
⎤
⎥
⎥
0 ⎥
⎥.
0 ⎥
⎥
R ⎦
L
−R
L
This voltage doubler operates with a duty ratio of 50%. Thus
equivalent series resistance (ESR) of the main capacitors, and
the ESR of the input capacitor, respectively.
Table II provides a comparison between the proposed voltage
doubler and the traditional switched-capacitor voltage doubler with soft-switching capability [12]. Ploss_S , Ploss_C , and
Ploss_Cin represent the total conduction loss on all of the
switches, on the two main capacitors, and on the input capacitor, respectively. The proposed switched capacitor has a much
smaller input current ripple and conduction loss compared with
the traditional voltage doubler. This is because, in the proposed
topology, the voltage source is always connected in series with
one capacitor. Therefore, half of the power is directly sent to
the load.
D. Stability Analysis of the Proposed Voltage Doubler
The stability of the proposed voltage doubler is analyzed
using the state-space averaging method. The state vector for the
voltage doubler in Fig. 4 is
x(t) = [VC1 , VC2 , iLS1 , iLS2 , iLS4 , iLS5 ]T .
A = 0.5 × A1 + 0.5 × A2
⎡
1
0
0
C
1
⎢ 0
0
C
⎢ 1
1
1 ⎢ −L −L −R
L
A= ⎢
R
1
2⎢
L
L
⎢ 0
⎣ 1
0
0
L
− L1 − L1
0
= 0.5 × (A1 + A2 )
⎤
0
− C1 − C1
1
1
⎥
−C
0
C ⎥
⎥
−R
0
0
L
⎥.
⎥
−R
0
0
L
⎥
R ⎦
R
0
−
0
L
R
L
(22)
(23)
L
−R
L
The following characteristic polynomial can be obtained
from (23):
λ6 +
(6L + 4R2 C)λ4 + 14Rλ3
4Rλ5
+
L
L2 C
+
R2
(5L + 4R2 C)λ2 + 6Rλ
+
= 0.
L3 C 2
L4 C 2
(24)
Calculations have been performed on the six eigenvalues of
A to determine their variation with changes in load resistance.
In these calculations, L and C are set to be 58.8 nH and 47 μF,
respectively, which is a value measured on the testing prototype.
Fig. 10 shows the locus of the six eigenvalues as R decreases
from 20 to 1 Ω. The real part of the eigenvalues stays on the lefthand side of the imaginary axis, showing the voltage doubler is
stable in this load range.
(19)
To simplify the analysis, it is assumed that C1 = C2 = C and
LS1 = LS2 = LS4 = LS5 = L. The doubler is modeled as
IV. F ULL -C ELL -BASED AND H ALF -C ELL -BASED
DC–AC I NVERTERS
A. Full-Cell-Based Inverters
ẋ(t) = Ax(t) + Bu(t)
where A = A1 d + A2 (1 − d) and B = B1 d + B2 (1 − d).
(20)
From the analysis in Section II, for an N -stage full-switchedcapacitor-cell-based converter, there are 2N + 1 achievable
voltage levels between port 2 of the first stage and port 4 of
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Fig. 12.
Five-level half-cell switched-capacitor inverter.
Fig. 13.
Six sections for a five-level switched-capacitor inverter.
Fig. 10. Locus of eigenvalues with a resistance from 20 to 1 Ω.
C. Multicarrier PWM Control Method for a Five-Level
Switched-Capacitor Inverter
Fig. 11. Five-level full-cell switched-capacitor inverter.
the last stage. As a result, to realize a 2N + 1 level of inverter,
only N full cells are required.
Fig. 11 shows one five-level dc–ac inverter consists of one
full cell and four extra switches S5 −S8 . The extra switches are
always connected to the load and function as current bypass
routes. By adding these four switches, the total achievable
voltage levels can be increased by 2. Therefore, only N − 1 full
cells are required to have a 2N + 1 inverter. In Fig. 11, one full
cell is enough to realize a five-level inverter. It should be noted
here that this inverter has a good switching redundancy, which
can help to balance the capacitor voltage and improve the fault
tolerance capability of the circuit.
B. Half-Cell-Based Inverters
Due to the high switching component requirements for the
full-cell-based inverter, half-cell-based inverters can be the
alternative choice. To realize a 2N + 1-level inverter, 2N halfcells are required. If four extra bypass switches are employed,
2N − 2 half-cells are required to have a 2N + 1-level inverter.
The number of stages required for a half-cell-based inverter is
two times the requirement for a full-cell-based inverter. The
capacitor count is doubled, and more current stress is added to
central cells.
A half-cell-based five-level inverter is shown in Fig. 12. This
topology was introduced in [15]. It consists of two half-cells
and four extra bypass switches S7 −S10 .
The design of a high-power switched-capacitor dc–ac inverter is more complex than the dc–dc multiplier. The main
reason is that the duty ratio of the inverter changes from cycle
to cycle, similar with the capacitor charging time. Therefore,
the charging current cannot be well controlled. Two methods
are proposed to solve this problem: a multicarrier PWM control
method and a soft-switching scheme using variable frequency
control.
The multicarrier PWM control scheme is used to eliminate unnecessary capacitor charging. The half-cell-based fivelevel inverter, as shown in Fig. 12, is used to illustrate this
method. Based on the capacitor charging characteristics, the
voltage modulation waveform for this inverter can be divided
into six sections, as shown in Fig. 13. The angle θ1 in
Fig. 13 can be calculated by using the modulation index ma
as follows:
1
θ1 = sin−1
.
(25)
2ma
Table III shows seven switching vectors used in this control
scheme. In order to minimize the capacitor charging loss, the
capacitor charging and discharging only occur in Sections II
and V, where positive or negative 2 Vin is needed. In other
sections, where the inverter only output ±Vin or zero voltage,
the capacitors are in the idle state, and there is no charging
activity. The source is directly connected to the load to output
Vin (vector V3 ) or −Vin (vector V5 ), and it is bypassed when
zero voltage is needed (vector V4 ). In these regions, the inverter
functions as a normal H-bridge inverter.
ZOU et al.: SWITCHED-CAPACITOR-CELL-BASED VOLTAGE MULTIPLIERS AND DC–AC INVERTERS
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TABLE III
SWITCHING VECTORS OF THE FIVE-LEVEL SWITCHED-CAPACITOR INVERTER
D. Soft-Switching Scheme for Switched-Capacitor Inverters
To realize soft switching at Sections II and V, a variable
frequency control scheme is proposed. In this scheme, the
switching frequency changes with the duty ratio to maintain a
constant capacitor charging time. Therefore, soft switching can
be realized for all cycles.
The relationship between the charging time and the instantaneous duty ratio is
Tch (t) = (1 − D(t))
1
.
fsw (t)
(26)
The switching frequency can be calculated from (8) and (26)
as follows:
1
(1 − D(t)) × 2π
×
.
π + θ0 (t)
Tosc
The peak capacitor charging current can be calculated as
follows:
π
(1 − D(t))
Ich_peak sin(θ)dθ = D(t)Id (t).
(32)
π
−θ0
Note here the instantaneous duty ratio D(t) is defined as
2ma sin(ωt)−1, θ1 < ωt < π−θ1
D(t) =
(27)
−2ma sin(ωt)−1, π+θ1 < ωt < 2π−θ1 .
fsw (t) =
The initial angle θ0 can be neglected at large duty ratio
conditions, due to the fact that θ0 becomes negligible when the
peak current is large; then, ΔVC _ max can be estimated as
2ma − 1
1
Id_peak Tosc
ΔVC _ max ≈
.
(31)
2C
2 − 2ma
(28)
Equation (28) provides a relationship between D(t) and the
switching frequency. Since θ0 only depends on D(t), a lookup
table of θ0 can be made for different duty ratios to expedite the
calculation of the switching frequency in real applications.
It should be noted that the switching frequency should have a
low limit. Otherwise, the capacitor will be overdischarged. The
capacitor voltage variation in one switching cycle is
1
1
Id (t)D(t)
C
fsw (t) π + θ0 (t)
1
1
− 1 . (29)
= Id (t)Tosc
C
2π
1 − D(t)
ΔVC =
It is shown from (29) that the capacitor voltage ripple increases with the load current Id (t) as well as D(t). The worst
scenario is at unity power factor, in which the load current Id (t)
and D(t) reach their peak value simultaneously. From (27),
Dmax (t) = 2ma − 1. Then, the peak capacitor voltage ripple is
π + θ0 (t) 2ma − 1
1
ΔVC _ max = Id_peak Tosc
. (30)
C
2π
2 − 2ma
Solve (32) as follows:
π
1
−1
Id (t).
Ich_peak =
2−2ma sin(θ)
(1+cos(θ0 ))
(33)
Under the condition where the power factor is large, the peak
current occurs near the peak voltage point, and cos(θ0 ) ≈ 1;
then,
1
π
− 1 Id_peak .
(34)
Ich_peak ≈
2 2 − 2ma
Equation (34) gives the estimated maximum capacitor charging current of the proposed method. It can be seen that both
the modulation index and the load current affect the maximum
charging current.
The third-quadrant operated switches (S1 and S4 in Fig. 12),
which carry both the capacitor charging current and load current, experience the highest current stress
π
π
− + 1 Id_peak .
(35)
IS1 _peak ≈
4 − 4ma
2
Given the peak load current and maximum safety current of
the switching devices, the maximum modulation index can be
calculated from (35).
E. Simulation Results
A simulation on a 20-kVA switched-capacitor inverter has
been performed using PSIM to verify the control method proposed in this paper. In this simulation, the dc input of this
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Fig. 16.
Photograph of the prototype cell.
Fig. 17.
Input and output voltage waveform of the voltage doubler.
Fig. 14. Simulation results of the inverter.
Fig. 15. Frequency spectrum of the output voltage.
inverter is 300 V, and the modulation index is 0.8. The load
is a constant RL load with resistance of 2 Ω and inductance
of 3.5 mH. The power factor of this converter is 0.83. To
realize soft switching at around 20 kHz, the loop inductance
is selected to be 200 nH, and the capacitance of the capacitor
is 300 μF.
Fig. 14 shows the output voltage, output current, the current
of S2 , and the switching frequency. It can be seen that, the
switching frequency is kept constant at 20 kHz in Sections I,
III, IV, and VI. In Sections II and V, where capacitor charging
occurs, the switching frequency varies from 15 to 25 kHz. The
peak current of S2 is about 426 A, whereas the peak load current
is 197 A. This ratio of peak charging current over peak load
current is 2.16, which is consistent with the estimated value of
2.36 from (34).
Fig. 15 shows the frequency spectrum of the output voltage.
Because of the variable frequency control, there is a band of
frequency components between 15 and 25 kHz.
V. E XPERIMENTAL R ESULTS
A group of 1-kW half-cell prototypes has been built to verify
the ideas presented in this paper. The photograph of this cell
is shown in Fig. 16. Three MOSFETs (IRFI4410ZPbF) are
placed in parallel to form one switching device. To reduce the
reverse recovery loss of the body diode, a power Schottky diode
(STPS30100ST) is used. Ten 100-V 4.7-μF ceramic capacitors
(C5750X7R2A475K) are used together as the main capacitor.
The soft-switching frequency of a voltage doubler is measured
at an input voltage of 5 V and room temperature. When the
switching frequency is adjusted to 62.7 kHz, the zero-current
turn-off is achieved. With the assumption that the capacitance
of the capacitor under this test condition is 47 μF, the total loop
stray inductance can be calculated as 117.6 nH.
A. DC–DC Multiplier Test
A half-cell dc–dc voltage doubler, which consists of two
prototype boards, is used to verify the soft-switching scheme
and the efficiency. The circuit topology is shown in Fig. 4. The
dead time is set to be 200 ns. A small 10-μF film capacitor
is added to the output terminal to filter out the ripples during
the dead time. At an input voltage of 40 V, the zero-current
turn-off is achieved for S1 and S5 at a switching frequency of
75.9 kHz. Compared with the case when the input voltage is
5 V, the soft-switching frequency is increased, which is because
the capacitance of the ceramic capacitors decreases with the
increase in voltage.
Fig. 17 shows the input and output voltage together at a
load current of 10 A. Fig. 18 shows with the drain–source
voltage Vs1 and the drain current IS1 of S1 . It can be seen that
IS1 drops to zero before the switching transient; therefore, the
ZOU et al.: SWITCHED-CAPACITOR-CELL-BASED VOLTAGE MULTIPLIERS AND DC–AC INVERTERS
1607
Fig. 18. Current and turn-off voltage of S1 .
Fig. 20. Breakdown of power loss at input power of 1000 W.
Fig. 19. Efficiency curve of the proposed dc–dc multiplier.
zero-current turn-off is realized. The peak value of IS1 is
17.2 A, which is consistent with (7).
Fig. 19 shows the efficiency of the prototype from 200 to
2000 W with 40-V fixed input voltage. It is measured with a
Yokogawa WT 3000 power meter and LEM IT 700-S highperformance current transducer.
Fig. 20 shows the calculated power-loss breakdown among
different components at an input power of 1000 W. The calculation on conduction losses is based on Table I. Since the
converter is built on a printed circuit board (PCB) with 2 OZ/ft2
and a trace width of 300–500 mils, the loss on PCB traces
contributes to a large portion (around 30%–40%) of the total
loss. Therefore, in this power-loss breakdown, the resistance
values of the capacitor and switches are estimated together with
the ac resistance (at 70 kHz) of the PCB traces that they are
connected to. The switches have an average resistance of 8 mΩ.
The resistance of the main capacitors and the input capacitor
is estimated to be 3.4 and 10 mΩ, respectively. The switching
power loss of the two diagonal switches S3 and S6 is estimated
using the turn-on time and turn-off time of the MOSFETs from
the datasheet. The diode loss is the conduction loss of the four
Schottky diodes during the dead time. Other losses include
the conduction losses on the connection cables, the reverse
recovery loss of the diodes, the loss due to charging the body
capacitance of the MOSFETs during operation, and estimation
error.
Fig. 21. Input and output voltage waveforms of the inverter.
The control power contributes to around 25% of the total
loss. The conduction loss of the switches and capacitors consists of more than 45% of the total loss. The switching loss is
only 12% of the total loss, which proves the effectiveness of the
soft-switching method.
B. DC–AC Inverter Test
A five-level dc–ac inverter is built and tested using the
switching-cell prototypes. The circuit structure is shown in
Fig. 12. It is realized by four switched-capacitor prototype
boards. The modulation index is set to be 0.8. An adjustable
RL load with a constant power factor of 0.83 is used. In
the experiment, the switching frequency changes from 48.6 to
83.3 kHz to realize the soft switching for all capacitor charging
cycles.
Fig. 21 shows the waveforms of input voltage Vin and output
voltage Vout at a load condition of 17.4 mH and 9.4 Ω. The
active power at this load condition is 272 W. The RMS value
of the fundamental output voltage and current is 58.74 V and
5.38 A, respectively. The RMS value of the total output voltage
is 62 V. According to IEEE Standard 519 [19], in which the total
harmonics distortion (THD) is calculated up to 40th order, the
voltage THD is 4.98%. The main reason for the harmonics is
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Fig. 22. Waveforms of the output current Id and the charging current IC1 .
Fig. 24.
Efficiency curve of the proposed dc–ac inverter.
VI. C ONCLUSION
This paper introduced two types of switched-capacitor cells:
the half-cell and the full cell. Both the dc–dc multipliers and
the dc–ac inverters based on these cells are analyzed. For the
dc–dc multiplier, a rotational charging scheme is proposed;
therefore, the large output capacitor required by traditional
switched-capacitor topologies can be eliminated. For the dc–ac
inversion, a multilevel inverter with voltage boost function can
be realized by using either the full cell or the half-cell. To
increase the efficiency, a soft-switching scheme without adding
extra components is adopted, and a variable frequency control
for the inverter is proposed to realize full-range soft switching.
The proposed topologies and control methods can be used in
applications with a power range from subkilowatts to tens of
kilowatts.
Fig. 23. Zoomed-in capacitor charging current of the inverter.
R EFERENCES
the large stray inductance of the current paths when the inverter
functions as an H-bridge inverter. This occurs because four
identical prototype boards are connected using external cables
in this experiment, and unnecessary large inductance is present
even if the capacitor charging is not required. An integrated
inverter design can help to optimize the stray inductance distribution and solve this problem.
Fig. 22 shows the waveforms of load current Id and the
charging current of capacitor C1 . The peak value of IC1 is
21 A, whereas the peak value of Id is 9 A. The ratio between the
two peak values is 2.33, which is consistent with the estimation
result of (34).
Fig. 23 shows the zoomed-in view of the capacitor charging
current of C1 . It can be seen that the zero-current switching is
realized for all cycles.
Fig. 24 shows the efficiency curve of the proposed dc–ac
inverter with an input power from 100 to 1000 W. The efficiency
value is about 3% lower than the efficiency of the voltage
doubler. The main reason is that four extra switching devices
are involved in the inverter topology, which introduce more
conduction loss and control power loss. In addition, the peak
value of the charging current of the inverter is higher than
that of the voltage doubler, which generates higher conduction
loss.
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Ke Zou (S’09) received the B.S. and M.S. degrees
from Xi‘an Jiaotong University, Xi’an, China, in
2005 and 2008, respectively. He is currently working
toward the Ph.D. degree at The Ohio State University, Columbus.
His current research interests include switchedcapacitor dc/dc converters and dc/ac multilevel
inverters, battery models in high-frequency applications, and hardware-in-the-loop systems for power
electronics and power systems.
1609
Mark J. Scott (S’09) received the B.S. degree in
electrical and computer engineering from The Ohio
State University, Columbus, in 2005. He is currently
working toward the Ph.D. degree in electrical and
computer engineering at The Ohio State University.
He has worked as a Field Engineer installing
large industrial automated systems and as a Test
Engineer validating power electronics for automotive applications. His research interests include utilizing wide-band-gap devices in new and existing
power electronic topologies for renewable energy
applications.
Mr. Scott is the founding member of the IEEE Graduate Student Body at The
Ohio State University and a member of Tau Beta Pi.
Jin Wang (S’02–M’05) received the B.S. degree
from Xi’an Jiaotong University, Xi’an, China, in
1998, the M.S. degree from Wuhan University,
Wuhan, China, in 2001, and the Ph.D. degree from
Michigan State University, East Lansing, MI, in
2005, all in electrical engineering.
From September 2005 to August 2007, he worked
at the Ford Motor Company as a Core Power Electronics Engineer and contributed to the traction drive
design of the Ford Fusion Hybrid. Since September
2007, he has been an Assistant Professor in the Department of Electrical and Computer Engineering, The Ohio State University,
Columbus. His teaching position is cosponsored by American Electric Power,
Duke/Synergy, and FirstEnergy. He is the author of 40 peer-reviewed journal
and conference publications. His research interests include high-voltage and
high-power converter/inverters, integration of renewable energy sources, and
electrification of transportation.
Dr. Wang was the recipient of the IEEE Power Electronics Society Richard
M. Bass Young Engineer Award and the National Science Foundation’s
CAREER Award, both in 2011. Since March 2008, he has been an Associate
Editor for the IEEE T RANSACTIONS ON I NDUSTRY A PPLICATION.