IS61LP6432A
IS61LP6436A
ISSI
64K x 32, 64K x 36 SYNCHRONOUS
PIPELINED STATIC RAM
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Pentium™ or linear burst sequence control using
MODE input
• Three chip enables for simple depth expansion
and address pipelining
• Common data inputs and data outputs
• JEDEC 100-Pin TQFP package
• Power-down snooze mode
• Power Supply:
+3.3V VDD
+3.3V or 2.5V VDDQ (I/O)
• Lead-free available
®
SEPTEMBER 2005
DESCRIPTION
The ISSI IS61LP6432A/36A is a high-speed synchronous
static RAM designed to provide a burstable, high-performance memory for high speed networking and communication applications. The IS61LP6432A is organized as 64K
words by 32 bits and the IS61LP6436A is organized as 64K
words by 36 bits. Fabricated with ISSI's advanced CMOS
technology, the device integrates a 2-bit burst counter, highspeed SRAM core, and high-drive capability outputs into a
single monolithic circuit. All synchronous inputs pass
through registers controlled by a positive-edge-triggered
single clock input.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock input. Write cycles can be from
one to four bytes wide as controlled by the write control
inputs.
Separate byte enables allow individual bytes to be written.
BW1 controls DQa, BW2 controls DQb, BW3 controls
DQc, BW4 controls DQd, conditioned by BWE being
LOW. A LOW on GW input would cause all bytes to be
written.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally and controlled by the ADV (burst address
advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW.
Interleave burst is achieved when this pin is tied HIGH or
left floating.
FAST ACCESS TIME
Symbol
tKQ
tKC
Parameter
Clock Access Time
Cycle Time
Frequency
-166
3.5
6
166
-133
4
7.5
133
Units
ns
ns
MHz
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
09/02/05
1
ISSI
IS61LP6432A
IS61LP6436A
®
BLOCK DIAGRAM
MODE
Q0
CLK
CLK
A0'
A0
BINARY
COUNTER
CE
ADV
ADSC
ADSP
A15-A0
Q1
A1'
A1
64K x 32
64K x 36
MEMORY ARRAY
CLR
16
D
Q
14
16
ADDRESS
REGISTER
CE
CLK
x32/x36
GW
BWE
BW4
D
x32/x36
Q
DQd
BYTE WRITE
REGISTERS
CLK
BW3
D
DQc Q
BYTE WRITE
REGISTERS
CLK
D
BW2
Q
DQb
BYTE WRITE
REGISTERS
CLK
BW1
D
DQa Q
BYTE WRITE
REGISTERS
CLK
CE
CE2
CE2
4
D
Q
ENABLE
REGISTER
INPUT
REGISTERS
CLK
OUTPUT
REGISTERS
CLK
x32/x36
OE
DQ[31:0]
DQ[35:0]
CE
CLK
D
Q
ENABLE
DELAY
REGISTER
CLK
OE
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
09/02/05
ISSI
IS61LP6432A
IS61LP6436A
®
PIN CONFIGURATION
A6
A7
CE
CE2
BW4
BW3
BW2
BW1
CE2
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A8
A9
100-Pin TQFP
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
78
3
77
4
76
5
75
6
74
7
73
8
72
9
71
10
70
11
69
12
68
13
67
14
66
15
65
16
64
17
63
18
62
19
61
20
60
21
59
22
58
23
57
24
56
25
55
26
54
27
53
28
52
29
51
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DQPb
DQb8
DQb7
VDDQ
VSS
DQb6
DQb5
DQb4
DQb3
VSS
VDDQ
DQb2
DQb1
VSS
NC
VDD
ZZ
DQa8
DQa7
VDDQ
VSS
DQa6
DQa5
DQa4
DQa3
VSS
VDDQ
DQa2
DQa1
DQPa
MODE
A5
A4
A3
A2
A1
A0
NC
NC
VSS
VDD
NC
NC
A10
A11
A12
A13
A14
A15
NC
DQPc
DQc1
DQc2
VDDQ
VSS
DQc3
DQc4
DQc5
DQc6
VSS
VDDQ
DQc7
DQc8
NC
VDD
NC
VSS
DQd1
DQd2
VDDQ
VSS
DQd3
DQd4
DQd5
DQd6
VSS
VDDQ
DQd7
DQd8
DQPd
64K x 36
PIN DESCRIPTIONS
A0, A1
A2-A15
CLK
ADSP
ADSC
ADV
BW1-BW4
BWE
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
Synchronous Address Inputs
Synchronous Clock
Synchronous Processor Address
Status
Synchronous Controller Address
Status
Synchronous Burst Address Advance
Individual Byte Write Enable
Synchronous Byte Write Enable
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
09/02/05
GW
CE, CE2, CE2
OE
DQa-DQd
MODE
VDD
Vss
Synchronous Global Write Enable
Synchronous Chip Enable
Output Enable
Synchronous Data Input/Output
Burst Sequence Mode Selection
+3.3V Power Supply
Ground
VDDQ
ZZ
DQPa-DQPd
Isolated Output Buffer Supply: +3.3V/2.5V
Snooze Enable
Parity Data I/O
3
ISSI
IS61LP6432A
IS61LP6436A
®
PIN CONFIGURATION
A6
A7
CE
CE2
BW4
BW3
BW2
BW1
CE2
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A8
A9
100-Pin TQFP
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
DQb8
DQb7
VDDQ
VSS
DQb6
DQb5
DQb4
DQb3
VSS
VDDQ
DQb2
DQb1
VSS
NC
VDD
ZZ
DQa8
DQa7
VDDQ
VSS
DQa6
DQa5
DQa4
DQa3
VSS
VDDQ
DQa2
DQa1
NC
MODE
A5
A4
A3
A2
A1
A0
NC
NC
VSS
VDD
NC
NC
A10
A11
A12
A13
A14
A15
NC
NC
DQc1
DQc2
VDDQ
VSS
DQc3
DQc4
DQc5
DQc6
VSS
VDDQ
DQc7
DQc8
NC
VDD
NC
VSS
DQd1
DQd2
VDDQ
VSS
DQd3
DQd4
DQd5
DQd6
VSS
VDDQ
DQd7
DQd8
NC
64K x 32
PIN DESCRIPTIONS
A0, A1
A2-A15
CLK
ADSP
ADSC
ADV
BW1-BW4
BWE
4
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
Synchronous Address Inputs
Synchronous Clock
Synchronous Processor Address
Status
Synchronous Controller Address
Status
Synchronous Burst Address Advance
Individual Byte Write Enable
Synchronous Byte Write Enable
GW
CE, CE2, CE2
OE
DQa-DQd
MODE
VDD
Vss
VDDQ
ZZ
Synchronous Global Write Enable
Synchronous Chip Enable
Output Enable
Synchronous Data Input/Output
Burst Sequence Mode Selection
+3.3V Power Supply
Ground
Isolated Output Buffer Supply: +3.3V/2.5V
Snooze Enable
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
09/02/05
ISSI
IS61LP6432A
IS61LP6436A
®
TRUTH TABLE
Operation
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Address
Used
None
None
None
None
None
External
External
External
Next
Next
Next
Next
Next
Next
Current
Current
Current
Current
Current
Current
CE
H
L
L
X
X
L
L
L
X
X
H
H
X
H
X
X
H
H
X
H
CE2
X
X
L
X
L
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
CE2
X
H
X
H
X
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
ADSP ADSC
X
L
L
X
L
X
H
L
H
L
L
X
H
L
H
L
H
H
H
H
X
H
X
H
H
H
X
H
H
H
H
H
X
H
X
H
H
H
X
H
ADV WRITE
X
X
X
X
X
X
X
X
X
X
X
X
X
Read
X
Write
L
Read
L
Read
L
Read
L
Read
L
Write
L
Write
H
Read
H
Read
H
Read
H
Read
H
Write
H
Write
OE
X
X
X
X
X
X
X
X
L
H
L
H
X
X
L
H
L
H
X
X
DQ
High-Z
High-Z
High-Z
High-Z
High-Z
Q
Q
D
Q
High-Z
Q
High-Z
D
D
Q
High-Z
Q
High-Z
D
D
PARTIAL TRUTH TABLE
Function
Read
Read
Write Byte 1
Write All Bytes
Write All Bytes
GW
H
H
H
H
L
BWE
H
L
L
L
X
BW1
X
H
L
L
X
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
09/02/05
BW2
X
H
H
L
X
BW3
X
H
H
L
X
BW4
X
H
H
L
X
5
ISSI
IS61LP6432A
IS61LP6436A
®
INTERLEAVED BURST ADDRESS TABLE (MODE = VDD or No Connect)
External Address
A1 A0
00
1st Burst Address
A1 A0
01
2nd Burst Address
A1 A0
10
3rd Burst Address
A1 A0
11
01
10
11
00
11
10
11
00
01
10
01
00
LINEAR BURST ADDRESS TABLE (MODE = Vss)
0,0
A1', A0' = 1,1
0,1
1,0
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
TSTG
PD
IOUT
VIN, VOUT
VIN
VDD
Parameter
Storage Temperature
Power Dissipation
Output Current (per I/O)
Voltage Relative to Vss for I/O Pins
Voltage Relative to Vss for
for Address and Control Inputs
Voltage on VDD Supply Relative to Vss
Value
–55 to +150
1.6
100
–0.5 to VDDQ + 0.3
–0.5 to VDD + 0.5
Unit
°C
W
mA
V
V
–0.5 to 4.6
V
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. This device contains circuitry to protect the inputs against damage due to high static voltages
or electric fields; however, precautions may be taken to avoid application of any voltage higher
than maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
09/02/05
ISSI
IS61LP6432A
IS61LP6436A
®
OPERATING RANGE
Range
Ambient Temperature
VDD
VDDQ
0°C to +70°C
3.3V + 5%
3.3V + 5%
2.5V + 5%
–40°C to +85°C
3.3V + 5%
3.3V + 5%
2.5V + 5%
Commercial
Industrial
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
2.5V (I/O)
Min.
Max.
3.3V (I/O)
Min.
Max.
IOH = –4.0 mA (3.3V)
IOH = 1.0 mA (2.5V)
2.0
—
2.4
—
V
IOL = 8.0 mA (3.3V)
IOL = 1.0 mA (2.5V)
—
0.4
—
0.4
V
1.7
VDD + 0.3
2.0
VDD + 0.3
V
–0.3
0.7
–0.3
0.8
V
–5
5
–5
5
µA
–5
5
–5
5
µA
Symbol
Parameter
Test Conditions
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
ILI
Input Leakage Current
Vss ≤ VIN ≤ VDD
ILO
Output Leakage Current
Vss ≤ VOUT ≤ VDDQ, OE = VI
(1)
Unit
POWER SUPPLY CHARACTERISTICS (Over Operating Range)
Symbol
ICC
Parameter
AC Operating
Supply Current
ISB1
Standby Current
IZZ
Power-down Mode
Current
Test Conditions
Device Selected,
Com.
All Inputs = VIL or VIH
Ind.
OE = VIH, VDD = Max.
Cycle Time ≥ tKC min.
Device Deselected,
Com.
VDD = Max.,
Ind.
All Inputs = VIH or VIL
CLK Cycle Time ≥ tKC min.
ZZ = VDD
Com.
Clock Running
Ind.
All Inputs ≤ VSS + 0.2V
or ≥ VDD – 0.2V
-166
Max.
190
200
-133
Max.
180
190
Unit
mA
mA
70
80
70
80
mA
mA
35
40
35
40
mA
mA
Notes:
1. The MODE pin has an internal pullup. This pin may be a No Connect, tied to Vss, or tied to VDD.
2. The MODE pin should be tied to VDD or Vss. It exhibits ±10 µA maximum leakage current when tied to ≤ Vss + 0.2V
or ≥ VDD – 0.2V.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
09/02/05
7
ISSI
IS61LP6432A
IS61LP6436A
®
CAPACITANCE(1,2)
Symbol
Parameter
CIN
Input Capacitance
COUT
Input/Output Capacitance
Conditions
Max.
Unit
VIN = 0V
6
pF
VOUT = 0V
8
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 3.3V.
3.3V I/O AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0V to 3.0V
1ns
1.5V
See Figures 1 and 2
3.3V I/O OUTPUT LOAD EQUIVALENT
317 Ω
+3.3V
ZO = 50Ω
OUTPUT
OUTPUT
50Ω
351 Ω
5 pF
Including
jig and
scope
1.5V
Figure 1
8
Figure 2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
09/02/05
ISSI
IS61LP6432A
IS61LP6436A
®
2.5V I/O AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0V to 2.5V
1 ns
1.25V
See Figures 3 and 4
2.5V I/O OUTPUT LOAD EQUIVALENT
1,667 Ω
+2.5V
ZO = 50Ω
OUTPUT
OUTPUT
50Ω
1,538 Ω
5 pF
Including
jig and
scope
1.25V
Figure 3
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
09/02/05
Figure 4
9
ISSI
IS61LP6432A
IS61LP6436A
®
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-166
Symbol
fMAX(3)
tKC(3)
tKH
tKL(3)
tKQ(3)
tKQX(1)
tKQLZ(1,2)
tKQHZ(1,2)
tOEQ(3)
tOEQX(1)
tOELZ(1,2)
tOEHZ(1,2)
tAS(3)
tSS(3)
tWS(3)
tCES(3)
tAVS(3)
tAH(3)
tSH(3)
tWH(3)
tCEH(3)
tAVH(3)
Parameter
Clock Frequency
Cycle Time
Clock High Time
Clock Low Time
Clock Access Time
Clock High to Output Invalid
Clock High to Output Low-Z
Clock High to Output High-Z
Output Enable to Output Valid
Output Disable to Output Invalid
Output Enable to Output Low-Z
Output Disable to Output High-Z
Address Setup Time
Address Status Setup Time
Write Setup Time
Chip Enable Setup Time
Address Advance Setup Time
Address Hold Time
Address Status Hold Time
Write Hold Time
Chip Enable Hold Time
Address Advance Hold Time
Min.
—
6
2.4
2.4
—
3
0
1.5
—
0
0
2
2.1
1.5
1.5
1.5
1.5
1.0
0.5
0.5
0.5
0.5
-133
Max.
166
—
—
—
3.5
—
—
3.5
3.5
—
—
4.5
—
—
—
—
—
—
—
—
—
—
Min.
—
7.5
2.8
2.8
—
3
0
1.5
—
0
0
2
2.1
1.5
1.5
1.5
1.5
1.0
0.5
0.5
0.5
0.5
Max.
133
—
—
—
4
—
—
3.5
3.8
—
—
5
—
—
—
—
—
—
—
—
—
—
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.
3. Tested with load in Figure 1.
10
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
09/02/05
ISSI
IS61LP6432A
IS61LP6436A
®
READ/WRITE CYCLE TIMING
tKC
CLK
tSS
tSH
tKH
tKL
ADSP is blocked by CE inactive
ADSP
tSS
tSH
ADSC initiate read
ADSC
tAVH
tAVS
Suspend Burst
ADV
tAS
A15-A0
tAH
RD1
RD3
RD2
tWS
tWH
tWS
tWH
GW
BWE
BW4-BW1
tCES
tCEH
tCES
tCEH
tCES
tCEH
CE Masks ADSP
CE
Unselected with CE2
CE2 and CE2 only sampled with ADSP or ADSC
CE2
CE2
tOEHZ
tOEQ
OE
DATAOUT
tKQX
tOEQX
tOELZ
High-Z
1a
2a
2b
2c
2d
tKQLZ
3a
tKQHZ
tKQ
DATAIN
High-Z
Pipelined Read
Single Read
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
09/02/05
Burst Read
Unselected
11
ISSI
IS61LP6432A
IS61LP6436A
®
WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-166
Symbol
tKC(1)
Parameter
Cycle Time
Min.
6
Max.
—
tKH(1)
tKL(1)
tAS(1)
tSS(1)
tWS(1)
tDS(1)
tCES(1)
tAVS(1)
tAH(1)
tSH(1)
tDH(1)
tWH(1)
tCEH(1)
tAVH(1)
Clock High Time
Clock Low Time
Address Setup Time
Address Status Setup Time
Write Setup Time
Data In Setup Time
Chip Enable Setup Time
Address Advance Setup Time
Address Hold Time
Address Status Hold Time
Data In Hold Time
Write Hold Time
Chip Enable Hold Time
Address Advance Hold Time
2.4
2.4
2.1
1.5
1.5
1.5
1.5
1.5
1.0
0.5
1.0
0.5
0.5
0.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-133
Min.
Max.
7.5
—
2.8
2.8
2.1
1.5
1.5
1.5
1.5
1.5
1.0
0.5
1.0
0.5
0.5
0.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note:
1. Tested with load in Figure 1.
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
09/02/05
ISSI
IS61LP6432A
IS61LP6436A
®
WRITE CYCLE TIMING
tKC
CLK
tSS
tSH
tKH
tKL
ADSP is blocked by CE inactive
ADSP
ADSC initiate Write
ADSC
tAVH
ADV must be inactive for ADSP Write tAVS
ADV
tAS
A15-A0
tAH
WR1
WR3
WR2
tWS
tWH
tWS
tWH
tWS
tWH
GW
BWE
BW4-BW1
WR1
tCES
tCEH
tCES
tCEH
tCES
tCEH
tWS
tWH
WR2
WR3
CE Masks ADSP
CE
CE2 and CE2 only sampled with ADSP or ADSC
Unselected with CE2
CE2
CE2
OE
DATAOUT
High-Z
tDS
DATAIN
High-Z
Single Write
tDH
1a
BW4-BW1 only are applied to first cycle of WR2
2a
2b
Burst Write
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
09/02/05
2c
2d
3a
Write
Unselected
13
ISSI
IS61LP6432A
IS61LP6436A
®
SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-166
-133
Symbol
tKC(3)
Parameter
Cycle Time
Min.
6
Max.
—
Min.
7.5
Max.
—
Unit
ns
tKH(3)
tKL(3)
tKQ(3)
tKQX(1)
tKQLZ(1,2)
tKQHZ(1,2)
tOEQ(3)
tOEQX(1)
tOELZ(1,2)
tOEHZ(1,2)
tAS(3)
tSS(3)
tCES(3)
tAH(3)
tSH(3)
tCEH(3)
tZZS
tZZREC
Clock High Time
Clock Low Time
Clock Access Time
Clock High to Output Invalid
Clock High to Output Low-Z
Clock High to Output High-Z
Output Enable to Output Valid
Output Disable to Output Invalid
Output Enable to Output Low-Z
Output Disable to Output High-Z
Address Setup Time
Address Status Setup Time
Chip Enable Setup Time
Address Hold Time
Address Status Hold Time
Chip Enable Hold Time
ZZ Standby
ZZ Recovery
2.4
2.4
—
1.5
0
1.5
—
0
0
2
2.1
1.5
1.5
1.0
0.5
0.5
2
2
—
—
3.5
—
—
3.5
3.5
—
—
4.5
—
—
—
—
—
—
—
—
2.8
2.8
—
1.5
0
1.5
—
0
0
2
2.1
1.5
1.5
1.0
0.5
0.5
2
2
—
—
4
—
—
3.5
3.9
—
—
5.0
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cyc
cyc
Notes:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.
3. Tested with load in Figure 1.
14
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
09/02/05
ISSI
IS61LP6432A
IS61LP6436A
®
SNOOZE AND RECOVERY CYCLE TIMING
tKC
CLK
tSS
tSH
tAS
tAH
tKH
tKL
ADSP
ADSC
ADV
A15-A0
RD2
RD1
GW
BWE
BW4-BW1
tCES
tCEH
tCES
tCEH
tCES
tCEH
CE
CE2
CE2
tOEHZ
tOEQ
OE
tOEQX
tOELZ
DATAOUT
High-Z
1a
tKQLZ
tKQ
DATAIN
tKQX
tKQHZ
High-Z
tZZS
tZZREC
ZZ
Single Read
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
09/02/05
Snooze with Data Retention
Read
15
ISSI
IS61LP6432A
IS61LP6436A
®
ORDERING INFORMATION: IS61LP6432A
Commercial Range: 0°C to +70°C
Speed
133 MHz
Order Part Number
IS61LP6432A-133TQ
Package
TQFP
Industrial Range: –40°C to +85°C
Speed
133 MHz
133 MHz
Order Part Number
IS61LP6432A-133TQI
IS61LP6432A-133TQLI
Package
TQFP
TQFP, Lead-free
ORDERING INFORMATION: IS61LP6436A
Commercial Range: 0°C to +70°C
Speed
166 MHz
133 MHz
Order Part Number
IS61LP6436A-166TQ
IS61LP6436A-133TQ
Package
TQFP
TQFP
Industrial Range: –40°C to +85°C
Speed
166 MHz
166 MHz
133 MHz
133 MHz
16
Order Part Number
IS61LP6436A-166TQI
IS61LP6436A-166TQLI
IS61LP6436A-133TQI
IS61LP6436A-133TQLI
Package
TQFP
TQFP, Lead-free
TQFP
TQFP, Lead-free
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
09/02/05
ISSI
PACKAGING INFORMATION
TQFP (Thin Quad Flat Pack Package)
Package Code: TQ
D
D1
E
E1
N
L1
L
C
1
e
SEATING
PLANE
A2
A
b
A1
Thin Quad Flat Pack (TQ)
Inches
Millimeters
Min
Max
Min
Max
Millimeters
Symbol Min
Max
Ref. Std.
No. Leads (N)
100
A
—
1.60
—
0.063
A1
0.05 0.15
0.002 0.006
A2
1.35 1.45
0.053 0.057
b
0.22 0.38
0.009 0.015
D
21.90 22.10
0.862 0.870
D1
19.90 20.10
0.783 0.791
E
15.90 16.10
0.626 0.634
E1
13.90 14.10
0.547 0.555
e
0.65 BSC
0.026 BSC
L
0.45 0.75
0.018 0.030
L1
1.00 REF.
0.039 REF.
C
0o
7o
0o
7o
128
—
1.60
0.05 0.15
1.35 1.45
0.17 0.27
21.80 22.20
19.90 20.10
15.80 16.20
13.90 14.10
0.50 BSC
0.45 0.75
1.00 REF.
0o
7o
Integrated Silicon Solution, Inc. — 1-800-379-4774
PK13197LQ Rev. D 05/08/03
Inches
Min
Max
—
0.063
0.002 0.006
0.053 0.057
0.007 0.011
0.858 0.874
0.783 0.791
0.622 0.638
0.547 0.555
0.020 BSC
0.018 0.030
0.039 REF.
0o
7o
Notes:
1. All dimensioning and
tolerancing conforms to
ANSI Y14.5M-1982.
2. Dimensions D1 and E1 do
not include mold protrusions.
Allowable protrusion is 0.25
mm per side. D1 and E1 do
include mold mismatch and
are determined at datum
plane -H-.
3. Controlling dimension:
millimeters.
®