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EE 330 Lecture 33 • Cascaded Amplifiers • High-Gain Amplifiers • Current Source Biasing Review from Last Time Can use these equations only when small signal circuit is EXACTLY like that shown !! Review from Last Time Basic Amplifier Structures 1. Common Emitter/Common Source 2. Common Collector/Common Drain 3. Common Base/Common Gate 4. Common Emitter with RE/ Common Source with RS 5. Cascode (actually CE:CB or CS:CD cascade) 6. Darlington (special CE:CE or CS:CS cascade) The first 4 are most popular Review from Last Time Basic Amplifier Characteristics Summary VDD RC Vout CE/CS C B Vin E • • • • Large noninverting gain Low input impedance Moderate (or high) output impedance Used more as current amplifier or, in conjunction with CD/CS to form two-stage cascode VEE VDD • • • • C B CC/CD Vin Vout E RE VSS VDD RC Vout C CB/CG B VBB E Vin VDD RC CEwRE/ CSwRS Vout C B Vin E RE VEE Gain very close to +1 (little less) High input impedance for BJT (high for MOS) Low output impedance Widely used as a buffer • • • • Large noninverting gain Low input impedance Moderate (or high) output impedance Used more as current amplifier or, in conjunction with CD/CS to form two-stage cascode • • • • Reasonably accurate but somewhat small gain (resistor ratio) High input impedance Moderate output impedance Used when more accurate gain is required Cascaded Amplifier Analysis and Operation Adjacent Stage Coupling Only • Systematic Methods of Analysis/Design will be Developed One or more couplings of nonadjacent stages • • Less Common Analysis Generally Much More Involved, Use Basic Circuit Analysis Methods Cascaded Amplifier Analysis and Operation Adjacent Stage Coupling Only • Systematic Methods of Analysis/Design will be Developed Case 1: All stages Unilateral Case 2: One or more stages are not unilateral Repeat from earlier discussions on amplifiers Cascaded Amplifier Analysis and Operation Case 1: All stages Unilateral RS Vin Vout V1 RiX1 A v01V1 RoX1 V2 RL1 V3 RiX2 A v02V3 RoX2 V4 RL Vout RiX1 RL1//RiX2 RL AV A V01 A V02 Vin RiX1+RS R //R +R R +R L1 iX2 0X1 L 0X2 Accounts for all loading between stages ! Cascaded Amplifier Analysis and Operation Case 2: One or more stages are not unilateral Standard two-port cascade RS V11 Rin1 Two-Port Model 1 Ro1 V12 Rin2 A v0V1 Model 2 Two-Port Ro2 V21 Vin A v01V11 A v0r1V21 V13 Two-Port Model 3 Rin3 Ro3 V23 V OUT V22 A v0r2V22 A v02V12 RL A v03V13 A v0r3V23 Analysis by creating new two-port of entire amplifier quite tedious because of the reverse-gain elements Right-to-left nested Rinx,AvX approach RS Vin V1 V1 RinX-AVoX Model Rin1X V2 Av1XV1 • • • • RinX-AV Model Rin2X V3 Av2XV2 RinX-AV Model Rin3X Vout Av3XV3 Rinx includes effects of all loading AVX is the voltage ratio from input to output of a stage AVX’s include all loading Can not change any loading without recalculating everthing! RL=∞ Example: Determine the voltage gain of the following circuit in terms of the smallsignal parameters of the transistors. Assume Q1 and Q2 are operating in the Forward Active region and C1…C4 are large. VDD R1 R5 R3 VOUT C1 C3 Q1 RS R6 C4 Q1 R8 R2 R4 C2 VIN R7 VEE In this form, does not look “EXACTLY” like any of the basic amplifiers ! Example: VDD R1 R5 R3 VOUT C1 C3 Q1 RS R6 C4 Q1 R8 R2 R4 C2 VIN R7 VEE VA RS Vin VB Q1 Vout Q2 R6//R8 R1//R2 R3//R5 R7 Will calculate AV by determining the three ratios (not voltage gains of dependent source): AV = Vout Vout VB VA A V2 A V1A V0 Vin VB VA Vin Example: RS Vin VB VA Q1 Vout Q2 R6//R8 R1//R2 R3//R5 R7 CE with RE Rin2 A V2 = Vout VB Rin2 R6 //R8 R7 βR7 Example: Vout Q2 R6//R8 R7 One-Port Rin2 Rin2 βR7 Rin2 Example: RS VA VB Q1 R1//R2 Vin Vout Q2 Rin2 R3//R5 R6//R8 R7 CE with RE Rin2 Vout A V2 = VB Rin2 R6 //R8 R7 βR7 Example: VB VA RS Q1 R1//R2 Vin R3//R5 Rin2 RS Vin V A V1= B VA Rin1 gm1 R3 //R5 //Rin2 r 1 VA VB Q1 R1//R2 R3//R5//Rin2 CE Config Rin1 Example: VB Q1 Rin1 R3//R5//Rin2 Rin1 Example: RS Vin A V0 = VA Vin R1//R2 R1//R2 // Rin1 RS R1//R2 // Rin1 VA VB Q1 Rin1 R3//R5//Rin2 Example: RS VA Vout VB Q2 Q1 R6//R8 R1//R2 Vin R3//R5 R7 VEE Thus we have V V V V A V = out out B A Vin VB VA Vin where Vout R //R 6 8 VB R7 VB VA gm1 R3 //R5 //Rin2 VA Vin R1//R2 // Rin1 RS R1//R2 // Rin1 Rin2 βR7 Rin1 r 1 Example: VB VA RS Vout Q2 Q1 R6//R8 R1//R2 Vin R3//R5 R7 VEE Observation: By working from the output back to the input we were able to create a sequence of steps where the circuit at each step looked EXACTLY like one of the four basic amplifiers even though stages were not unilateral. Engineers often follow a design approach that uses a cascade of the basic amplifiers and that is why it is often possible to follow this approach to analysis. Will formalize what we have done (consider 3-stage unilateral cascade) Exactly same approach when not unilateral iB iB Stage 1 iB Stage 2 Stage 3 VOUT RB1 Vin VBE gπ gmVBE g0 RB2 VBE gπ gmVBE g0 RB3 VBE gπ gmVBE g0 RL Formalization of cascade circuit analysis working from load to input: (consider 3-stage unilateral cascade) V1 iB iB V2 Stage 1 V3 Stage 2 iB Stage 3 VOUT RB1 Vin VBE gmVBE gπ g0 RB2 VBE gmVBE gπ g0 VBE RB3 gmVBE gπ g0 RL VOUT V1 V2 V3 VOUT VIN VIN V1 V2 V3 V1 iB V2 Stage 1 iB V3 Stage 2 iB Stage 3 VOUT RB1 Vin VBE gπ gmVBE g0 RB2 VBE gπ gmVBE g0 RB3 VBE gπ gmVBE g0 RL Formalization of cascade circuit analysis working from load to input: (consider 3-stage unilateral cascade) V1 iB V2 Stage 1 iB V3 Stage 2 iB Stage 3 VOUT RB1 Vin VBE gmVBE gπ g0 RB2 VBE gmVBE gπ g0 RB3 VBE gπ gmVBE g0 RL Starting at output stage obtain: V3 iB VBE VOUT Stage 3 gπ gmVBE g0 RL VOUT V1 V2 V3 VOUT VIN VIN V1 V2 V3 Formalization of cascade circuit analysis working from load to input: (consider 3-stage unilateral cascade) V1 iB iB V2 Stage 1 V3 Stage 2 iB Stage 3 VOUT RB1 Vin VBE gmVBE gπ g0 VBE RB2 gmVBE gπ g0 RB3 VBE gπ gmVBE g0 RL Replace Stage 3 with RIN3 V1 iB V2 Stage 1 iB V3 Stage 2 Stage 3 RB1 Vin VBE gmVBE gπ g0 RB2 VBE gπ gmVBE g0 RB3 RIN3 Analyze Stage 2: V2 iB VBE V3 Stage 2 gπ gmVBE g0 RB3 RIN3 VOUT V1 V2 V3 VOUT VIN VIN V1 V2 V3 Formalization of cascade circuit analysis working from load to input: (consider 3-stage unilateral cascade) V1 iB V2 Stage 1 iB V3 Stage 2 iB Stage 3 VOUT RB1 Vin VBE gmVBE gπ g0 RB2 VBE gmVBE gπ g0 RB3 VBE gπ gmVBE g0 RL Replace Stage 2 with RIN2 V1 iB V2 Stage 1 RB1 Vin VBE gmVBE gπ g0 RB2 RIN2 Analyze Stage 1: V1 iB VBE V2 Stage 1 gπ gmVBE g0 RB2 RIN2 VOUT V V V V 1 2 3 OUT VIN VIN V1 V2 V3 Formalization of cascade circuit analysis working from load to input: (consider 3-stage unilateral cascade) V1 iB V2 Stage 1 iB V3 Stage 2 iB Stage 3 VOUT RB1 Vin VBE gπ gmVBE g0 RB2 VBE gmVBE gπ Replace Stage 1 with RIN1 V1 RB1 Vin RIN1 Analyze Stage 0: V V V V VOUT 1 2 3 OUT VIN VIN V1 V2 V3 g0 RB3 VBE gπ gmVBE g0 RL Formalization of cascade circuit analysis working (when stages are not unilateral) from load to input: RS Vin V1 V1 RinX-AVoX Model Rin1X V2 Av1XV1 RinX-AV Model Rin2X V3 Av2XV2 RinX-AV Model Rin3X Vout Av3XV3 RL=∞ Rinx includes effects of all loading AVX includes all loading (not typical dependent voltage source since dependent upon other circuit elements) Can not change any loading Analysis systematic and rather simple VOUT V1 V2 V3 VOUT V1 A V1X A V2X A V3X VIN VIN V1 V2 V3 VIN This was the approach used in analyzing the previous cascaded amplifier Example: RS Vin VA Vout VB Q2 Q1 R6//R8 R1//R2 R3//R5 R7 VEE Observation: By working from the output back to the input we were able to create a sequence of steps where the circuit at each step looked EXACTLY like one of the four basic amplifiers. Engineers often follow a design approach that uses a cascade of the basic amplifiers and that is why it is often possible to follow this approach to analysis. Two other methods could have been used to analyze this circuit What are they? Example: RS Vin VA Vout VB Q2 Q1 R6//R8 R1//R2 R3//R5 R7 VEE Two other methods could have been used to analyze this circuit 1. Create a two-port model of the two stages (for this example, since the first-stage is unilateral, it can be shown that ) RiX1 V RL1//RiX2 RL A V out A V01 A V02 Vin RiX1+RS RL1//RiX2 +R0X1 RL +R0X2 AV01 and AV02 are open-loop two-port gain and are different than what used above 1. Small signal model could have been put in for Q1 and Q2 Example: RS Vin VA Vout VB Q2 Q1 R6//R8 R1//R2 R3//R5 R7 VEE Two other methods could have been used to analyze this circuit 2. Put in small-signal model for Q1 and Q2 and solve resultant circuit (not too difficult for this specific example ) 1. Small signal model could have been put in for Q1 and Q2 Example: AV = Vout ? Vin Express in terms of small-signal parameters VDD M2 RC RB1 Q3 RB2 I1 -VSS Vout C M4 2 C1 M1 Vin RD RL Example: VDD M2 RC V1 RB1 Q3 C1 V2 M1 Vin RD Vout C M4 2 RL RB2 I1 -VSS Note: Even though the second stage has a resistor in the collector, the gain expressions developed for the common collector amplifier still apply V V V A V = out 2 1 V2 V1 Vin -g m1 -gm4 RD //RL 1 1 gm2 + β3 RB1//RB2 High-gain BJT amplifier -gm AV g0 GC VDD RC Vout C B Vin E VEE -gmRC To make the gain large, it appears that all one needs to do is make RC large ! AV -ICQRC -gmRC Vt But Vt is fixed at approx 25mV and for good signal swing, ICQRC<(VDD-VEE)/2 VDD VEE AV 2Vt If VDD-VEE=5V, 5V AV 100 2 25mV Gain is practically limited with this supply voltage to around 100 High-gain MOS amplifier -gm AV g0 GD VDD To make the gain large, it appears that all one needs to do is make RD large ! RD Vout G Vin D S VSS -gmRD AV -2IDQRD -gmRD VEB But VEB is practically limited to around 100mV and for good signal swing, IDQRD<(VDD-VSS)/2 VDD VSS AV VEB If VDD -VSS=5V and VEB=100mV, 5V AV 50 100mV Gain is practically limited with this supply voltage to around 100 Are these fundamental limits on the gain of the BJT and MOS Amplifiers? High-gain amplifier VDD iB VOUT IB VOUT VIN VIN VIN VBE VOU gπ gmVBE Q1 Q1 -gm AV 0 VEE This gain is very large ! Too good to be true ! Need better model of MOS device! High-gain amplifier VDD VOUT iB VOUT IB VOUT VIN VIN Q1 VIN Q1 VEE This gain is very large (but realistic) ! But how can we make a current source? VBE gπ gmVBE g0 -gm AV g0 AV -ICQ V - AF VtICQ /VAF Vt V A V - AF Vt 200V 8000 25mV High-gain amplifier VDD AV 8000 IB VOUT VIN Q1 VEE How can we build the ideal current source? What is the small-signal model of an actual current source? End of Lecture 33
