A Digitally Adjustable Resistor for Path Delay Characterization in HighFrequency Microprocessors
Martin Saint-Laurent
Intel Corporation
martin.saint-laurent@intel.com
Madhavan Swaminathan
Georgia Institute of Technology
madhavan.swaminathan@ece.gatech. edu
Abstract
Variable-Delay
Elements
Most high-frequency microprocessors 'have a clock
distribution network allowing the manipulation of the
clock edges to facilitate silicon debug and path delay
characterization. Typically, a particular edge of the clock
is skewed using a variable-delay element until a failure
occurs. This paper describes a digitally adjustable
resistor applied to the construction of such a variabledelay element. The operation of the digitally adjustable
resistor is explained. A strategy to choose the control bits
for the resistor is also discussed. The proposed variabledelay element can achieve a I-ps resolution over a 50-ps
range in a 180-nmfabrication technology.
Domain A
Fig. 1: Variable-delay element insertion.
technology. However, it requires an output multiplexer
and occupies a rather large area: about 1050 x 100 pm2.
This paper proposes a new digitally adjustable resistor.
The new circuit is a significant generalization of the ideas
presented in [2] because multiple transistor rows are
allowed and because the binary-weighted transistor width
constraint is removed: The result is a digitally adjustable
resistor that can be controlled with a considerably higher
resolution and over a wider range. The resistor is used
here to construct a compact variable-delay element that
does not require an output multiplexer. The circuit
topology of the proposed variable-delay element is
described in Section 11. The problem of choosing
appropriate values for the digital signal controlling the
resistor is discussed in Section 111. Finally, the simulated
performance of the circuit is presented and discussed in
Section IV for a 180-nm fabrication technology under
various process, voltage, and temperature conditions.
I. Introduction
Debugging a modem microprocessor is a challenging
task that requires the ability to control the clock precisely
and accurately. An effective strategy to identify and
characterize fiequency-limiting paths is presented in [ 11.
The strategy relies on a few variable-delay elements to
manipulate the clock. The variable-delay elements are
inserted at various points in the distribution network and
skew can be deliberately introduced between clock
domains, as shown in Fig. 1. Determining how much skew
a path can tolerate is a simple way to characterize its
timing margin.
A variable-delay element is easy to construct using a
digitally adjustable resistor. In [2] such a resistor is used
to control the impedance of a line driver. The resistor is
built using a row of transistors having binary-weighted
widths. The conductance of the row can be varied linearly,
but its resistance cannot. In [3], a skew compensation
circuit uses a variable-delay element constructed using
inverters and transmission gates. The transmission gates
are used to digitally connect or disconnect capacitors to
the output of the inverters. Unfortunately, the delay steps
are non-linear and remain relatively coarse. Another
interesting variable-delay element is proposed in [4].It
achieves a 26-ps resolution in a 350-nm fabrication
0-7803-6742-1/01/$10.00 02001 IEEE
11. Variable-Delay Element Circuit Topology
The variable-delay element proposed here is logically
equivalent to an inverter. As shown in Fig. 2, an n-bit
control signal sets the delay between the rising input
-
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Fig. 2: Variable-delay element.
61
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Fig. 3: General circuit topology.
transition and the falling output transition. The other
transition cannot be controlled by the proposed circuit.
However, two variable-delay elements in series would
permit the manipulation of both edges.
The general circuit topology of the variable-delay
inverter is shown in Fig. 3. The pull-down stack uses a
transistor array in which multiple rows are allowed. The
transistor array actually forms the digitally adjustable
resistor. Each bit of the control signal b[n - 1:0] is
connected to the gate of one transistor in the array. It is
reasonable to assume that all the control bits for a
particular row cannot be simultaneously zero to guarantee
that the output can switch. Every control bit combination
that blocks the pull-down stack is considered illegal. The
resistance of the pull-down stack is minimal when the n
transistors of the array are conducting. The maximum
resistance is achieved when, for each row, only the
smallest transistor conducts. In general, different control
bits produce different pull-down resistances. It is worth
noting that a relatively small number of bits can produce a
large number of resistance values (roughly 2”).
Although the digitally adjustable resistor described
here is implemented with a transistor array part of the
pull-down stack, its principles of operation would not
change for a pFET array. Using pFETs instead of nFETs
could perhaps be interesting to reduce the substrate noise
sensitivity of the circuit.
Legal Control Bit Combination
Fig. 4: Resistance distribution.
choosing which combinations to apply to the digitally
adjustable resistor then becomes a coding problem.
It is possible to carefully choose the transistors widths
such that the resistance values are fairly evenly distributed
between their minimum and maximum, like in Fig. 4. The
horizontal axis represents the control bits that must be
applied to produce a particular resistance value. Each set
of control bits determines which transistors are on and
which are off. In other words, each set of control bits
defines a particular combination of transistors in parallel
and in series.
A. Optimal Coding Under Nominal Conditions
With a large number of points densely scattered
between Rminand R,,, the resistance of the pull-down
stack can be varied in small steps. For any desired
resistance value between Rmi, and R,,, the existence of a
transistor combination producing nearly the same value is
guaranteed if the scattering density is high enough.
Mathematically, any desired pull-down resistance R(L)
lying between
and R,, can be very closely
approximated by R(L) if the control bits associated with
the resistance label L are chosen such that
<,
is minimized. Because the desired pull-down resistances
are arbitrary, they can follow the points of any linear or
non-linear function of L. The only restriction is that the
function must be bounded by Rminand R,,.
B..Optimal Coding to Tolerate Variations
111. Choosing the Control Bits
When a digitally adjustable resistor is subjected to
random variations, the resistance corresponding to a
particular control bit combination varies randomly from
its nominal value. However, some control bit
combinations are more robust than others. For instance, if
the channel length of every transistor is varied randomly,
the resistance corresponding to the control bit
combination labeled Lo may deviate from its nominal
value by 2%. The resistance corresponding to L , , another
As mentioned in Section 11, a transistor array can
produce a rather large number of resistance values, even
when n , its number of transistors, is relatively small. The
problem is deciding which control bit combinations to use
and which to avoid. For this, it is convenient to assign a
resistance label L to each combination of control bits
b[n - 1:0] that can be legally applied to the array. The
resistance label is just an integer. The problem of
62
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Fig. 5: Simulation schematic.
control bit combination, may change by 5%. In other
words, the resistance associated with Lo is more stable that
the resistance associated with 15,.
The control bits to apply to the digitally adjustable
resistor can be chosen to take advantage of the fact that
some combinations are more stable than others. Let L be
the label of a particular set of control bits. Also, let the
range of resistance-values corresponding to L be defined
by R,,,(L) and R,,(L) when the digitally adjustable
resistor is random perturbed. Mathematically, the best
control bit combination to approximate a desired pulldown resistance R(L) lying between Rmi, and R,,
minimizes:
max(lk,, ( L ) - R(L$
lLx
( L )- R(L)()
Equivalently, the optimal control bit combination
minimizes the worst-case resistance deviation from the
desired value.
IV. Simulation Results
Fig. 5 shows a variable-delay inverter having a 2-by-4
transistor array followed by a conventional inverter. The
input is x. The output of the variable-delay inverter is y
and the output of the conventional inverter is z. The
second inverter helps to protect the output of the variabledelay inverter. The purpose of the circuit is to adjust the
rising edge of z in small linear steps; varying the digitally
adjustable resistor linearly is not. In fact, by purposely
choosing non-linear steps for the digitally adjustable
resistor, some second-order delay variations due to the
second inverter can be compensated. In particular, the
digitally adjustable resistor is used here to compensate the
variable shape and transition time ofy.
Since the falling edge ofy is adjustable, so is the rising
edge of z. There are 256 possible control bit
combinations: 225 are legal and 31 are illegal. By
choosing 51 of the legal combinations as described in
0
'
'
'
'
'
'
100
200
300
400
500
600
'
700
800
'
1
900 1000
Time (ps)
Fig. 6: Simulated waveform.
Section IIL, the rising edge of z can be varied in 1-ps steps
over a 50-ps range. Fig. 6 shows the simulated waveform
associated with each combination. The delay steps are too
small to make the 51 rising edges distinctly visible.
However, the achievable delay points are clearly shown in
Fig. 7. The transition time of the rising edge is nearly
constant. Obviously, the falling edge is practically not
disturbed by the variable resistance of the pull-down
stack. When the rising edge moves, the position of the
falling edge remains within 0.5 ps of its average value.
A. Channel Length Variations
Fig. 7 also shows the robustness of the digitally
adjustable resistor against uncorrelated channel length
variations. The points represent the delays nominally
achievable. Each line represents a particular channel
length variation experiment. For each experiment, the
channel length of each transistor in the simulation
schematic is varied randomly. Each experiment is run
under nominal process, voltage, and temperature
conditions. It is interesting to observe that the random
variations tend to increase or decrease all the achievable
delays relatively uniformly. The delay steps are not
significantly affected in any of the random experiments
and remain at 1 ps.
B. Process, Voltage and Temperature Variations
Fig. 8 shows how the variable-delay inverter is affected
when the design comer changes. More precisely, the
supply voltage and the temperature are respectively varied
by 25% and 50 degrees at various process comers. Like
most circuits, the absolute speed of the variable-delay
element varies considerably. However, for the purpose of
comparing its behavior under the different design comers,
it is convenient to normalize its speed. Here, all the curves
63
130
1
70
-25
-20
-15
-10
-5
0
5
10
15
20
25
Resistance Label
-25
are normalized to their average. Regardless of the design
comer, the control bit combination labeled L = -25 is
always about 30% faster than the combination labeled
L = 0. The remarkable similarity of all the curves indicates
that changing the process, voltage, and temperature
conditions uniformly moves the delays points. In other
words, although the design comer has a considerable
influence on the absolute range of the variable-delay
inverter, it does not significantly affect its linearity.
Here, the control bits are only optimized for the
nominal design comer. However, a different set of control
bit combinations could be used for each design comer to
further improve the linearity of the circuit.
-15
-10
-5
0
5
10
15
20
25
Fig. 8: Effect of process, voltage, and
temperature variations on delay.
VI. References
.[ 11 U. Desai et al., “ItaniumTMProcessor Clock Design”,
International Symposium on Physical Design, 2000, pp.
94-98.
[2] T. J. Gabara, and S. C. Knauer, “Digitally Adjustable
Resistors in CMOS for High-Performance Applications”,
IEEE Journal of Solid-State Circuits, August 1992, pp.
1176-1 185.
[3] G. Geannopoulos, and X. Dai, “An Adaptive Digital
Deskewing Circuit for Clock Distribution Networks”,
IEEE International Solid-state Circuits Conference,
V. Conclusion
The new digitally adjustable resistor can be used to
construct a variable-delay element well suited to highfrequency microprocessor debugging. The variable-delay
element remains very linear under various process,
voltage, and temperature conditions. Its 1-ps resolution is
more than one order of magnitude better than the
resolution recently reported in [I] and is clearly sufficient
for path-delay characterization. Since the variable-delay
element is topologically similar to a static logic gate, its
area and power dissipation are relatively small. Moreover,
the circuit is reasonably robust against random channel
length variations.
Because of its high resolution, the digitally adjustable
resistor can be used to compensate a wide variety of nonlinear effects. The challenge is to carehlly choose which
control bit combinations to use and which combinations to
avoid. Digital compensation with an adjustable resistor is
a general circuit technique. It could potentially be used to
transform a wide variety of analog design problems into
easier-to-solve coding problems, like in [5].
-20
Resistance Label
Fig. 7: Effect of channel length variations on
delay.
‘
1998, pp. 400-401.
[4] H. Noda et al., “An On-Chip Clock-Adjusting Circuit
with Sub-100-ps Resolution for a High-speed DRAM
Interface”, IEEE Transactions on Circuits and Systems II:
Analog and Digital Signal Processing, August 2000, pp.
771-775.
[5] M. Saint-Laurent, and G . P. Muyshondt, “A Digitally
Controlled Oscillator Constructed Using Adjustable
Resistors”, IEEE Southwest Symposium on Mixed-Signal
Design, 2001.
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