High Speed Logic ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING High Speed Logic Circuits Dr. Lynn Fuller Webpage: http://people.rit.edu/lffeee Microelectronic Engineering Rochester Institute of Technology 82 Lomb Memorial Drive Rochester, NY 14623-5604 Tel (585) 475-2035 Email: Lynn.Fuller@rit.edu Department webpage: http://www.microe.rit.edu Rochester Institute of Technology Microelectronic Engineering © April 13, 2016 4-13-2016 High_Speed_Logic.ppt Dr. Lynn Fuller Page 1 High Speed Logic ADOBE PRESENTER This PowerPoint module has been published using Adobe Presenter. Please click on the Notes tab in the left panel to read the instructors comments for each slide. Manually advance the slide by clicking on the play arrow or pressing the page down key. Rochester Institute of Technology Microelectronic Engineering © April 13, 2016 Dr. Lynn Fuller Page 2 High Speed Logic OUTLINE Introduction Definitions MOSFET Internal Capacitances Inverter Rise and Fall times and Gate Delay Sizing Gates for Equal Rise and Fall Times Fan In and Fan Out Considerations Astable Multivibrator Two Phase Non-Overlapping Clocks Buffers Tristate I/O Pads with ESD protection Power Dissipation Energy and Delay References Homework Rochester Institute of Technology Microelectronic Engineering © April 13, 2016 Dr. Lynn Fuller Page 3 High Speed Logic INTRODUCTION High speed digital electronics depends on technology, design, and architecture among other things. Technology includes Strained Silicon, Silicon on Insulator, and Metal Gate, The transistors themselves can be made of different materials such as Silicon, Germanium, or Gallium Arsenide, or can be FINFETS instead of planner MOSFETS. Design includes transistor size, gate design, interconnect methodology and more. There are many design goals other than high speed such as low power, compact size, high yield (redundancy) and more. Everything is complicated by the 100’s of millions of transistors in todays complicated microchips. Because the mobility of carriers in n-type silicon is always higher than the mobility in p-type silicon the pull up transistor drive current (pmos) in an inverter will be less than the pull down transistor drive current (nmos) for transistors of equal length and width. By Rochester Institute of the Technology increasing the width drive current can be increased. Microelectronic Engineering © April 13, 2016 Dr. Lynn Fuller Page 4 High Speed Logic DEFINITIONS Rise Time – time for Vout of a gate to go from 10% to 90% Fall Time – time for Vout of a gate to go from 90% to 10% Propagation Delay or Gate Delay – (td) average time it takes for the output of a gate to get to switch using the 50% point of Vout high – Vout low. Also td = ½ (tdLTH + tdHTL) Low to High Delay (tdLTH) – time for output to go from low to the 50% point. High to Low Delay (tdHTL) – time for output to go from high to the 50% point. Rochester Institute of Technology Microelectronic Engineering © April 13, 2016 Dr. Lynn Fuller Page 5 High Speed Logic RISE TIME, FALL TIME AND PROPAGATION DELAY The system speed is determined by many factors but the basic parameter that determines the speed of the system is the individual gate propagation delay, td. The propagation delay is often used as a figure of merit to compare different technologies. For example in 1997 IBM reported their measured ring oscillator propagation delay of 9.5ps the fastest reported to date for CMOS at room temperature. The definition of propagation is the average of tdLTH and the tdHTL for the output of a gate (typically an inverter). Thus: td = ½(tLTH + tHTL) These times are so fast they are hard to measure so td is typically extracted from the measured period of a ring oscillator. A ring oscillator is an odd number of inverters (N) in series with the output connected back to the input, which will oscillate with period T. Rochester Institute of Technology thus: td = T/2N Microelectronic Engineering © April 13, 2016 Dr. Lynn Fuller Page 6 High Speed Logic MOSFET INTERNAL CAPACITANCES The internal capacitors for a MOSFET are associated with the gateto-channel, Gate overlap with the Drain, Source and substrate, and the source and drain junction capacitance to the substrate. The values of these capacitors depend on the length, L, width, W, Overlap in the length and width directions, Area and perimeter of the drain and source. Further, these capacitors change with voltage (with junction space charge width) and with the circuit topology including voltage gain Miller capacitance. The models are complex however this complexity is imbedded in the more advanced SPICE models used for simulation. We will attempt to get values for these capacitances, making simplifying approximations and assumptions. In addition we need to include the capacitance associated with the interconnectRochester wiring. Today’s complex chips have 1000’s of meters Institute of Technology Microelectronic Engineering of wiring. © April 13, 2016 Dr. Lynn Fuller Page 7 High Speed Logic SPICE LEVEL-1 MOSFET MODEL G CGSO CGDO S D COX p+ p+ ID RS RD CBD CBS CGBO B ID is a dependent current source. These C and R values are calculated separately in SPICE and multiplied by Ad, As, Pd, Ps, Nd, Ns, L, W etc. Rochester Institute of Technology Microelectronic Engineering for a given MOSFET. CGBO is small compared to the other capacitors © April 13, 2016 Dr. Lynn Fuller Page 8 High Speed Logic TRANSISTOR LAYOUT SHOWING CAPACITANCE W CGD = CGS = WxCGSO Gate Overlap with Drain Drain Gate Overlap with Substrate CGBO Gate Source Gate Fox Overlap L Source Junction Capacitance Area=AS Perimeter=PS CBS =CJ’ AS + CJSW’ PS Rochester Institute of Technology Microelectronic Engineering © April 13, 2016 Dr. Lynn Fuller Page 9 High Speed Logic MOSFET SHOWING CAPACITANCE Drain CD-Sub CG-D Substrate Gate CGin Cs-Sub CG-S Source Rochester Institute of Technology Microelectronic Engineering © April 13, 2016 Dr. Lynn Fuller Page 10 High Speed Logic SPICE LEVEL-1 PARAMETERS FOR MOSFET Cox’ = ro/XOX=3.9o/XOX where r = 3.9 for Oxide o = 8.85E-14 F/cm XOX= gate oxide thickness CGSO is the gate-to-source overlap capacitance (per meter channel width) CGSO = Cox’ (mask overlap in L direction + LD) F/m CGDO is the gate-to-drain overlap capacitance (per meter channel width) CGDO = Cox’ (mask overlap in L direction + LD) F/m CGBO is the gate-to-bulk overlap capacitance (per meter of overlap) CGBO = Cfield_oxide * mask overlap in W direction F/m Rochester Institute of Technology Cfield_oxide = ro/XFieldOX Microelectronic Engineering © April 13, 2016 Dr. Lynn Fuller Page 11 High Speed Logic SPICE LEVEL-1 PARAMETERS FOR MOSFET CBD zero bias bulk to drain junction capacitance CBD = CJ’ AD + CJSW’ PD CBS zero bias bulk to source junction capacitance CBS = CJ’ AS + CJSW’ PS CJ is the zero bias bulk junction bottom capacitance per square meter of junction area. CJ = ro / W where W is width of space charge layer. CJ = ro / [2 (ro/q) (o-VA) (1/Na + 1/Nd]-m where r = 11.7 F/cm for Silicon F/m2 o = PB = (KT/q) ln (NSUB/ni) + 0.56 m = junction grading coefficient = 0.5 MJ is the junction grading coefficient = 0.5 CJSW is the zero bias bulk junction sidewall capacitance per meter of junction perimeter. CJSW = CJ XJ Rochester Institute of Technology MJSW is the junction grading coefficient = 0.5 Microelectronic Engineering © April 13, 2016 Dr. Lynn Fuller Page 12 High Speed Logic SPICE LEVEL-1 PARAMETERS FOR MOSFET (cont.) For ~1um Technology L= 1um and W=4um Xox=150Å Xj=1um VDD=5 V AD=25um2 Field Fox=6500Å VTO =1 V PD=20um Nsub=3E16cm-3 Gate Fox Overlap (GFoxO)=2um N+D/S = 1E19 cm-3 Gate to Drain Overlap (LD)=0.1um Cox’= eoer/Xox=8.85e-14(F/cm)x3.9/150E-8cm = 2.30E-7 F/cm2 CGin=Cox’ LxW=2.30E-7(F/cm2)x1umx4um = 9.2 fF Cfield’= eoer/Fox = 8.85e-13(F/cm)x3.9/6500E-8cm=5.31E-9F/cm2 CG-Sub=Cfield’xLxGFoxO=2x5.31E-9x2umx1um=0.21fF CGDO=Cox’x LD=2 x 2.30E-7 x 0.1um=4.6e-12F/cm CGD=CGDOxW=4.6E-12 x 4um=1.8fF Cj’=eoer/Wsc=5.41E-8F/cm2 CJ=Cj’x AD=5.41E-8(F/cm2)x25um2=13.5fF CBD Rochester Institute of Technology Cjsw’=eoer Xj/Wsc=5.41E-12 F/cm Microelectronic Engineering CJ2=Cjsw’x PD = 5.41E-12 x 20um=10.8fF © April 13, 2016 Dr. Lynn Fuller Page 13 High Speed Logic MOSFET SHOWING CAPACITANCE Drain 24.3fF 1.8fF CD-Sub CG-D Substrate Gate 9.2fF CGin Cs-Sub CG-S 1.8fF 24.3fF Source CG = Institute CGinof+Technology CG-S + CG-D (1-Av) Rochester Microelectronic Engineering = 9.2fF + 1.8fF + 1.8fF x (1- -5) = ~22fF © April 13, 2016 Dr. Lynn Fuller Page 14 High Speed Logic SPICE LEVEL-1 MOSFET MODEL G CGSO CGDO S COX 1.8fF 9.2fF 1.8fF D p+ p+ ID RS CBS 24.3fF CGBO 24.3fF 0.21fF B RD CBD The capacitors in this model are a function of the voltages on the D, G, S and B terminals. CGDO is across a voltage gain in many circuits so that capacitor will appear to be larger do to Miller effect. CG = Institute CGinof+Technology CG-S + CG-D (1-Av) Rochester Microelectronic Engineering = 9.2fF + 1.8fF + 1.8fF x (1- -5) = ~22fF © April 13, 2016 Dr. Lynn Fuller Page 15 High Speed Logic GATE TO DRAIN OVERLAP, JUNCTION CAPACITANCE Since the Drain and Source Junction Capacitance is large we want to keep the area of the Drain and Source as small as we can. The doping concentration on both sides of the junction determine the space charge layer width and ultimately the junction capacitance. We can minimize that by careful well design. Today’s wells are shallow and are not uniformly doped. Retrograde wells provide higher doping near but slightly below the surface to reduce punch through. The deeper parts of the drain and source contact area are to provide robust contacts. If these intersect the wells where the wells are lighter doped the junction capacitance will be lower. The Gate to Drain overlap capacitance is multiplied by the Miller effect so it is one of the larger capacitances. To reduce this overlap the Poly is oxidized after being etched (Poly ReOx) before the Drain and Source is ion implanted. This reduces the overlap because the ion implant of the D/S is placed further away from the gate. Rochester Institute of Technology Microelectronic Engineering © April 13, 2016 Dr. Lynn Fuller Page 16 High Speed Logic GATE TO DRAIN OVERLAP, JUNCTION CAPACITANCE GATE DRAIN SOURCE p+ p+ WELL The Gate to Drain overlap capacitance is reduced if the Poly is oxidized before the Drain and Source is ion implanted. Rochester Institute of Technology Microelectronic Engineering © April 13, 2016 Dr. Lynn Fuller Page 17 High Speed Logic CMOS INVERTER SHOWING CAPACITANCE During switching one transistor is off while the other is in saturation. The self capacitance is the capacitance connected to the output. One CD-sub and the overlap capacitance from gate to drain for each transistor. The capacitance from gate to drain is a Miller capacitance and is Cm’=CD-sub VIN In this example: Cself = 2x(24.3fF + 1.8fF) Cself=2x25.2fF=50.4fF CG is everything connected to Vin Including miller effect CG=25.6fF VDD 1.8fF CG-S CD-Sub 24.3fF 9.2fF CGin C G-D 1.8fF VOUT 1.8fF CG-D 24.3fF CD-Sub 9.2fF CGin CG-S 1.8fF Rochester Institute of Technology Microelectronic Engineering © April 13, 2016 Dr. Lynn Fuller Page 18 High Speed Logic INTERNAL CAPACITANCE CALCULATION All the internal capacitances can be calculated from the equation, C=or Area/d, where d is the oxide thickness or width of the space charge layer. This spreadsheet does the calculations for the capacitors shown on the previous page. The total internal capacitance for the inverter with this technology is ~1.15pF Rochester Institute of Technology Microelectronic Engineering © April 13, 2016 ~1.15pF Dr. Lynn Fuller Page 19 High Speed Logic RING OSCILLATOR, td, THEORY Seven stage ring oscillator, N=7 with two output buffers td = T / 2 N td = gate delay N = number of stages T = period of oscillation Buffer Vout T = period of oscillation Rochester Institute of Technology Microelectronic Engineering © April 13, 2016 Dr. Lynn Fuller Page 20 Vout High Speed Logic MEASURED RING OSCILLATOR OUTPUT RIT 2µm CMOS Ring Oscillator 73 Stage Ring at 5V td = 104.8ns / 2(73) = 0.718 ns Rochester Institute of Technology Microelectronic Engineering © April 13, 2016 Rob Saxer 2005 Dr. Lynn Fuller Page 21 High Speed Logic MOSFETS IN THE INVERTER OF 73 RING OSCILLATOR nmosfet pmosfet 73 Stage Ring Oscillator Rochester Institute of Technology Microelectronic Engineering © April 13, 2016 Dr. Lynn Fuller Page 22 High Speed Logic FIND DIMENSIONS OF THE TRANSISTORS 73 Stage NMOS PMOS L 2u 2u W 12u 30u AD 12ux12u=144p 12ux30u=360p AS 12ux12u=144p 12ux30u=360p PD 2x(12u+12u)=48u 2x(12u+30u)=84u PS 2x(12u+12u)=48u 2x(12u+30u)=84u NRS 1 0.3 NRD 1 0.3 Use Ctrl Click on all NMOS on OrCad Schematic Use CtrlInstitute Click on all PMOS on OrCad Schematic Rochester of Technology Microelectronic Engineering Then Enter Dimensions © April 13, 2016 Dr. Lynn Fuller Page 23 High Speed Logic SPICE MODELS FOR MOSFETS *4-4-2013 LTSPICE uses Level=8 *For RIT Sub-CMOS 150 process with L=2u .MODEL RITSUBN8 NMOS (LEVEL=8 +VERSION=3.1 CAPMOD=2 MOBMOD=1 +TOX=1.5E-8 XJ=1.84E-7 NCH=1.45E17 NSUB=5.33E16 XT=8.66E-8 +VTH0=1.0 U0= 600 WINT=2.0E-7 LINT=1E-7 +NGATE=5E20 RSH=1082 JS=3.23E-8 JSW=3.23E-8 CJ=6.8E-4 MJ=0.5 PB=0.95 +CJSW=1.26E-10 MJSW=0.5 PBSW=0.95 PCLM=5 +CGSO=3.4E-10 CGDO=3.4E-10 CGBO=5.75E-10) * *4-4-2013 LTSPICE uses Level=8 *For RIT Sub-CMOS 150 process with L=2u .MODEL RITSUBP8 PMOS (LEVEL=8 +VERSION=3.1 CAPMOD=2 MOBMOD=1 +TOX=1.5E-8 XJ=2.26E-7 NCH=7.12E16 NSUB=3.16E16 XT=8.66E-8 +VTH0=-1.0 U0= 376.72 WINT=2.0E-7 LINT=2.26E-7 +NGATE=5E20 RSH=1347 JS=3.51E-8 JSW=3.51E-8 CJ=5.28E-4 MJ=0.5 PB=0.94 +CJSW=1.19E-10 MJSW=0.5 PBSW=0.94 +CGSO=4.5E-10 CGDO=4.5E-10 CGBO=5.75E-10) Rochester Institute of Technology Microelectronic Engineering © April 13, 2016 Dr. Lynn Fuller Page 24 High Speed Logic SIMULATED OUTPUT AT 5 VOLTS Three Stage Ring Oscillator with Transistor Parameters for 73 Stage Ring Oscillator and Supply of 5 volts Rochester Institute of Technology Measured td =Engineering 0.718 nsec @ 5 V Microelectronic © April 13, 2016 td = T / 2N = 5.5nsec / 2 / 3 td = 0.92 nsec Dr. Lynn Fuller Page 25 High Speed Logic CONCLUSION Since the measured and the simulated gate delays, td are close to correct, then the SPICE model must be close to correct. The inverter gate delay depends on the values of the internal capacitors and resistances of the transistor. Specifically: RS, RS, RSH CGSO, CGDO, CGBO CJ, CJSW These are combined with the transistors L, W Length and Width AS,AD Area of the Source/Drain PS,PD Perimeter of the Source/Drain NRS,NRD Number of squares Contact to Channel Rochester Institute of Technology Microelectronic Engineering © April 13, 2016 Dr. Lynn Fuller Page 26 High Speed Logic GATE DELAY FROM SPICE Equal L and W tdLTH = 441ps tdHTL = 328ps of Technology GateRochester delayInstitute is the time to get to Microelectronic Engineering 50% of the final value. © April 13, 2016 Dr. Lynn Fuller Page 27 High Speed Logic GATE DELAY Equal L and W Include parameters Rochester Institute Technology Gate delay isofthe time to get to Microelectronic Engineering 50% of the final value. © April 13, 2016 Dr. Lynn Fuller tdLTH = 825ps tdHTL = 599ps Page 28 High Speed Logic INVERTER MODEL FOR LTH AND HTL TRANSISTION +V +100uA ReqP PMOS NMOS Ipmos -125uA Cin Inmos ReqN ReqN = ~ Vave/Iave = 2.5/125uA = 20K ohms ReqP = ~ Vave/Iave = 2.5/100uA = 25K ohms Rochester Institute of Technology Microelectronic Engineering © April 13, 2016 Gate delay is the time to get to 50% of the final value. Dr. Lynn Fuller Page 29 High Speed Logic INVERTER RISE TIME AND FALL TIME ReqN = ~ Vave/Iave = 2.5/125uA = 20K ohms ReqP = ~ Vave/Iave = 2.5/100uA = 25K ohms RN = 1/(q µn Dose) x Lnmos/Wnmos RP = 1/(q µp Dose) x Lpmos/Wpmos Rise/Fall time is defined as the time for Vout to go from10% to 90%. For rise time equal to fall time the RC time constants are equal RN Cin = RP Cin Lnmos/(Wnmos µn) = Lpmos/(Wpmos µp) µp / µn = (Lpmos/Wpmos) / (Lnmos/Wnmos) Often Lpmos = Lnmos Finally µp / µn = (Wnmos/Wpmos) Wpmos = Wnmos (µn/µp) Rochester Institute of Technology Microelectronic Engineering © April 13, 2016 Dr. Lynn Fuller Page 30 High Speed Logic electrons 10 ^1 8 10 ^1 9 10 ^2 0 holes 10 ^1 6 10 ^1 7 1600 1400 1200 1000 800 600 400 200 0 10 ^1 3 10 ^1 4 10 ^1 5 Mobility (cm2/ V sec) MOBILITY Electron and hole mobilities Arsenic in silicon at 300 K as Boron functions of the total dopant Phosphorus concentration (N). The values plotted are the results of the curve fitting measurements from several sources. The mobility curves can be generated using the equation below with the parameters shown: Total Impurity Concentration (cm-3) (µmax-µmin) µ(N) = µ mi+ {1 + (N/Nref)} See Dr. Fuller’s Mobility Calculator From Muller and Kamins, 3rd Ed., pg 33 Rochester Institute of Technology Microelectronic Engineering © April 13, 2016 Parameter µmin µmax Nref Dr. Lynn Fuller Arsenic 52.2 1417 9.68X10^16 0.680 Page 31 Phosphorous 68.5 1414 9.20X10^16 0.711 Boron 44.9 470.5 2.23X10^17 0.719 High Speed Logic RISE TIME EQUALS FALL TIME Wpmos = 1.5 x Wnmos Gate delay isofthe time to get to Rochester Institute Technology Microelectronic Engineering 50% of the final value. © April 13, 2016 Dr. Lynn Fuller tdLTH = 526ps tdHTL = 663ps Page 32 High Speed Logic RISE TIME EQUALS FALL TIME Wpmos = 1.25 x Wnmos Rochester Institute Technology Gate delay is ofthe time to get to Microelectronic Engineering 50% of the final value. © April 13, 2016 Dr. Lynn Fuller tdLTH = 604ps tdHTL = 652ps Page 33 High Speed Logic LOGIC GATE RISE TIME AND FALL TIME The inverter rise time is determined by the channel resistance and the capacitance to be charged or discharged. +V ReqP = 25K L/W For L=2um and W=3um PMOS NMOS RC=25K/1.5 x 41fF = 683ps Ipmos Cself Inmos 19fF ReqN= 20K L/W Cwire zerofF CG 22fF Rochester Institute of Technology Microelectronic Engineering © April 13, 2016 Dr. Lynn Fuller Page 34 High Speed Logic LOGIC GATE RISE TIME AND FALL TIME The inverter rise time is determined by PMOS and NMOS current charging or discharging output capacitance. Q = CV +V For L=2um I = Q/t = CV/t W= 2.5um I = 125uA t = CV/I t = 41fF 2.5/125uA Ipmos PMOS C total= 41fF = 820ns NMOS For L=2um W= 2um Inmos Cself Cwire CG I = 125uA 19fF zerofF 22fF Rochester Institute of Technology Microelectronic Engineering © April 13, 2016 Dr. Lynn Fuller Page 35 High Speed Logic CAPACITANCE FOR EXAMPLE ON PREVIOUS PAGE Rochester Institute of Technology Microelectronic Engineering © April 13, 2016 Dr. Lynn Fuller Page 36 High Speed Logic WIRE RESISTANCE AND CAPACITANCE, LOW K, CU The wiring is typically aluminum or copper. The resistivity of aluminum is 26.5 nohm-cm and copper is 17.1 nohm-cm thus the wire will be lower resistance if copper. Rochester Institute of Technology Microelectronic Engineering © April 13, 2016 Dr. Lynn Fuller Page 37 High Speed Logic MULTILAYER METAL, W PLUGS, CMP 8 Layers Metal Rochester Institute of Technology Microelectronic Engineering © April 13, 2016 Dr. Lynn Fuller Page 38 High Speed Logic LOW-K FOR INTERCONNECT Rochester Institute of Technology Microelectronic Engineering © April 13, 2016 Dr. Lynn Fuller Page 39 High Speed Logic CMOS INVERTER DESIGN The design guideline is that the inverter should have the same current drive when Vout is switching low to high as high to low. Because the mobility of electrons is ~1.5 times higher than mobility for holes we make the PMOS 1.5 times wider. Typically L’s are the same. (W/L)pullup = ~ 1.5 (W/L)pulldown based on mobility only Vin Vout Pull up 1.5µW/L ID = µW Cox’ (Vg-Vt)2 2L +V I low to high Vout Vin C Load Pull down µW/L Rochester Institute of Technology Microelectronic Engineering CMOS © April 13, 2016 Dr. Lynn Fuller Page 40 High Speed Logic CMOS NOR AND NAND The design guideline for other logic gates is to provide the same current drive as the inverter. For the NOR gate we can go from high to low by starting with both inputs at zero and then making either input high or both high. The worst case condition is making only one input high. For that condition we want the same current drive as the inverter. Thus the width of the NMOS should be W. If both the inputs were switching high at the same time the current would be twice as much (that’s okay) For a low to high transition the current goes through two PMOS in series. The equivalent L for the series combination is 2L. If the width for each transistor was 3W the combined value is 3W/2L which is 1.5W/L as desired for equal drive current as the inverter. VA VB NOR NAND VA VB Vout +V 3W 0 0 1 1 0 1 0 1 1 0 0 0 1 1 1 0 VA VB +V 1.5W 1.5W 3W VA NOR WRochester Institute of W Technology VB VAMicroelectronic Engineering © April 13, 2016 2W NAND VB 2W Dr. Lynn Fuller Page 41 Vout High Speed Logic SIZING AND TIMING FOR THREE-INPUT NAND To achieve equal rise time and fall time (and make these times approximately equal to the simple inverter rise time and fall time). The transistors length and width can be calculated. In the simple inverter the nmos W/L is the smallest values for that technology. The pmos is 1.5 times wider to give equal drive current. For a more complex gate there will be transistors in series and parallel and those combinations need to be considered when trying to achieve rise and fall times equivalent to the simple inverter. For example: +V M1, M2 and M3 have a combined length of 3L So the combined width should be 3W to give 1.5W/L drive current equivalent to the nmos in the simple inverter. M1,M2,M3 nmos = 3W/L The worst case condition for low to high transition is only one input going low. So the width of the PMOS should be 1.5W. (when two or moreRochester inputs are going low at the same Institute of Technology Microelectronic Engineering time there will be more current (that is okay) © April 13, 2016 Dr. Lynn Fuller VA 1.5W/L 1.5W/L VOUT M1 3W/L VB M2 3W/L VC M3 3W/L Page 42 High Speed Logic FAN IN AND FAN OUT CONSIDERATIONS Fan in refers to the number of inputs to a gate. It is common to have up to 8 inputs. In CMOS this implies that there are 8 transistors in parallel and 8 transistors in series. The 8 in parallel is not necessarily a problem but the 8 in series is because of the body effect on the threshold voltage of some of the transistors if they are all in the same well (at Vss or Vdd for p-well or n-well respectively) The solution to this problem is to use a Pseudo CMOS logic gate where the series transistors are replaced by a single transistor with the gate wired to VDD or Ground for NMOS or PMOS respectively. This transistor is always on. Fan-In = 6 Rochester Institute of Technology Microelectronic Engineering © April 13, 2016 Dr. Lynn Fuller Page 43 High Speed Logic FAN IN AND FAN OUT CONSIDERATIONS What is the correct sizing for the transistors in this gate? Fan-In = 6 1.5W W Rochester Institute of Technology Microelectronic Engineering © April 13, 2016 Dr. Lynn Fuller Page 44 High Speed Logic FAN OUT GATE CAPACITANCE Fan out refers to the number of gates connected to the output of a gate. Each gate adds more capacitance to be charged or discharged during switching which has implications on rise time, fall time and gate delay. The size (W and L) of the MOSFETS in the gate, G1, can be set to keep the gate delay small. CG = CGin + CG-S + CG-D (1-Av) = 23fF + 2.3fF + 2.3fF x (1- -5) = ~25fF CG G1 Fan-Out = 6 Cfan-out = Fan-Out x (CG) = 6 x 25fF = 150fF CG CG CG CG Rochester Institute of Technology Microelectronic Engineering © April 13, 2016 CG Dr. Lynn Fuller Page 45 High Speed Logic MONO STABLE MULTIVIBRATOR This circuit will give a pulse at Vout whose width depends on RC time constant. VDD = 5 V R Vtrigger 1 2 V2 3 VDD V3 27 kΩ C 0.01 F I VC 1 s 0 Vout t Start with Vtrigger=0 and Vout=0 In steady state I = 0 so voltage across R = 0, Vc = 5 When Vtrigger goes high V2 goes high and V3 goes low, V across C cannot change so Vc also goes low but will charge up toward Vc=5 with RC time constant When Vc get up to Vs (switching voltage for gate 2 then V2 switches to low Institute Technologyeventually Vc=5 in steady state and V3 Rochester and Vc goof high, Microelectronic Engineering © April 13, 2016 Dr. Lynn Fuller Page 46 High Speed Logic TWO PHASE NON OVERLAPPING CLOCK Synchronous circuits that use the two phase non overlapping clock can separate input quantities from output quantities used to calculate the results in feedback systems such as the finite state machine. 1 2 Rochester Institute of Technology Microelectronic Engineering © April 13, 2016 Dr. Lynn Fuller Page 47 High Speed Logic SWITCHED CAPACITOR VOLTAGE DOUBLER 2 C1 1 Vdd 1 2 1 CLoad RLoad C1 1 2 Another example for two phase non overlapping clocks Rochester Institute of Technology Microelectronic Engineering © April 13, 2016 Dr. Lynn Fuller Page 48 High Speed Logic TWO-PHASE CLOCK GENERATORS A B C 0 0 1 1 0 1 0 1 1 0 0 0 R CLOCK t2 Q 1 t1 CLOCKBAR S t3 2 R S Q 0 0 1 1 0 1 0 1 Qn-1 1 0 CLOCK CLOCK BAR t1 1 t2 2 t1 t3 t3 Rochester Institute of Technology Microelectronic Engineering © April 13, 2016 = Dr. Lynn Fuller Page 49 INDETERMINATE High Speed Logic TRANSISTOR LEVEL SCHEMATIC OF 2 PHASE CLOCK +V 1 Layout 2 Clock +V Rochester Institute of Technology Microelectronic Engineering © April 13, 2016 Dr. Lynn Fuller Page 50 High Speed Logic TWO PHASE NON OVERLAPPING CLOCK Clock 1 2 Rochester Institute of Technology Microelectronic Engineering © April 13, 2016 Dr. Lynn Fuller Page 51 High Speed Logic CMOS TWO PHASE NON-OVERLAPPING CLOCK Rochester Institute of Technology Microelectronic Engineering © April 13, 2016 Dr. Lynn Fuller Page 52 High Speed Logic CMOS TWO PHASE NON-OVERLAPPING CLOCK Rochester Institute of Technology Microelectronic Engineering © April 13, 2016 Dr. Lynn Fuller Page 53 High Speed Logic SIMULATION NON-OVERLAPPING CLOCK + BUFFERS R CLOCK t2 1 BUFFERS t1 CLOCKBAR S t3 2 Rochester Institute of Technology Microelectronic Engineering © April 13, 2016 Dr. Lynn Fuller Page 54 High Speed Logic SIMULATION NON-OVERLAPPING CLOCK + BUFFERS t2 R CLOCK 1 BUFFERS t1 CLOCKBAR t3 S 2 0.1pF Loads Rochester Institute of Technology Microelectronic Engineering © April 13, 2016 Dr. Lynn Fuller Page 55 High Speed Logic SIMULATION NON-OVERLAPPING CLOCK + BUFFERS t2 R CLOCK 1 BUFFERS t1 CLOCKBAR t3 S 2 5pF Loads 10pF Loads Rochester Institute of Technology Microelectronic Engineering © April 13, 2016 Dr. Lynn Fuller Page 56 High Speed Logic SIMULATION NON-OVERLAPPING CLOCK + BUFFERS R CLOCK t2 1 BUFFERS t1 CLOCKBAR S 2 t3 4xL 16xL Rochester Institute of Technology Microelectronic Engineering © April 13, 2016 Dr. Lynn Fuller Page 57 High Speed Logic SIMULATION NON-OVERLAPPING CLOCK + BUFFERS t2 R CLOCK 1 BUFFERS t1 CLOCKBAR t3 S 2 10pF Loads Rochester Institute of Technology Microelectronic Engineering © April 13, 2016 Dr. Lynn Fuller Page 58 High Speed Logic CMOS TRISTATE INPUT OUTPUT PAD The Input/Output/Tristate Pad is the interface between the chip and the rest of the system. The pad is typically connected via a printed circuit board (PCB) to other chips, other PCB’s, and other devices. If an oscilloscope probe is connected to a chip it represents a large capacitive load (~10pF) in parallel with a 1MEG or 10MEG resistor. If the chip is connected in parallel with other chips (as is done in memory) via a data bus it represents a large capacitive load to the chip. In the case of a data bus the pad could be for an input or an output signal or high impedance (thus Tri State) Also, these pads are subject to possible electrostatic discharge (ESD) as connections are made to the pads. Rochester Institute of Technology Microelectronic Engineering © April 13, 2016 Dr. Lynn Fuller Page 59 High Speed Logic TRISTATE I/O PAD WITH ESD PROTECTION - SCHEMATIC Vdd l/w=5/40 M3 l/w=5/40 M5 M6 M11 l/w=5/2000 l/w=5/20 M4 Data D I/O l/w=5/20 Tristate Logic Vdd Vdd M7 Vdd l/w=5/30 150 l/w=5/40 l/w=5/46 M9 M1 l/w=5/40 M2 M10 M13 Enable EN l/w=5/20 M8 l/w=5/20 M14 l/w=5/1000 l/w=5/28 ESD Protection Rochester Institute of Technology Microelectronic Engineering M4 IN Vin M12 l/w=5/20 © April 13, 2016 Pad Dr. Lynn Fuller Page 60 High Speed Logic TRISTATE I/O PAD WITH ESD PROTECTION - SCHEMATIC If the enable EN is low M8 will be on making M11 off. If the enable EN is low M10 will be on making M12 off. Data can be low or high and if EN is low both M11 and M12 are off. This is the high impedance state. If EN is high M6 will be on and if Data is high then M4 will be on making M11 on providing a high output to the I/O pad. If EN is high M9 will be on and if Data is low then M7 will also be on making M12 on providing a low output to the I/O pad. Transistors M13 and M14 will normally be off unless the pad voltage is at large negative or positive voltages. For large negative voltages current can flow from ground through M14 and the resistor. For large positive voltages (more than Vdd) current can flow through the resistor and M13 to Vdd. The voltage IN will always be between Vdd Rochester Institute of Technology +0.7 and -0.7 Microelectronic volts. Engineering © April 13, 2016 Dr. Lynn Fuller Page 61 High Speed Logic TRISTATE I/O PAD WITH ESD PROTECTION - LAYOUT Resistor Rochester Institute of Technology Microelectronic Engineering © April 13, 2016 Dr. Lynn Fuller Page 62 High Speed Logic ELECTROSTATIC DISCHARGE Electrostatic Discharge (ESD) Dielectric Breakdown Strength of SiO2 is approximately 8 E6 V/cm, thus a 250 Å gate oxide will not sustain voltages in excess of 20 V Triboelectricity (electricity produced by rubbing two materials together) can generate high voltages. A person walking across a room can generate 20,000 Volts and if discharged into an IC can cause immediate failure or damage that will reduce operating life. Even with proper handling several hundred volts can be applied to the IC. Therefore, protection circuitry is needed to provide a safe path for dischargeRochester of this electricity. Institute of Technology Microelectronic Engineering © April 13, 2016 Dr. Lynn Fuller Page 63 High Speed Logic ESD DAMAGE Rochester Institute of Technology Microelectronic Engineering © April 13, 2016 Dr. Lynn Fuller Page 64 High Speed Logic ELECTROSTATIC DISCHARGE - PROTECTION CIRCUITRY VDD PAD R I -10 FIRST TRANSISTOR GATE V 0.7 Rochester Institute of Technology Microelectronic Engineering © April 13, 2016 Dr. Lynn Fuller Page 65 High Speed Logic ELECTROSTATIC DISCHARGE - MODEL Human Model: VDD R = 1500 ohms R 0 to 5000 Volts L = 7.5 µH C = 100 pF VDD Machine Model One: R = 100 ohms R 0 to 100 Volts Rochester Institute of Technology Microelectronic Engineering Machine Model Two L = 1.0 µH C = 200 pF R = 10 ohms © April 13, 2016 Dr. Lynn Fuller Charged Device Model L = 50 nH C = 10 pF R = 1 ohms Page 66 High Speed Logic SPICE FOR ESD CIRCUIT Rochester Institute of Technology Microelectronic Engineering © April 13, 2016 Dr. Lynn Fuller Page 67 High Speed Logic REFERNCES 1. Hodges Jackson and Saleh, Analysis and Design of Digital Integrated Circuits, Chapter 4. 2. Sedra and Smith, Microelectronic Circuits, Sixth Edition, Chapter 13. 3. Dr. Fuller’s Lecture Notes, http://people.rit.edu/lffeee Rochester Institute of Technology Microelectronic Engineering © April 13, 2016 Dr. Lynn Fuller Page 68 High Speed Logic HOMEWORK – HIGH SPEED LOGIC 1. Investigate a 100nm ring oscillator. Does the number of stages change the period of oscillation, explain. Does the number of stages change the inverter gate delay, td, explain. Does the size of the transistors affect the period of oscillation, explain. Does the supply voltage, VDD, affect the period of oscillation, explain. Does the temperature affect the period of oscillation, explain. 2. Use SPICE to illustrate some of the questions in problem 1. 3. The simple hand calculation for inverter gate delay, td, uses Resistors to represent the PMOS and NMOS transistors and capacitors to represent the gate self capacitance and input capacitance. Assume the wiring capacitance is zero. How are the resistors and capacitors different for 1um technology compared to 100nm technology. Provide approximate values for the resistors and capacitors for both technologies. Rochester Institute of Technology Microelectronic Engineering © April 13, 2016 Dr. Lynn Fuller Page 69 High Speed Logic SPICE MODELS FOR CD4007 MOSFETS *SPICE MODELS FOR RIT DEVICES - DR. LYNN FULLER 8-7-2015 *LOCATION DR.FULLER'S WEBPAGE - http://people.rit.edu/lffeee/CMOS.htm * *Used in Electronics II for CD4007 inverter chip *Note: Properties L=10u W=170u Ad=8500p As=8500p Pd=440u Ps=440u NRD=0.1 NRS=0.1 .MODEL RIT4007N7 NMOS (LEVEL=7 +VERSION=3.1 CAPMOD=2 MOBMOD=1 +TOX=4E-8 XJ=2.9E-7 NCH=4E15 NSUB=5.33E15 XT=8.66E-8 +VTH0=1.4 U0= 1300 WINT=2.0E-7 LINT=1E-7 +NGATE=5E20 RSH=300 JS=3.23E-8 JSW=3.23E-8 CJ=6.8E-8 MJ=0.5 PB=0.95 +CJSW=1.26E-10 MJSW=0.5 PBSW=0.95 PCLM=5 +CGSO=3.4E-10 CGDO=3.4E-10 CGBO=5.75E-10) * *Used in Electronics II for CD4007 inverter chip *Note: Properties L=10u W=360u Ad=18000p As=18000p Pd=820u Ps=820u NRS=O.54 NRD=0.54 .MODEL RIT4007P7 PMOS (LEVEL=7 +VERSION=3.1 CAPMOD=2 MOBMOD=1 +TOX=5E-8 XJ=2.26E-7 NCH=1E15 NSUB=8E14 XT=8.66E-8 +VTH0=-1.65 U0= 400 WINT=1.0E-6 LINT=1E-6 +NGATE=5E20 RSH=1347 JS=3.51E-8 JSW=3.51E-8 CJ=5.28E-8 MJ=0.5 PB=0.94 Rochester Institute of Technology +CJSW=1.19E-10 MJSW=0.5 PBSW=0.94 pCLM=5 Microelectronic Engineering +CGSO=4.5E-10 CGDO=4.5E-10 CGBO=5.75E-10) © April 13, 2016 Dr. Lynn Fuller Page 70 High Speed Logic SPICE MODELS FOR MOSFETS * From Sub-Micron CMOS Manufacturing Classes in MicroE ~ 1um Technology .MODEL RITSUBN7 NMOS (LEVEL=7 +VERSION=3.1 CAPMOD=2 MOBMOD=1 +TOX=1.5E-8 XJ=1.84E-7 NCH=1.45E17 NSUB=5.33E16 XT=8.66E-8 +VTH0=1.0 U0= 600 WINT=2.0E-7 LINT=1E-7 +NGATE=5E20 RSH=1082 JS=3.23E-8 JSW=3.23E-8 CJ=6.8E-4 MJ=0.5 PB=0.95 +CJSW=1.26E-10 MJSW=0.5 PBSW=0.95 PCLM=5 +CGSO=3.4E-10 CGDO=3.4E-10 CGBO=5.75E-10) * *From Sub-Micron CMOS Manufacturing Classes in MicroE ~ 1um Technology .MODEL RITSUBP7 PMOS (LEVEL=7 +VERSION=3.1 CAPMOD=2 MOBMOD=1 +TOX=1.5E-8 XJ=2.26E-7 NCH=7.12E16 NSUB=3.16E16 XT=8.66E-8 +VTH0=-1.0 U0= 376.72 WINT=2.0E-7 LINT=2.26E-7 +NGATE=5E20 RSH=1347 JS=3.51E-8 JSW=3.51E-8 CJ=5.28E-4 MJ=0.5 PB=0.94 +CJSW=1.19E-10 MJSW=0.5 PBSW=0.94 +CGSO=4.5E-10 CGDO=4.5E-10 CGBO=5.75E-10) Rochester Institute of Technology Microelectronic Engineering © April 13, 2016 Dr. Lynn Fuller Page 71 High Speed Logic SPICE MODELS FOR MOSFETS *4-4-2013 LTSPICE uses Level=8 * From Electronics II EEEE482 FOR ~100nm Technology .model EECMOSN NMOS (LEVEL=8 +VERSION=3.1 CAPMOD=2 MOBMOD=1 +TOX=5E-9 XJ=1.84E-7 NCH=1E17 NSUB=5E16 XT=5E-8 +VTH0=0.4 U0= 200 WINT=1E-8 LINT=1E-8 +NGATE=5E20 RSH=1000 JS=3.23E-8 JSW=3.23E-8 CJ=6.8E-4 MJ=0.5 PB=0.95 +CJSW=1.26E-10 MJSW=0.5 PBSW=0.95 PCLM=5 +CGSO=3.4E-10 CGDO=3.4E-10 CGBO=5.75E-10) * *4-4-2013 LTSPICE uses Level=8 * From Electronics II EEEE482 FOR ~100nm Technology .model EECMOSP PMOS (LEVEL=8 +TOX=5E-9 XJ=0.05E-6 NCH=1E17 NSUB=5E16 XT=5E-8 +VTH0=-0.4 U0= 100 WINT=1E-8 LINT=1E-8 +NGATE=5E20 RSH=1000 JS=3.51E-8 JSW=3.51E-8 CJ=5.28E-4 MJ=0.5 PB=0.94 +CJSW=1.19E-10 MJSW=0.5 PBSW=0.94 PCLM=5 +CGSO=4.5E-10 CGDO=4.5E-10 CGBO=5.75E-10) * Rochester Institute of Technology Microelectronic Engineering © April 13, 2016 Dr. Lynn Fuller Page 72 SOLUTION The layout for an NMOS transistor and its SPICE model is shown on the next page. Calculate the internal capacitance Cgate and Cdrain. Cgate = or Area / TOX where Area = L x W = 2um x 12um = 8.85e-12 (3.9) (2e-6) 12e-6/1.5e-8 = 55.2fF Cdrain = Cj Ad + Cjsw Pd where Cj=6.8e-4 and Cjsw=1.26E-10 Ad=144p Pd=48u Cdrain = 6.8e-4x144e-12 + 1.26e-10x48e-6 = 97.9fF + 6.05fF = 104fF Combine these capacitors into one equivalent capacitance (Cinverter) at the output node of a CMOS inverter in a ring oscillator. Assume the PMOS capacitor values are equal to the NMOS internal capacitor values. Cinverter = 2 Cgate + 2 Cdrain = 2x55.2fF +2x104fF = 318fF If the transistors provide a constant current of 3mA when charging or discharging Cint calculate the gate delay lowto-high TDLH and high-to-low TDHL and the inverter gate delay. Q=CV=I t where V= VDD/2= 2.5, C=Cinverter, I=3mA TDLH = TDHL = Cinverter xV / I = 318fF x 2.5 / 0.003 = 0.265ns td = TDLH + TDHL = 0.53ns * From Sub-Micron CMOS Manufacturing Classes in MicroE ~ 1um Technology .MODEL RITSUBN7 NMOS (LEVEL=7 +VERSION=3.1 CAPMOD=2 MOBMOD=1 +TOX=1.5E-8 XJ=1.84E-7 NCH=1.45E17 NSUB=5.33E16 XT=8.66E-8 +VTH0=1.0 U0= 600 WINT=2.0E-7 LINT=1E-7 +NGATE=5E20 RSH=1082 JS=3.23E-8 JSW=3.23E-8 CJ=6.8E-4 MJ=0.5 PB=0.95 +CJSW=1.26E-10 MJSW=0.5 PBSW=0.95 PCLM=5 +CGSO=3.4E-10 CGDO=3.4E-10 CGBO=5.75E-10) *