A New Three Phase Multilevel Inverter With
Reduced Number Of Switching Power Devices With
Common Mode Voltage Elimination
Arpan Hota, Sachin Jain
Vivek Agarwal
Department of Electrical Engineering
National Institute of Technology Warangal
Warangal, India
hota.arpan@gmail.com, jsachin@nitw.ac.in
Department of Electrical Engineering
Indian Institute of Technology Bombay
Mumbai, India
agarwal@ee.iitb.ac.in
Abstract— This paper presents a new topology for a 3-ϕ,
three step multilevel inverter (MLI) with Common Mode Voltage
(CMV) elimination. The proposed MLI structure is realized with
fewer switching power devices compared to the conventional
MLI solutions for CMV elimination. A space vector modulation
technique, based on Large Medium Zero Vector Modulation
(LMZVM), is also proposed to operate the presented MLI.
Reduced number of switching power devices results in less
number of driver circuits, reduced installation space and low
cost. Further, due to the elimination of CMV, the proposed MLI
is free from issues like EMI and leakage current. Presented
topology is compared with other topologies to prove its
superiority. Simulation results are presented to confirm the
capability of the proposed MLI.
Keywords— Common Mode Voltage elimination; 3-ϕ Multilevel
Inverter; Reduced switching power device;
I. INTRODUCTION
The demand for High Voltage (HV) and high power
applications is increasing rapidly. At the same time there are
increasing constraints with respect to size, volume, cost and
weight of the systems. This restricts the use of low frequency
heavy weight transformers in HV and high power applications
which would have been a viable solution. Also, the usage of
low frequency transformer restricts the variation in input and
output voltage. Thus, there is a requirement for power
conditioners which not only give extended bandwidth for
variations in input and output voltage but also have the
advantages of low weight, low cost and controllability. For
these reasons, the HV power converters are at the focal point
of continuing studies for the researchers. Among the various
options, Multilevel Inverters (MLI) are a good solution for HV
applications, as they are supported by advantages like high
power quality (low THD), reduced switching loss and lower
dv/dt stress [1-5].
However MLIs are often operated at high frequency to
reduce the size and improve power quality. This may result in
high frequency voltage transitions between the load and
source neutral point. This voltage is also known as CMV. The
high frequency switching of CMV causes several issues in
electrical systems like electromagnetic interference, leakage
current etc. These problems also restrict the application of
MLI to various sophisticated fields like aerospace, military,
medical etc. In case of electric drives applications, the high
frequency transitions of CMV may cause leakage current and
bearing current, which are hazardous for the motor. It can also
result in lubricant insulation failure [6-7]. For PV applications
high frequency voltage transition in CMV causes the flow of
leakage current in the stray capacitance between the grounded
body of the PV cell and the PV cell itself [8].
In literature there are several methods and MLI
configurations which have been proposed to eliminate or
reduce the CMV. Configurations proposed in [9-12] use a dual
inverter system for its application to an open-end winding
induction motor with CMV reduction. These are good
solutions but for specific application. Some other proposed
topologies in [13-14] eliminate CMV in induction motor
drives. However they suffer the disadvantage of higher switch
count. This results in higher cost, size and weight of the MLI.
Another good solution given by Lee et.al. where authors have
proposed a new PWM technique for reduction of the CMV in
3-ϕ grid connected PV system [15]. It also minimizes leakage
current. In short all the above solutions are either application
specific or require more number of devices for the elimination
of CMV.
This paper presents an optimized configuration of a
3-ϕ MLI with minimum number of switches. The proposed
system eliminates the CMV and high frequency voltage
transition in between the load neutral and source terminal
points. Proposed topology requires simple Space Vector
Modulation (SVM) strategy with Large Medium Zero Vector
Modulation (LMZVM) [15]. LMZVM is modified in a way
that it can completely eliminate CMV for the proposed MLI
structure. The proposed MLI structure is optimized with
respect to the PWM strategy. So, it can eliminate CMV even
with a reduced switch count compared to the conventional
solutions.
This manuscript is divided into five sections. Section
II describes about the structure of the proposed 3-ϕ MLI.
Section III discuss about the PWM technique used to operate
the proposed MLI. Section IV gives the comparison of the
proposed topology with the conventional topologies and the
recent topologies proposed. The simulation results are shown
and explained in section V and the concluding statements are
given in section VI.
MLI for CMV elimination. The details of the PWM strategy
are given in the next subsection.
II. OPERATION OF THE PROPOSED MLI
Fig. 1 shows the configuration of the proposed 3-ϕ MLI
topology with CMV elimination. The structure comprises 13
switches. As shown in Fig. 1 phase A can be connected to bus
1,2 or 3 by using the power switches S1A, S2A or S3A
respectively. Similarly for phase B the switches are S1B, S2B or
S3B and for phase C, the switches are S1C, S2C or S3C. Out of
these switches, S2A, S2B and S2C are four quadrant switches.
These switches are realized by anti-series connection of two
MOSFETs with anti-parallel diode. All other switches are two
quadrant switches which can be realized by single MOSFETs
with anti-parallel diode. Thus, to realize these nine switches
twelve MOSFETs are required. Further, it may be observed in
Fig. 1 that these switches connect the 3-ϕ output to three buses
(bus 1, 2 and 3). So, they are called ‘phase-to-bus’ switches.
Another important point to be noted is that the proposed
configuration requires four dc voltage sources each of equal
magnitude (Vdc) as can be observed in Fig. 1. The string of the
dc sources consists of five terminal or nodal points at the dc
bus (P0, P1, P2, P3, P4). Now, as suggested by Fig. 1, bus 2 can
be connected to nodal point P3 if switch S1 is turned ON or can
be connected to nodal point P2 if switch S2 is turned ON.
Switch S1 and S2 cannot be turned ON simultaneously as that
will cause a ‘shoot through’. Similarly, Bus 3 can be
connected to nodal point P1 if switch S3 is active or nodal point
P0 if switch S4 is active but to avoid shoot through problem, S3
and S4 cannot be turned ON simultaneously. Switches S1, S2,
S3 and S4 are called ‘bus-to-point’ switches. These four
switches are also two-quadrant in nature. So, they can be
realized using single MOSFETs. Thus, the total number of
MOSFETs required to build the complete topology is sixteen.
A star connected load is connected at the nodal point PA, PB
and PC with load neutral point N.
Now, by properly switching phase-to-bus and bus-topoint switches many state vectors can be generated. For
example, a certain vector [X,Y,Z] can be generated by
connecting phase A to point PX, phase B to point PY and phase
C to nodal point PZ (X,Y,Z ranges from 0 to 4). Proposed
topology can generate 13 state vectors for which CMV is zero.
These 13 vectors are presented in Table 1. The active switches
for each of the vector are also shown in Table 1. For example
to generate the vector [1, 4, 1] phase A, B and C should be
connected to nodal point P1, P4 and P1 respectively. Now,
nodal point P1 is only accessible via bus 3 so, phase A and C
both connected to bus 3 by turning ON switch S3A and S3C
then bus 3 is connected to nodal point P1 by turning ON
switch S3. Similarly nodal point P4 is accessible directly via
bus 1 so, switch S1B is turned ON to connect phase B to nodal
point P2. Similarly, other vectors with zero CMV can be found
as described in Table I. These 13 vectors are plotted in Fig. 2
which takes the form of a hexagon with 12 Sectors. And a
suitable PWM strategy is devised to operate proposed 3 phase
Fig. 1. Proposed optimized 3-ϕ MLI topology with zero CMV.
TABLE I.
VOLTAGE VECTORS WITH ZERO CMV AND THE CORRESPONDING ACTIVE
SWITCHES
State
Vector
location [Fig. 2]
[2,2,2]
[4,1,1]
[4,2,0]
[3,3,0]
[2,4,0]
[1,4,1]
[0,4,2]
[0,3,3]
[0,2,4]
[1,1,4]
[2,0,4]
[3,0,3]
[4,0,2]
Corresponding active switches (while all
other switches are turned OFF)
S2A, S2B, S2C, S2
S1A, S3B, S3C, S3
S1A, S2B, S3C, S2, S4
S2A, S2B, S3C, S1, S4
S2A, S1B, S3C, S2, S4
S3A, S1B, S3C, S3
S3A, S1B, S2C, S2, S4
S3A, S2B, S2C, S1, S4
S3A, S2B, S1C, S2, S4
S3A, S3B, S1C, S3
S2A, S3B, S1C, S2, S4
S2A, S3B, S2C, S1, S4
S1A, S3B, S2C, S2, S4
Fig. 2. State vectors generated using proposed optimized configuration
with zero CMV.
Now, using the values from Table II in (1) and (4) the values
of T1, T2, T0 can be calculated.
III. PWM STRATEGY
The PWM technique required to operate the proposed 3
phase MLI uses LMZVM method [15]. LMZVM is an SVM
strategy, which uses state vectors located in the hexagon
boundary and its centre as given in Fig. 2. There are twelve
vectors, which are located at the hexagon boundary and the
zero vector [2,2,2] which is located at the centre. Out of those
12 vectors 6 are large vectors and the remaining 6 are medium
vectors. Large vectors utilize all dc bus voltage which results a
vector with magnitude 3.742Vdc. Similarly medium voltage
vector bypasses one dc source resulting in a vector with
magnitude 3Vdc. Large voltage vectors are [4,0,2], [4,2,0],
[2,4,0], [2,0,4], [0,2,4] and [0,4,2]. Medium voltage vectors
are [4,1,1], [1,1,4], [1,4,1], [0,3,3], [3,0,3] and [3,3,0]. The
magnitude and angle values for all the vectors are listed in
Table II. These 13 vectors divide the hexagon in 12 sectors as
illustrated by Fig. 2. Now, the output vector at any sector will
be realized using a large vector, a medium vector and a zero
vector. To achieve this following steps are involved:
Step 1: The sector identification is done from the value of the
angle of the output vector.
Step 2: The switching times are calculated for the three
vectors associated with the identified sector.
One example is taken for a given sector as shown in
Fig. 3. As Fig. 3 suggests the sector is made up of large,
medium and zero vectors. X 11 is the medium
vector, X 2  2 is the large vector and the zero vector is 00 .
Now, an output vector X has to be implemented using the
three vectors. This is achieved when X 11 vector is turned
ON for time T1, vector X 2 2 is turned ON for time T2 and
the zero vector is turned ON for T0 time. If total switching
time is TS then
T0 + T1 + T2 = TS
(1)
And T1X1θ1  T2 X 2 θ 2  TS Xθ
(2)
 X cos 1
Or,  1
 X 1 sin 1
(3)
X 2 cos  2  T1 
cos  
 TS X 

X 2 sin  2  T2 
 sin  
 X 1 cos1
T1 
Or,    TS X 
T
 X 1 sin 1
 2
Fig. 3. Generation of output voltage vector using LMZVM.
Vector
Number
State
Vector
Magnitude of the
vector (in voltage)
Angle
of
the
vector (in degrees)
0
[2,2,2]
0
0 / 360
1
2
[4,1,1]
[4,2,0]
3Vdc
3.742Vdc
0 / 360
30
3
[3,3,0]
3Vdc
60
4
5
6
7
8
9
10
11
[2,4,0]
[1,4,1]
[0,4,2]
[0,3,3]
[0,2,4]
[1,1,4]
[2,0,4]
[3,0,3]
3.742Vdc
3Vdc
3.742Vdc
3Vdc
3.742Vdc
3Vdc
3.742Vdc
3Vdc
90
120
150
180
210
240
270
300
12
[4,0,2]
3.742Vdc
330
Now, it may be observed in Table II that among the nonzero
vectors, the minimum magnitude is 3Vdc. The circle inscribed
inside the hexagon can have a maximum radius of 3Vdc as can
be observed from Fig. 2. So, the linear range of modulation
exists for the output voltage vector with magnitude up-to 3Vdc.
The amplitude modulation index is defined as:
X
(5)
ma =
3Vdc
When ma is operated between 0 and 1 it is the range
for linear modulation. In the range of linear modulation the
output voltage will always have same number of levels.
Because any arm of the hexagon in Fig. 2 has three vectors
and whatever the value of ma the chosen vectors to implement
the output vector are always selected from hexagon boundary
and its centre. The voltage spikes in CMV that may occur due
to the dead band can be suppressed by using a common mode
capacitive filter.
IV. COMPARISON OF THE PROPOSED CMLI WITH EXISTING
1
X 2 cos 2  cos 

X 2 sin  2   sin  
TABLE II.
STATE VECTORS WITH THEIR ANGLE AND MAGNITUDE
(4)
TOPOLOGIES
The purpose of the introduction of the proposed 3
phase MLI is to eliminate CMV with a reduction in the
number of power semiconductor devices. Therefore, the
proposed CMLI is compared with existing topologies in terms
of number of switching power devices, number of levels
produced and CMV. The configuration proposed in [14]
requires 24 switches to completely eliminate CMV and it
produces three level output. Whereas the proposed topology
consists of only 16 switches and it also produces a three level
output voltage.
The topology and the PWM technique presented in [15]
requires only 12 power switches but it cannot eliminate CMV
completely whereas the presented topology completely
eliminates CMV. The proposed topology is also compared
with the three level NPC, three level Cascaded H-bridge
(CHB) and the proposed topology in [14] and [15] in terms of
number of switches and CMV. The comparison results are
presented in Table III.
observation can be made from Fig. 7 is that the current
becomes more trapezoidal with the increase of ma. Though
slight increase in current THD can be observed with the
increase of ma, it is always less than 5% meeting the IEEE
1547 standard.
TABLE III.
COMPARISON OF THE PROPOSED TOPOLOGY WITH EXISTING TOPOLOGIES
3-ϕ Three level MLI
Topology
NPC
Cascaded H-bridge
Configuration given by
Kumar et.al. [14]
Configuration given by
Lee et.al. [15]
Presented topology in
this paper
V.
Number of
power semiconductors
18
12
24
CMV
Not eliminated
Not eliminated
eliminated
12
Reduced
16
eliminated
SIMULATION RESULTS
The performance of the above mentioned 3 phase MLI
has been investigated by using a simulation model in
MATLAB/SIMULINK environment with PLECS block-set.
Switching frequency is kept at 10 kHz. Each phase of the 3
phase Y connected load consists of an RL load with R=100 Ω
and L=0.05 H while the value of voltage of each voltage
source is 100 Volts i.e. Vdc=100 Volts. Fig. 4 (a) shows the 7
level line to line output voltage of the proposed MLI at ma=1.
The sinusoidal nature of the load current is depicted in Fig. 4
(b). From Fig. 4 (c) it can be seen that the CMV is zero which
proves the fact that the proposed MLI eliminates the CMV.
From Fig. 5 it can be seen that the voltage difference between
load neutral point N and different nodal points from the string
of the sources (P0, P1, P2, P3, P4) are constant. As these
voltages do not involve any high frequency voltage transitions
it can be inferred that, the proposed MLI eliminates the
leakage current flow when used for PV applications. Output
voltage and current waveform with current THD at different
ma under linear modulation have been recorded in Fig. 6. An
important observation can be made from Fig. 6 that for every
value of ma output voltage waveform always has 7 levels
which proves the fact that the proposed MLI will have same
number (7) of levels irrespective of the value of ma. But it can
also be seen from Fig. 6 that as ma decreases pulse width also
decreases. Fig. 7 shows output voltage and current with THD
in over-modulation at different ma values with ma greater than
1. It is evident from Fig. 7 that as ma increases the switching
time of zero vector reduces. And at ma= 1.3 there is no
switching of zero vector i.e. the output vector is completely
outside of the hexagon boundary. Another important
Fig. 4. (a) Line to line output voltage of the proposed MLI (b)Load current (c)
CMV between load neutral N and source neutral P2.
The blocking voltages of the switches (S1A, S2A, S3A)
that connects phase A to the three buses are shown in Fig. 8.
For the other phases the waveform will be same but 120
degree phase shifted. One important observation can be made
from Fig. 8 (b) that the blocking voltage of switch S2A varies
from -300 volts to 200 volts which supports the requirement
of a four quadrant, bi directional switch for the realization of
S2A. Fig. 8 also indicates that switch S1A and S3A will stay in
turn OFF state for a long time (TOFF). And switching state
transition happens between 0 to 200 V which is half of the
total dc bus voltage. So, it can be concluded that switches S1A
S3A will have low switching loss. Fig. 9 shows the blocking
voltage waveform of the bus-to-point switches S1, S2, S3, S4.
The blocking voltage of the 4 bus-to-point switches are 100 V
which is one fourth of the total dc bus voltage.
Fig. 5. V0N, V1N, V2N, V3N and V4N are voltage difference between load neutral
point N and P0, P1, P2, P3 and P4 respectively.
ma=1
THD=1.97%
ma=1
iA
400
200
0
-200 VAB ma=0.5
-400
400
200
0
-200 VAB ma=0.3
-400
3.5
3.0
Time (sec)
ma=0.7
iA
ma=0.5
THD=3.67%
iA
0
-2
2
THD=2.81%
ma=0.7
2
ma=0.3
0
-2
2
0
-2
1
Fig. 9. Blocking voltage of switches S1, S2, S3, S4.
0
THD=4.63%
4.0
× 1e2
3.0
3.5
Time (sec)
4.0
-1
× 1e2
Fig. 6. Output voltage VAB (line to line) and load current iA at different values
of ma under linear modulation with current THD.
400
200
0
-200
-400
Voltage (V)
400
200
0
-200
-400
400
200
0
-200
-400
2.0
ma=1.3
THD =
4.06%
VAB
ma=1.2
VAB
ma=1.1
ma=1.05
2.5
3.0
Time (s)
3.5
ma=1.1
iA
THD =
1.34%
VAB
4.0 2.0
× 1e-2
2.5
Time (s)
iA
ma=1.2
iA
THD =
3.52%
THD =
1.73%
VAB
ma=1.3
3.0
ma=1.05
iA
3.5
2
0
-2
2
0
-2
2
Current (A)
400
200
0
-200
-400
The load current THD for proposed MLI is always less
than 5% as shown in Fig. 6 and 7. This meets the requirement
of IEEE 1547 standard. Therefore, the proposed MLI is
expected to be a convenient solution for grid integration. The
FFT analysis of load current is shown in Fig. 10 for ma= 1. It
can be seen that the maximum magnitude of the other
harmonics is less than 1.6%.
0
-2
Mag(% of Fundamental)
iA
Current (A)
Voltage (V)
400
200
0
-200 VAB
-400
400
200
0
-200 VAB
-400
2
0
Fig. 10. FFT analysis for the load current shown in Fig. 4 (b).
-2
4.0
× 1e-2
Fig. 7. Output voltage VAB (200V/div.)(line to line) and load current iA
(2A/div.) at different values of ma under over modulation with current THD.
VI. CONCLUSION
The topology presented in this paper is optimized with
respect to the PWM strategy used to eliminate the CMV. So,
the proposed configuration is blessed with the advantage of
reduced number of power switches when compared to the
existing topologies. Another advantage of the proposed MLI
structure is the voltage difference between the load neutral
point and the different terminals of dc bus are constant i.e. no
high frequency voltage transition. This is expected to solve the
major issues related to CMV like EMI and leakage current.
Another important point to be noted is that the current THD of
the proposed MLI converter meets the IEEE 1547 standard.
This results in better power quality performance. The
abovementioned points indicate that the proposed MLI
configuration is expected to be a good solution for drives
applications and grid-tied PV applications.
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ON period of a switch. TOFF: Continuous OFF period of switch. TSw: Period
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