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IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 17, NO. 1, FEBRUARY 2004
Characterization of Spatial Intrafield Gate CD
Variability, Its Impact on Circuit Performance,
and Spatial Mask-Level Correction
Michael Orshansky, Member, IEEE, Linda Milor, Member, IEEE, and Chenming Hu, Fellow, IEEE
Abstract—The authors present a comprehensive characterization method applied to the study of the state-of-the-art 18- m
CMOS process. Statistical characterization of gate CD reveals
a large spatial intrafield component, strongly dependent on the
local layout patterns. The authors describe the statistical analysis
of this data and demonstrate the need for such comprehensive
characterization. They describe the experimental setup of the
novel measurement-based characterization approach that is
capable of capturing all the relevant CD variation patterns
necessary for accurate circuit modeling and statistical design
for increased performance and yield. Characterization is based
upon an inexpensive electrically based measurement technique. A
rigorous statistical analysis of the impact of intrafield variability
on circuit performance is undertaken. They show that intrafield
CD variation has a significant detrimental effect on the overall
circuit performance that may be as high as 25%. Moreover, they
demonstrate that the spatial component of gate CD variability,
rather than the proximity-dependent component, is predominantly responsible for speed degradation. In order to reduce the
degradation of circuit performance and yield, the authors propose
a mask-level spatial gate CD correction algorithm to reduce the
intrafield and overall variability and provide an analytical model
to evaluate the effectiveness of correction for variance reduction.
They believe that potentially significant benefits can be achieved
through implementation of this compensation technique in the
production environment.
Index Terms—Characterization, correction, modeling, process
variation, statistical design.
I. INTRODUCTION
W
ITH the increasing complexity of advanced semiconductor processes, intrafield CD variability becomes a
more significant component of the overall CD variability. This
necessitates a more thorough investigation of its effect on circuit performance and yield. It has been traditionally believed
that, for the purpose of statistical circuit analysis, intradie parameter variability is a concern exclusively for analog designs.
Manuscript received February 28, 2001; revised August 25, 2003. This work
was supported by fellowships from Semiconductor Research Corporation and
Advanced Micro Devices, Inc.
M. Orshansky is with the Department of Electrical and Computer
Engineering, University of Texas, Austin, TX 78712 USA (e-mail: orshansky@mail.utexas.edu).
L. Milor is with the Department of Electrical Engineering and Computer
Sciences, Georgia Institute of Technology, Atlanta, GA 31405 USA (e-mail:
linda.milor@ece.gatech).
C. Hu is on leave from the Department of Electrical Engineering and
Computer Science, University of California, Berkeley, CA 94720 USA (e-mail:
hu@eecs.berkeley.edu).
Digital Object Identifier 10.1109/TSM.2003.822735
However, the growing magnitude of the intrafield CD variation
component may now have a notable effect on the behavior of
digital circuits [1]–[3].
For reasons of modeling simplicity, it was sometimes
suggested that within-field CD variability could be treated as
random and adequately described by a sigma value [4]. Statistical analysis of the process shows, however, that intrafield
CD variability is largely systematic, not random, resulting in a
distinct CD trend surface. The systematic intrafield variation of
gate CD may be due to many factors, including: stepper induced
variations (illumination, imaging nonuniformity due to lens
aberrations); reticle imperfections; resist-induced variations
(coat nonuniformity, resist thickness variation), and others [4],
[5]. It is also important to realize that the scaling of lithographic
features makes the lens aberrations even more severe by forcing
us to operate at the optical resolution limit of a stepper system.
Much effort has been recently devoted to addressing the
optical proximity effect that worsens the ability to print small
polysilicon features because of the presence of neighboring
lines [6]. In this work, we extend the analysis of pattern-dependent variability by estimating the CD bias resulting from
the coma effect acting on gates which are asymmetrical with
respect to their left and right neighbors [7]. We also experimentally evaluate the CD bias due to the vertical–horizontal
orientation of the gates in the layout.
The analysis shows that while the intrafield variance is still
a relatively small fraction of the overall variance, its impact on
circuit performance is very significant. Through measurements
and circuit simulation, we find that spatial gate CD variation
leads to a large variation in the raw speed of CMOS logic. This is
very important because if the simulation of a circuit’s behavior
ignores the spatial CD information, misleading timing results
are obtained which lead to slower and malfunctioning circuits.
In fact, by considering the analytical results derived in [7], we
also show that the nonuniformity of gate CD leads to significant
degradation of the overall performance of the high-speed digital
circuits. Importantly, it is the spatial (rather than proximity-dependent) gate CD component of variation that is predominantly
responsible for circuit speed degradation.
Given the significant negative impact of intrafield CD variation on circuit performance, we propose a mask-level spatial
correction algorithm to be used for reduction of intrafield and
overall CD variability. The correction algorithm utilizes the fact
that intrafield variation is largely systematic, with a repeatable
mean CD profile. Thus, one may apply a negative profile to compensate for the observed variation pattern. To easily evaluate the
0894-6507/04$20.00 © 2004 IEEE
ORSHANSKY et al.: CHARACTERIZATION OF SPATIAL INTRAFIELD GATE CD VARIABILITY
3
Fig. 2. Gate categories are not represented with equal frequency in the product.
Four major categories account for about 85% of all the gates.
Fig. 1. Classification of gates into the various categories according to their
local layout patterns. This classification of gates uses three distance categories:
dense (1), denso (3), and isolated (5). Dense refers to the minimum allowable
spacing between gates. Denso is an intermediate distance, associated with
the minimum distance between gates separated by a contact. All other larger
distances are labeled as “isolated.”
potential of such correction, we derive an analytical model predicting the reduction of variance.
The paper is organized as follows. First, a comprehensive
measurement-based characterization scheme is described, and
the results of statistical analysis are discussed. Second, the impact of gate CD variation on the performance of digital circuit is
described. Finally, the correction algorithm is described in detail, and the variance-reduction model is derived.
II. CHARACTERIZATION OF INTRAFIELD CD VARIABILITY
For full characterization of pattern-dependent variability, we
classified all the gates into 18 categories depending on their orientation in the layout (vertical or horizontal) and the spacing
to the nearest neighboring gate. To capture the coma effect, we
distinguished the relative position of the surrounding gates, i.e.,
the neighbor on the left versus the neighbor on the right. To capture the multitude of possibilities, we devised a categorization
scheme that allows us to describe easily the layout properties of
or
,
a particular gate. Each gate is denoted by either
where ( ) defines the vertical (horizontal) orientation of a
gate,
defines the spacing to the left (upper) neighbor, and
defines the spacing to the right (lower) neighbor for vertical
(horizontal) gates. The categorization scheme is illustrated in
Fig. 1. It is interesting to note that, as the analysis of an ad-
Fig. 3. Location of test sites on the reticle. Reticle contains test chips arranged
in a 5 5 grid.
2
vanced product layout shows (Fig. 2), 85% of all the gates belong to only four major categories: V53, V35, V33, and V55.
We characterized the intrafield CD variability of a production 0.18- m technology using electrical CD measurements. On
the 22 22 mm reticle field a grid of 5 5 test modules was
placed, as shown in Fig. 3. Each module contained long and
narrow polysilicon resistors, with a variety of distances to adjacent polysilicon lines. The polysilicon resistors were manufactured with the same process steps as polysilicon gates, including
poly CVD, resist coating, exposure, development, and gate definition by plasma etching. We paid special attention to minimizing the confounding of CD variability due to photolithography with other sources of variation. One possible source of undesired variability is the variation in the sheet resistance across
the reticle field that would confound the measurement results.
In order to eliminate this component, each module contained a
test structure to calibrate the sheet resistance. Another possible
source of variation is the silicide resistance, which is known to
cause a large standard deviation in the sheet resistance of thin
lines. In order to avoid this source of variation, the polysilicon
resistors were not silicided. Finally, a third source of variation
would be due to variability in the widths of lines on the test chip
mask. This component of variation could not be eliminated and
is confounded with our measurement results. However, we believe that this component is small.
Data was collected by measuring the resistance of the
polysilicon lines. CD values were then computed. The data
set came from measuring 18 test modules coming from three
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IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 17, NO. 1, FEBRUARY 2004
Fig. 4. CD spatial map for category V53. CD values are minimum in the center
of the reticle field.
Fig. 6. CD spatial map for category V35. Spatial behavior is very different
from that for category V53.
Fig. 7. Difference between the measured CD values for V35 and the CD values
interpolated as (1=2)(V 55+V 33) is plotted. Spatial interpolation of CD values
for V35 on basis of V55 and V33 is quite inaccurate.
Fig. 5. CD spatial map for category V33. Spatial profile of V33 appears to be
similar to V53, but F-tests show that spatial behavior is statistically different.
distinct wafers, thus allowing tests for statistical significance.
Because the observed spatial and proximity-dependent variability is determined by the combined effect of the stepper
and the lens, the same stepper-lens system was used for all
the measurements. Within each test chip devices from ten
major categories were characterized. The measurements were
performed on three wafers with six fields per wafer resulting in
18 replications for each spatial location within the field.
The following statistical model is used for the analysis:
(1)
is the category-dependent within-field syswhere
are the random residuals. The spatematic surface and
tial CD maps were generated by averaging the replicated CD
values and by treating different gate categories separately. A
series of F-tests were carried out to verify that the generated
topological maps of CD variability over the field are statistically significant, i.e., that the level of variation is large in comparison with the random CD noise. Analysis shows that for
all the gate categories, the extracted CD maps are in fact statistically significant. Consider, for example, the gate category
and
. These results indi-
cate that any accurate modeling, or correction, approach must
consider the variation of the mean CD as a function of position
within the reticle field. Variation within the reticle field cannot
be modeled as purely random.
The CD maps for some categories exhibit quite distinct spatial
behaviors, as can be seen from Figs. 4–6. The F-tests confirm
the statistical difference of spatial behavior at 95% confidence
level. This is due to the interaction between the global lens aberration and the pattern-dependent optical proximity effect. The
result is that, at least for some gate categories, distinct spatial
models have to be used for modeling and correction. Data also
suggests that regardless of spatial variability, a statistically significant bias exists between CDs of gates belonging to different
categories.
The t-tests show a bias between mean CDs depending
on spacing (V33 and V55), orientation (V33 and H33), and
left–right asymmetry (V15 and V51). Neither is it possible
to predict the mean CD for a “mixed” category on the basis
of “pure” categories, e.g., one cannot approximate V35 as
. A spatial plot of the difference between
, in fact, shows a large nonuniforV35 and
mity across the area of the field (Fig. 7).
The range of the within field CD variation differs significantly
among the categories. In fact, the relative range is not a smooth
ORSHANSKY et al.: CHARACTERIZATION OF SPATIAL INTRAFIELD GATE CD VARIABILITY
5
Fig. 10. Spatially aware timing analysis flow is shown. In contrast to the
standard timing flow, it uses measured spatial CD maps to produce a modified
netlist and a location-dependent timing report.
Fig. 8. Relative variance of CD from different categories is plotted. It is not
a smooth function of mean CD for that category. Some gate categories (V55)
exhibit much better CD control than others (V51).
Fig. 11. Spatial timing report is shown. Ring oscillator speed varies
significantly across the reticle field. Maximum deviation is 14.5%.
Fig. 9.
Ring oscillator circuits were placed in the positions shown in the reticle.
function of the mean CD for the category (Fig. 8). For example,
the symmetrical isolated gates (V55) seem to have the least relative variability despite having the smallest mean CD. Also, data
shows that the transistors placed horizontally have a 7% higher
overall variability than the vertical transistors and that a larger
portion of their variability is due to noise. This is because most
transistors in the design are oriented in the vertical direction and
the lithography system was optimized for vertical transistors.
III. IMPACT OF SYSTEMATIC INTRACHIP CD VARIABILITY ON
CMOS DEVICE SPEED AND CIRCUIT PERFORMANCE
The immediate effect of spatial CD variation on digital circuits is the resulting variation of CMOS gate delay. In fact, because of the nonlinear delay versus CD relationship
[8], variation of circuit speed may be larger than CD variation. We evaluated circuit variation by measuring the speed of
a 151-stage NAND ring oscillator, often used as a predictor of the
chip performance. The measurements were taken on four spatially separated ring oscillator test structures placed within the
field, as shown in Fig. 9. The range of variation measured in ring
oscillator speed across the field was 14.5%.
In order to assess the impact of CD variation on circuit performance, we need to propagate the spatial CD information down
to the level of timing simulation tools. This may be achieved by
making the device properties depend on the device’s location
within the chip. We developed a tool with the required functionality (Fig. 10). A netlist is first extracted from the original
circuit layout. The layout and the netlist are then passed to the
tool that classifies each gate as belonging to a particular category
and determines the spatial location of the particular gate within
the layout (chip). Using this information together with the set of
CD maps produced at the stage of characterization, the tool then
generates a modified netlist in which each gate has a proper location-dependent CD value and simulates it using a circuit simulator. To verify the accuracy of the approach, we used the SPICE
simulator [8] to generate a spatial ring oscillator frequency map.
Results showed that the ring oscillator frequency map is consistent with the spatial patterns of CD variation (Fig. 11); the
frequency is highest in the center of the chip, where CD is the
smallest. A comparison with the measurements was made for
the four ring oscillators available for test within each reticle.
The ring oscillator data was collected on different wafers than
the CD data, which were processed weeks later. Given the potential sources of noise, the agreement between simulation results and experimental data is notable (Fig. 12). We then used
the tool to assess the impact of CD variation on two metrics crucial for digital circuit performance: the delay of a critical path
of a combinational circuit and the global clock skew.
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IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 17, NO. 1, FEBRUARY 2004
The correction algorithm utilizes the fact that intrafield variation is largely systematic, with a repeatable mean CD profile.
Once we know the shape of the CD spatial map, it is possible
to compensate for this variation by predistorting the features of
the layout. From the point of view of statistics the correction
approach leads to the reduction of uncertainty about the actual
value of CD, reducing the negative impact of the intrachip variability on circuit performance. We envision that spatial correction would complement the existing optical proximity correction algorithms to achieve better intrafield CD uniformity and
increase circuit performance. To evaluate the potential of the
correction, we derive an analytical model predicting the reduction of variance. One of the important results of our analysis is
the finding that the spatial correction is more important for the
improvement of circuit performance than traditional proximity
correction.
Fig. 12. Comparison of measured ring oscillator speed (box) and the predicted
speed distribution (the contour map) at different positions within the reticle field.
Fig. 13. Spatial clock skew map for an H-tree clock distribution network (ps).
Map is shown for one die only. Maximum skew is 74 ps, which is approximately
8% of the total clock cycle.
We simulated timing behavior of a benchmark combinational
circuit from ISCAS’85 [9], containing 1764 CMOS devices,
using a static timing simulator PathMill from Synopsis [10].
Analysis was done for nine spatial locations on the reticle field
in a uniform 3 3 grid. For chip 4, located in the lower-right
quadrant, the delay of the same path placed at different corners
of the chip varied by 16%. Thus, circuit paths with identical
designed-for delays will, in reality, have considerably different
delay distributions, depending on the physical location of the
path within the chip. We then employed this tool to investigate
the impact of CD variation on the skew of the global clock, distributed using the popular H-tree scheme. Because in our stepper
reticle the field consists of four die, we generated four different
skew maps for the clock laid out using buffers composed of V55
gates. For the die in the upper left quadrant of the field, the maximum skew was approximately 8% of the overall clock cycle
(Fig. 13). In practice, the errors due to estimation of the critical
path delay and the clock skew are additive, thus the cumulative
error can be as high as 25%—a considerable amount for digital
circuits with tight cycle time budgets.
IV. SPATIAL MASK-LEVEL CORRECTION AND IMPROVEMENT
OF CIRCUIT PERFORMANCE
We propose a mask-level spatial correction algorithm to be
used for reduction of the intrachip and overall CD variability.
A. Algorithm for Mask-Level CD Correction
We propose to correct the systematic CD variation by predistorting the actual layout features. Algorithmically, and from the
tool’s point of view, this would be achieved through enhancement of the currently existing OPC algorithms. The systematic
intrafield variation of gate CD may be due to many process-related factors, and the precise causal decomposition is difficult
and costly. Our approach to correction is to treat all the contributions as a lump term, as finally observed in CD measurements of the actual devices. After a comprehensive measurement-based and transistor-based CD characterization, a twodimensional (2-D) correction profile would be applied to the
mask, compensating for the observed spatial CD dependency to
achieve superior uniformity. The interaction between the global
variation due to lens aberrations and the local pattern-dependent
variation, found to be significant, must be taken into account
during correction. This can be done by generating a unique spatial correction profile for each gate CD category.
Complete correction is not possible. One limiting factor is the
of printable features on a mask. In addifinite resolution
tion, the random intrafield component is not zero, and correcting
by an amount smaller than the noise level leads to diminishing
returns in the amount of intrafield variability reduction.
In order to develop the correction algorithm, we return to the
most general formulation of the statistical CD model
(2)
In this model ( , ) refers to the position of the CD measurement within the field and denotes the gate category, i.e., V35,
H33, etc. Therefore, the term
describes the categorydependent intrafield CD surface for gate category . It captures
both the global (spatial) CD variation and the local (category-de,
pendent) CD variation. Let
where is the area of the reticle field, be the average CD for
be the overall
a given category. Also, let
mean CD averaged out across all the categories, where is the
number of different gate categories, considered in the analysis
and is the frequency of the particular category. The first step
ORSHANSKY et al.: CHARACTERIZATION OF SPATIAL INTRAFIELD GATE CD VARIABILITY
7
generate a mask with a continuous feature bias reduces the
benefits of corrections. In the next section, we consider the
practical limitations of the correction algorithm on the overall
CD variance reduction, taking into account the finite mask
resolution.
B. Variance Reduction Due to Correction: An Analytical
Approach
To analyze the effectiveness of correction, we propose
a model that allows the evaluation of the reduction of CD
variance due to spatial CD intrafield correction. The achievable
, the
variability reduction depends on the mask resolution
range of spatial intrafield CD variation, category-dependent
CD variance, and the random residual variance. Analysis is
based on a modified statistical model compared to (2)
Fig. 14. Final discrete correction profile is shown. It is generated from the
exact continuous profile based on mask resolution R .
in the algorithm is to generate the continuous CD correction profile
(3)
Alternatively, we can write
(4)
The first term corresponds to the proximity-determined bias
and is the one used in rule-based OPC algorithms. The second
one corresponds to the spatial bias. Equation (4) gives us the description of the ideal spatial CD bias. That is, if we could generate such a bias on the wafer after the etching step, it would
compensate the observed spatial CD variability in the most efficient manner theoretically possible. Thus, this equation describes the theoretical limit to the potential improvement of CD
uniformity. This limit is imposed by the stochastic properties of
the problem, i.e., by the presence of random noise.
However, there exist practical limitations on the gains permitted by a mask-level spatial correction algorithm. One limitation is the finite resolution of the mask that makes it impossible
to create a mask with a continuous compensation profile. Be, the final
cause the mask resolution is not ideal, e.g.,
correction profile has to be discrete rather than continuous, with
. We outline the process of generating the discrete
steps of
correction profile on the basis of the continuous map described
by (4).
1) Experimentally characterize spatial CD profiles:
.
2) Generate continuous correction profiles:
.
with a minimum step size of
.
3) Discretize
4) Define the corresponding regions for each gate category
as follows:
a) CDs in the zeroth region have values
;
b) CDs in the
regions have values
.
Fig. 14 shows a one-dimensional simplification of the
resulting 2-D discrete spatial correction profile generated
according to the algorithm above. However, our inability to
(5)
represents the category-dependent CD
In this model,
stands for spatial CD variation. The
variation and
assumption that this models thus makes is that it is possible to
approximate systematic variance due to both proximity effects
and spatial variation by a combination of two statistically
noninteracting terms. Analysis shows that this is a reasonable
simplification. At the same time, the residual component is
corresponds to the
decomposed into two components,
between-field CD variability component and is modeled by
, and the random intrafield residual is
.
The goal of the variance-reduction model is to establish the
relationship between the CD variances and the mask resolution.
Based on (5), we estimate the variance of CD before and after
correction. We make the assumption that statistical interaction
between the terms of (5) is negligible. Then, their total variance
is given by
First, we describe the variance due to the systematic spatial
CD variation in terms of the range of variation of the CD profile
within the field. Here, we rely on the assumption that statistical
interaction between the spatial and proximity-dependent variability is negligible. Then, the variance of the systematic spatial
term can be adequately represented by
(7)
To evaluate the maximum benefits of the mask correction,
we use the upper bound on the estimate of spatial variability.
We define the range of spatial variation for a given category as
as well as the largest CD
. We can find
range among all the categories
by adopting the following
the upper bound on
simplified model. The initial data set comes from a 2-D spatial map. However, to find the upper bound on the variance of
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IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 17, NO. 1, FEBRUARY 2004
this data set we may choose to ignore the spatial character of
this data. We know that the range of data in this set is given by
. For the purposes of deriving the model, we assume that the
values are distributed uniformly within the data set. We use the
uniform distribution because it provides the upper bound on the
variance and, compared to the normal distribution, it is significantly easier to analyze. (Indeed, an alternative could have been
to assume that the values are distributed according to the normal
.) With the assumption of a unidistribution truncated at
form distribution
(8)
After the spatial correction algorithm is applied to the mask,
the maximum difference that may still exist between the mean
, the mask resCDs at different locations within the field is
olution. A similar derivation can demonstrate that the variance
of the corrected spatial CD profile is bounded by
(9)
The calculation of the variance of the category-dependent
term takes into account the frequency of a gate category in the
is a discrete random variable, its
overall gate CD count.
variance is found according to the standard textbook equation
[11]
(10)
where is the frequency of the particular category. To evaluate
the effect of correction, we note that in the course of the category-dependent correction, e.g., such as is being done in the
OPC algorithms, we guarantee that for any given gate CD category the bias cannot be larger than
(11)
Then, the corrected total category-dependent variance is
bounded by
Fig. 15. Variance reduction as a function of mask resolution. Presence
of random noise sets a point of diminishing return below which resolution
improvements give a significantly smaller payoff in terms of variance reduction.
We verified the model for variance reduction by simulating
the effect of correction on the actual data set collected in the
course of our CD characterization. The data set values were
modified (i.e., “corrected”) in a way prescribed by the correction
algorithm. A bias was assigned to each location and was added
to all the data points coming from the same location. After that,
the new variance for the entire data set was calculated. Fig. 15
values for purely
shows the result of correction at different
spatial correction; all the data comes from a single gate category, so no category-dependent variation is present (the corresponding terms in the model were set to zero). The figure shows
that the model can predict the reduction in the overall variance
produced by the simulation of the correction algorithm fairly
well.
The usefulness of the model is that it allows us to assess the
behavior of the algorithm for different mask resolutions and different correction strategies. For example, the model predicts that
improving mask resolution would allow improving the effectiveness of correction, at the expense of the increased mask cost
associated with high printing resolution. At the same time, there
clearly exists a point of diminishing return with respect to reduction of the mask resolution. Overall, the model indicates that for
very fine mask resolutions (close to the ideal mask resolution
), there exists a potential to reduce CD variance by up
to 35%.
(12)
C. Sampling Requirements of the Spatial Mask
Correction Algorithm
All other remaining components of (5) are purely random
variables, whose variance is not affected by the mask correction mechanism. We can assess the overall variance reduction
through the ratio between the corrected and raw (original) CD
.
variance
Combining all the terms, the ratio between the raw and corrected variability may be characterized as
(13)
We discovered that an important factor in achieving maximum benefits from correction is the completeness of the sampling plan that is responsible for the initial characterization of
the spatial CD profile. Therefore, in addition to considering
correction using full sampling (25 points/reticle), we considered correction under uncertainty caused by limited spatial sampling. Sampling plan A assumes that only the center and four
corner points on the field are available for measurement. In sampling plan B, the center point and four edge points are available (Fig. 16). Fig. 17 shows that correction under uncertainty,
ORSHANSKY et al.: CHARACTERIZATION OF SPATIAL INTRAFIELD GATE CD VARIABILITY
9
predictor. Let us denote the set of neighboring sites for each spa, and let
be the number of sites
tial site (x,y) by
. Then, the predicted value is given by
in
(14)
Then, we compared the predicted and the actually measured
value to assess the predictive power of the model at this location
as
and calculated the standard error of cross-validation
Fig. 16. Comparison of two different limited sampling plans. Samples are
placed within the field as indicated.
(15)
Fig. 17. Variance reduction as a function of mask resolution under different
spatial sampling plans. Correction under uncertainty (sampling plans A and B)
results in significantly smaller variance reduction compared to correction using
a full sampling plan.
e.g., correction that relies on spatial maps characterized by incomplete sampling plans A and B, leads to substantially smaller
variability reduction. For the finer mask resolution, the sampling
plan A appears to be marginally better than plan B.
It is also possible to consider the issue of how good our “full”
sampling plan is. Clearly, the truly accurate spatial map can be
generated only through an infinitely fine sampling. What is thus
desirable is to provide some measure of the interpolative power
of the “full” sampling plan. What we want to know is how well
the “full” spatial map predicts CD values outside of the measurement locations. Typically, the statistical test of this nature is
performed by separating from the start a “training” data set from
the “test” data set. Because we are unable to increase the size of
our data set beyond the available 25 spatial locations, such an
approach is not feasible for us. Instead, we can perform the comparison using cross-validation or boot-strapping techniques. We
carried out a particularly simple cross-validation test in which
we successively predict the mean CD value for all our spatial locations using the measured data from the neighboring sites only.
The average of the nearest neighbors was used as the simplest
We computed the cross-validation error for the gate category
V53. The meaningful way of interpreting the error is by comparing it with the random residual as defined by (2). The
, and an F-test at 95% concomputed ratio is
fidence level gives
, confirming that the random
residual error is significantly larger than the cross-validation
error. This indicates that the model predictions are reasonably
accurate compared to the amount of “noise” in the data, which
confirms our belief in the validity of the model and the adequacy
of a spatial sample size of 25 points per field.
An interesting practical conclusion follows from the analysis
with limof Fig. 17. It appears that ideal correction
ited sampling gives worse results than correction with finite resolution. One possible explanation of this trend is the so-called
bias-variance tradeoff, well known in statistics. Roughly, the
final empirically observable variance is a combination of the
random variation around the spatial CD map plus the deviation
of the spatial CD map from the global mean. When we have
precise knowledge about the shape of the spatial CD map, correcting this known map with as fine resolution as possible results
in optimal variability reduction. When, however, our knowledge
of the spatial CD map is limited due to insufficient sampling,
performing the correction with the perfect resolution may lead
to a suboptimal variability reduction. Indeed, we may think that
we corrected the spatial trend entirely, but that is the case only
for the observed rather than unknown true CD map.
D. Impact of Mask-Level CD Correction on Circuit
Performance
In this section, we explore the impact of gate CD correction
on circuit speed. We do this by using the model for circuit speed
dependence on intrachip CD variability developed in [9] and
also by applying the model of variability reduction due to masklevel correction described above. In [9], it is shown that clock
cycle time of a digital circuit is limited by
(16)
is the maximum designed-for delay,
is the
where
nominal CD value, is the degradation coefficient determined
by the complexity of the circuit and the number of near-critical
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IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 17, NO. 1, FEBRUARY 2004
comprehensive characterization methodology is needed to accurately capture all the sources of CD variation and their complex patterns. Our analysis shows that in contrast to the interfield variation component, intrafield CD variation has a detrimental effect on the overall circuit performance distribution, reducing the average speed by up to 20%. We derive an analytical
model quantitatively relating intrafield CD variance to circuit
delay degradation. In order to reduce the detrimental effect of
intrafield CD variability, we propose a mask-level spatial gate
CD correction algorithm that should be employed along with
the traditional optical proximity correction schemes. We also
provide an analytical model to evaluate the effectiveness of correction for variance reduction, which indicates that correction
can lead to notable improvement in average circuit speed.
ACKNOWLEDGMENT
Fig. 18. Circuit performance improvement as a function of mask resolution.
Spatial correction combined with standard OPC algorithms is drastically more
effective in improving circuit speed than OPC alone.
The authors wish to acknowledge Advanced Micro Devices
for providing the experimental data used in this work.
REFERENCES
paths, and
is the average number of gates along a critical
path. We now use the variances of the spatial and category-dependent variation components computed in Section IV-B,
and
to evaluate
(16)
(17)
This expression allows us to evaluate the circuit performance
enhancement that will result from implementing the proposed
spatial CD correction algorithm with a given mask resolution.
We simulated the impact of the correction algorithm on our data
set so that every data point was modified in accordance with
the algorithm. We compared two correction approaches to determine which provides a more effective way of increasing circuit performance. The first correction scheme is purely category
. The
dependent, aiming to eliminate the bias between
second scheme also includes spatial correction. Fig. 18 summarizes the results of the comparison. The important observation
is that reduction of spatial intrafield variation has a much more
significant effect on the improvement of circuit speed than the
reduction of category-dependent CD variation. This is because
the category-dependent variation gets averaged across the multiple gates in the path, while the spatial variation affects all the
gates of a spatially confined path. This result is important since
it shows that, for circuit performance improvement, correcting
spatial variability is far more important than correcting the proximity effects done by the standard OPC algorithms.
V. CONCLUSION
In this paper, we have reported the statistical characterization
of a production 0.18- m CMOS process that shows the presence of significant systematic intrafield gate CD variability. A
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Michael Orshansky (S’96–M’03) received the Ph.D. degrees in electrical engineering and computer science from the University of California, Berkeley, in
2001.
He is currently an Assistant Professor of electrical and computer engineering
at the University of Texas, Austin. Prior to that, he was a Research Scientist and
Lecturer with the Department of Electrical Engineering and Computer Science
at the University of California, Berkeley. His research interests include circuit
design and analysis techniques for manufacturability of high-performance digital and mixed-signal circuits, statistical CAD algorithms for design-for-manufacturing and yield improvement, algorithms for low-power IC design, and modeling and simulation of semiconductor devices. He has published more than 20
technical papers in the areas of statistical CAD algorithms, device physics, and
modeling.
ORSHANSKY et al.: CHARACTERIZATION OF SPATIAL INTRAFIELD GATE CD VARIABILITY
Linda Milor (S’86–M’90) received the Ph.D. degree in electrical engineering
from the University of California, Berkeley, in 1992.
She is currently an Associate Professor of electrical and computer engineering
at the Georgia Institute of Technology, Atlanta. Prior to that, she served as Vice
President of Process Technology and Product Engineering at eSilicon Corporation, as Product Engineering Manager at Advanced Micro Devices, Sunnyvale,
California, and was a faculty member at the University of Maryland, College
Park. She has authored over 50 publications and is the holder of three patents
on yield and test of semiconductor ICs.
11
Chenming Hu (S’71–M’76–SM’83–F’90) received the B.S. degree from National Taiwan University, Taiwan, R.O.C., and the M.S. and Ph.D. degrees in
electrical engineering from the University of California, Berkeley.
He is the Chief Technology Officer of TSMC, Hsinchu, Taiwan. He is on
leave from the University of California, Berkeley, where he is the TSMC Distinguished Professor of Electrical Engineering and Computer Sciences. He was
an Assistant Professor at the Massachusetts Institute of Technology, Cambridge,
for three years. He was the Board Chairman of the East San Francisco Bay Chinese School and is a frequent advisor to industry and educational institutions.
He is a Cofounder and Cochairman of Celestry Design Technologies, Inc. His
present research interests include microelectronic devices, thin dielectrics, circuit reliability simulation, and nonvolatile memories. He has authored or coauthored four books and over 600 research papers and supervised 60 doctoral students. He leads the development of the MOSFET model BSIM3v3 that has been
chosen as the first industry standard model for IC simulation by the Electronics
Industry Association Compact Model Council. He is an Adjunct Professor of
Peking University.
Dr. Hu is a member of the U.S. National Academy of Engineering and an
Honorary Professor of the Chinese Academy of Science. In 1991, he received
the Excellence in Design Award from Design News and the inaugural Semiconductor Research Corporation Technical Excellence Award for leading the research of the IC reliability simulator, BERT. He received the SRC Outstanding
Inventor Award in 1993 and 1994. In 1997, he received the IEEE Jack A. Morton
Award for contributions to the understanding of MOSFET reliability physics. In
1999, he received the DARPA Most Significant Technological Accomplishment
Award for codeveloping FinFET, a promising MOSFET structure for scaling
to 10-nm gate length. He is a member of the U.S. National Academy of Engineering, a Fellow of the Institute of Physics, an Honorary Professor of the
Chinese Academy of Science, Beijing, China, and of Chiao Tung University,
Taiwan. He has received the University of California at Berkeley’s highest honor
for teaching—the Distinguished Teaching Award. He was given a Research and
Development 100 Award for one of the 100 most technologically significant
new products of the year, in 1996.