Frequency / Duty Cycle Control of LCC Resonant Converter Supplying
High Voltage Very Low Frequency Test Systems
Manli Hu, Norbert Fröhleke, Joachim Böcker
Paderborn University, Power Electronics and Electrical Drives
D-33095 Paderborn, Germany
Tel.:+49-5251-60-2220
E-Mail: {hu, froehleke, boecker}@lea.upb.de
URL: http://wwwlea.upb.de
Acknowledgements
The authors like to thank BAUR Prüf- und Messtechnik GmbH, Sulz (Austria), Regatron AG,
Rorschach (Switzerland), and Habemus Electronic & Transfer GmbH, Thannhausen (Germany) for
the support in building and testing the prototype.
Keywords
«Converter control», «Resonant converter», «Soft switching»
Abstract
Very low frequency (VLF) high-voltage (HV) sinusoidal test waveforms are suitable for testing
characteristics and insulation qualities of long buried power cables. Unlike as with conventional PWM
converters, a newly developed LCC resonant inverter combined with a symmetrical three-stage
voltage multiplier rectifier is introduced in this paper to generate VLF HV sinusoidal waves. Due to
the wide ranges of output voltage and output load, both the switching frequency and the duty cycle are
adopted as control variables. Based on a small-signal equivalent circuit model and a reduced-order
transfer function, an average mode current controller is developed for the zero voltage switched LCC
resonant converter generating up to 85 kV (RMS) at 0.1 Hz as test voltage. The theoretical analysis
and design are verified by simulations and experimental measurements with a prototype setup.
1 Introduction
Mobile very low frequency (VLF) high-voltage (HV) test generators are required for the examination
of the characteristics and insulation qualities of long buried cables during commissioning or services.
Such a test generator should be capable of providing the sinusoidal waves with full voltage of some
tens to hundreds of kV at a relatively small power of few to tens of kW. After the original introduction
of VLF test method two decades ago, it has been accepted by European Union Harmonization HD
620-S1 in 1996 and IEC 60060-3-2006 recently [1]. Compared with voltage test systems operating at
50 Hz, the VLF-generators have considerable advantages in terms of volume, weight and energy
consumption.
Resonant topologies are an attractive solution for such HV-generators due to their quasi-sinusoidal
voltage and current waveforms and soft-switching features, which are favourable to reduce
electromagnetic interference and losses. Among all the topologies, the LCC resonant converter shows
most desirable features, including natural commutation for BJT, GTO and SCR devices, if the
switching frequency is lower than the resonant frequency, and zero voltage switching for MOSFETs,
if the switching frequency is higher than the resonant frequency. Besides the above features, the LCC
resonant converter shows additional merits. First, the voltage conversion characteristics enable an
operation in wide output voltage, power and load ranges. Secondly, a proper design of a LCC resonant
converter can make even use of the parasitics of HV-transformer and capacitors, such as leakage
inductances and stray capacitances, thus allows the control of the static and dynamic voltage stress
across HV-rectifiers and results in smaller tank size of Ls and Cp. A number of high-power high-
voltage applications adopting LCC resonant converter demonstrate its practicability and effectiveness
in this field [2].
It is well known that voltage multiplier circuits can be used for generating high output voltage. The
losses and size of the multiplier circuits do not exceed the savings made on the transformer, if the
number of voltage multiplier stages is limited to 3-5 [3]. Fig. 1 shows the circuit diagram of the LCC
resonant converter: The zero voltage switched LCC-circuit is connected with a symmetrical threestage voltage multiplier rectifier via a step-up transformer, the shown load consists of a capacitance of
the cable under test and a resistor for discharging.
Fig. 1: Circuit diagram of LCC resonant inverter, HV-transformer and symmetrical three-stage voltage
multiplier rectifier (each of the shown diode consists of 10 single diodes connected in series).
Investigations showed that a regulation with only one control variable cannot meet the wide output
voltage demands in conjunction with wide output load range. In this paper, both the switching
frequency and the duty cycle are adopted as control variables. Refer to Section 2 for the details.
This paper is organized as below: Section 2 presents the steady-state characteristics and the equivalent
simplified circuit of the original LCC resonant converter. In Section 3, the small-signal equivalent
circuit model of LCC resonant converter is given. Based on that, the full-order and reduced-order
control-to-output-current transfer functions are derived. Section 4 presents the current mode controller
design process. Section 5 provides the corresponding verification results. Finally, the conclusions are
stated in Section 6.
2 Steady-State Characteristics and System Simplification
In order to derive the small-signal equivalent circuit model for controller design, the original circuit
depicted in Fig. 1 is simplified as the follows. Firstly, the original capacitive load of the cable under
test and the resistive discharge load are combined and replaced by a varying equivalent resistive load
Ro’, which is corresponding with each quiescent operating point. Secondly, the three-stage
symmetrical voltage multiplier rectifier is simplified to a one-stage symmetrical rectifier since the
voltage across the capacitors of each stage is proportional to the final output voltage [3].
(1)
u k 1 = u o ' 2 m , u ki = u o ' m , u gj = j ⋅ u o ' m
(m: stage-number; j = 1~m; uki = ukia or ukib; i = 2~m)
The average value of all the diode currents is same for each stage [3]. This can be explained simply by
the fact that the output DC current can only flow via the two arms of the diode bridge in a symmetrical
multiplier rectifier.
I avg= I o' 2
(2)
Thirdly, the transfer ratio of HV transformer is simplified from n to 1. As a result, the equivalent
simplified circuit is shown in Fig. 2. The equivalent output current io, output voltage uo and output
resistance Ro, referred to the original circuit, are respectively:
u '
R '
(3)
i o = m ⋅ n ⋅i o ' , u o = o , R o = 2 o 2
m⋅n
m ⋅n
The voltage conversion ratio of LCC resonant converter vs. switching frequency and duty cycle are
shown in Fig. 3. The voltage conversion ratio is defined by (4); the switching frequency is normalized
to the natural resonant frequency of the converter, which is defined by (5). The characteristic
impedance and the quality factor of the resonant tank are given by (6). Obviously, the output voltage
can be adjusted by modulating the switching frequency or the duty cycle. As mentioned before, the
output voltage is in the range from a few to hundreds of kV, and the equivalent resistive load of the
cable under test has also a wide range. From Fig. 3, it can be seen that for low voltage conversion ratio
M or high quality factor Q, the modulation of duty cycle in the range 0-95 % can meet the system
demands. However, for high voltage conversion ratio M combined with low quality factor Q, the
switching frequency has to be varied, but it has to be considered that the switching frequency is
limited to 27-40 kHz due to the design of the HV-transformer and selected diodes in multiplier
rectifier circuit. Fig. 3 shows the allowed operation range as the shaded area with boundary operating
points OP1-OP8, which are determined by the specified output voltage range, load range and
modulation limit of control variables. Parameters of the operating points are listed in Table I.
Fig. 2: Equivalent simplified circuit diagram of LCC resonant converter
(a)
(b)
Fig. 3: Voltage conversion ratio of LCC resonant converter vs.
(a) duty cycle (b) normalized switching frequency
Table I: Parameters of Boundary Operating Points OP1-OP8
Control
Variable
Switching
Frequency
Duty cycle
M=
Operating
Point
OP1
OP2
OP3
OP4
OP5
OP6
OP7
OP8
Q
2.58
5.81
2.58
2.58
5.81
8.88
2.58
8.88
fsn
d
1.046 0.95
1.046 0.95
0.893 0.95
1.046 0.95
1.046 0.95
1.046 0.503
1.046 0.025
1.046 0.025
Uo
Uo '
=
U in m ⋅ n ⋅ U in
(4)
f sn =
fs
,
f0
f0 =
1
,
2π Ls C R
Z=
Ls
,
CR
Q=
R '
Ro
= 2 o2
Z m ⋅n ⋅Z
CR =
Cs ⋅ C p
Cs + C p
,
ω s = 2πf s ,
ω0 = 2πf 0
(5)
(6)
3 Small-Signal Circuit Model and Reduced-Order Transfer Functions
The small-signal circuit model of Fig. 2 is derived by using generalized averaging method [8] and
extended describing functions [6]. Since the current through the inductor Ls and the voltage in the
series capacitor Cs are predominantly sinusoidal, it is accurate enough to approximate them with their
fundamental terms of the Fourier series:
iL (t ) ≈ iLs (t ) ⋅ sin(ωs t ) + iLc (t ) ⋅ cos(ωs t )
(7)
u s (t ) ≈ uss (t ) ⋅ sin(ωs t ) + usc (t ) ⋅ cos(ωs t )
The output voltage is a slow varying magnitude with respect to the switching frequency, so it can be
approximated by its DC term of the Fourier series: uo(t). Hence, the state variables can be defined as:
(8)
x (t ) = {iLs (t ), iLc (t ), u ss (t ), u sc (t ), uo (t )}
A corresponding small-signal equivalent circuit model is shown in Fig. 4. The variables in Fig. 4 are
the small-signal deviations of the state variables and input variables. The steady-state solutions of the
LCC resonant converter are provided in Appendix A, the parameters of the small-signal circuit model
are given in Appendix B. The control-to-output-current transfer functions are derived by (9). The low
frequency gains, Gf0 and Gd0, are the product of 1/Q and the slope of the DC conversion ratio curve at
the given operating point (refer to Fig. 3 and (10)).
Fig. 4: Small-signal equivalent circuit model of LCC resonant converter
Gif (s ) =
G f 0 [1 − 2ξ fz1, 2 ( s ω fz1, 2 ) + ( s ω fz1, 2 ) 2 ]
Δion
=
Δf sn (1 + s ω fp1 )[1 + 2ξ fp 2,3 ( s ω fp 2,3 ) + ( s ω fp 2,3 ) 2 ][1 + 2ξ fp 4,5 ( s ω fp 4,5 ) + ( s ω fp 4,5 ) 2 ]
(9)
Gd 0 (1 + s ω dz1 )[1 + 2ξ dz 2,3 ( s ω dz 2,3 ) + ( s ω dz 2,3 ) 2 ]
Δi
Gid (s ) = on =
Δd (1 + s ω dp1 )[1 + 2ξ dp 2,3 ( s ω dp 2,3 ) + ( s ω dp 2,3 ) 2 ][1 + 2ξ dp 4,5 ( s ω dp 4,5 ) + ( s ω dp 4,5 ) 2 ]
Gf 0 =
Gd 0
ΔI on
ΔU o
U in ΔM
1 ΔI o
1
Z ΔM 1 ΔM
=
⋅
=
⋅
=
⋅
=
⋅
= ⋅
Δf sn I B Δf sn I B ⋅ R0 Δf sn I B ⋅ R0 Δf sn R0 Δf sn Q Δf sn
(10)
ΔI
ΔU o
U in ΔM
1 ΔI o
1
Z ΔM 1 ΔM
= ⋅
= on =
⋅
=
⋅
=
⋅
=
⋅
Δd
I B Δd I B ⋅ R0 Δd
I B ⋅ R0 Δd R0 Δd Q Δd
The output current is normalized to the assumed supply current, which is defined as:
U
ΔI
Δi
(11)
ΔI on = o , Δion = o , I B = in
Z
IB
IB
Parameters of (9) at operating points OP1-OP3, OP5-OP7 are listed in Table II. OP4 and OP8 will not
be considered, since their transient characteristics are among those of other boundary points.
Table II: Parameters of Control-to-Output Current Transfer Functions
Control
Variable
Operating
Points
OP1
Switching
OP2
Frequency
OP3
OP5
Duty
OP6
Cycle
OP7
ωfz1,2 or ξfz1,2
ωdz1
ωdz2,3
or
Gf0 or
ξdz2,3
Gd0
(1/s)
(1/s)
-1.50
N/A
3.04E+05 0.002
-1.37
N/A
3.04E+05 0.002
-5.78
N/A
2.75E+05 0.005
0.026 2.64E+05 2.30E+05 0.326
0.163 2.33E+05 2.37E+05 0.33
0.556 4.48E+05 2.06E+05 0.027
ωfp1 or
ωdp1
(1/s)
3877.58
1721.89
3877.58
1721.89
1126.59
3877.58
ωfp2,3 or
ωdp2,3
(1/s)
7.97E+04
7.97E+04
4.30E+04
7.97E+04
7.97E+04
7.97E+04
ξfp2,3
or
ξdp2,3
0.018
0.009
0.02
0.009
0.009
0.009
ωfp4,5 or
ωdp4,5
(1/s)
4.23E+05
4.20E+05
3.86E+05
4.23E+05
4.23E+05
4.23E+05
ξfp4,5
or
ξdp4,5
0.0035
0.002
0.002
0.0017
0.002
0.0017
The corresponding pole-zero plots of the full-order control-to-output-current transfer functions at
operating points OP1-OP3, OP5-OP7 are shown in Fig. 5. Conclusions can be drawn from Table II
and Fig. 5 that in the studied frequency region, Gif(s) has two Right Half Plane (RHP) zeros (ωfz1,2) and
five Left Half Plane (LHP) poles (ωfp1, ωfp2,3 ,ωfp4,5), while Gid(s) has three LHP zeros (ωdz1, ωdz2,3) and
five LHP poles (ωdp1, ωdp2,3 ,ωdp4,5). Among them, ωfp2,3 or ωdp2,3 are beat frequency poles and determine
system beat frequency dynamics, while ωfp1 or ωdp1 determines the low frequency dynamics. Since all
the zeros (ωfz1,2 , ωdz1 and ωdz2,3) and one pair of poles (ωfp4,5 or ωdp4,5) are larger than or almost the
same as the resonant frequency (ω0 ≈ 2.4·105 /s), which have less effect on system dynamics or control
loop design, they will be ignored. Only the low frequency pole (ωfp1 or ωdp1) and beat frequency poles
(ωfp2,3 or ωdp2,3) are considered. The reduced-order transfer functions for switching-frequency-tooutput-current Gif’(s) and duty-cycle-to-output-current Gid’(s) are derived:
Gif ' ( s ) = G f 0 {(1 + s ω fp1 )[1 + 2ξ fp 2,3 ⋅ ( s ω fp 2,3 ) + ( s ω fp 2,3 ) 2 ]}
Gid ' ( s) = Gd 0 {(1 + s ω dp1 )[1 + 2ξ dp 2,3 ⋅ ( s ω dp 2,3 ) + ( s ω dp 2,3 ) 2 ]}
(12)
Fig. 5: Pole-zero plots of the original control-to-output-current transfer functions at operating points
OP1-OP3 and OP5-OP7. Poles are black, zeros are red.
(a)
(b)
Fig. 6: Comparison between the original and reduced-order control-to-output current transfer functions
(a): OP1-OP3 with switching frequency control, (b): OP5-OP7 with duty cycle control.
Solid: Original transfer functions, Dashed: Reduced-order transfer functions.
Fig. 6 shows the comparison of original and reduced-order control-to-output-current transfer functions
in boundary cases. The conclusions can be drawn from the figure: in the studied region, there is almost
no difference in the magnitude and phase comparisons between original and the reduced-order transfer
functions with frequency control. In duty cycle modulation region, both magnitude bode plots are
nearly same in the whole studied region. However, some differences exist in the phase comparison at
high-frequency region, but they have negligible effect on the closed-loop design. From these
conclusions, it can be ensured that a current mode controller design on basis of the simple reducedorder transfer function is feasible.
4 Controller Design
The loop gain method [9] has been adopted for the closed-loop design. The loop gains for switchingfrequency-to-output-current and duty-cycle-to-output-current are (refer to Fig. 7):
L f ( s ) = Gcf ( s ) ⋅ Gif ' ( s ) ⋅ H ( s)
(13)
Ld ( s ) = G cd ( s ) ⋅ Gid ' ( s) ⋅ H ( s )
Based on reduced-order transfer functions, two simple and commonly used PI compensators have been
employed. They have the following forms for switching frequency or duty cycle control, respectively.
K cf ⋅ 1 + s / ωcf
Gcf ( s ) =
s
(14)
K cd ⋅ (1 + s / ωcd )
Gcd ( s ) =
s
The position of the zeros (ωcf, ωcd) and the gains (Kcf, Kcd) need to be designed. By adjusting such
compensator parameters, we can maximize the control bandwidth and maintain the phase margin at
about 45°. Attention should be paid to the adjustment of the two zeros ωcf and ωcd, which are
correlative with the adjusted frequency of the switching frequency and the duty cycle, are equal in this
application and limited by the current switching frequency. Due to this reason, ωcf and ωcd can be
denoted as one: ωc. The loop gains for frequency control and duty cycle control at operating points
OP1-OP3, OP5-OP7 are shown in Fig. 8. It can be seen from Fig. 8 that both the phase margins and
gain margins are adequate, which ensure the stability of the converter in entire operating region.
However, there has an intrinsic shortcoming: The control bandwidth drops significantly with changed
operating points. In this application, such shortcoming is more obvious in duty cycle modulation
region. This phenomenon can be explained by the fact that the low-frequency gains (Gf0 and Gd0) of
the control-to-output-current transfer functions, which are determined by the quality factor and the
slope of the DC curve, are much different at various operating points (refer to Fig. 3). For example, the
low-frequency gain difference is about 26 dB between operating points OP5 and OP7 (refer to Fig. 6).
Hence, it is desirable to adopt some nonlinear control schemes to schedule the compensators’ gain for
performance improvement.
(
)
Fig. 7: Average mode output current control block diagram
In the actual system, a two-loop control diagram is adopted, which consists of an inner current control
loop and outer voltage control loop, as shown in Fig. 9. The details of outer voltage control loop are
not included in this paper. From Fig. 9, it can be seen that an estimator is adopted for the output
current in order to substitute a direct measurement, which would cause a very costly sensor due to HV
applied. From the small-signal circuit model, the estimator can be derived, which is correlative with
the output voltage uo(t), peak value of resonant current iLP(t), parallel capacitor Cp and the switching
frequency fs(t):
iLP (t ) − π ⋅ f s (t ) ⋅ C p ⋅ uo (t )
(15)
iest (t ) =
π
From Fig. 9, we can also see that there has only one compensator Giu(s) in the inner current control
loop, which is generated based on the combination of the aforementioned two compensators, Gcf(s)
and Gcd(s). Since the two zeros (ωcf, ωcd) are equal and replaced by ωc, Giu(s) can be obtained:
K ⋅ (1 + s ωc )
(16)
Giu ( s ) = iu
s
The primary compensator gains Kcf, Kcd can be expressed by Kiu and two newly introduced parameters
Kf and Kd:
K cf = K iu ⋅ K f , K cd = K iu ⋅ K d
(17)
The compensator Giu(s) generates an auxiliary control parameter μ. The actual control variables, fs and
d, are linear functions of μ, which have the slope of Kf or Kd, respectively. In this application, only one
control variable will be adjusted at the same time (refer to Fig. 3 and Fig. 9). This combination ensures
the stability of the closed current control loop.
(a)
(b)
Fig. 8: Closed-loop control-to-output-current transfer functions.
(a) With frequency control. (b) With duty cycle control.
Fig. 9: Two-loop control diagram comprising average mode current controller
5 Verification
Before the launch of the VLF HV test generators, two prototypes were built first. One is a simplified
equivalent power prototype, which consists of LCC resonant inverter, 1:2 transformer, one-stage
symmetrical voltage multiplier rectifier and a corresponding resistive load. This scaled-down
prototype was built and measured in order to verify the system structure and controller design. The
corresponding simulation and experimental verification on this simplified prototype will be shown
later. The other prototype consists of LCC resonant inverter, 1:15 HV transformer, three-stage
symmetrical voltage multiplier rectifier, the resistive discharge circuit and an equivalent resistive load.
This prototype is a real VLF HV generator and used to verify all the design specifications. The details
of the experimental verifications on this prototype are not included in this paper. Photos of both
prototypes are shown in Fig. 10, each part of them is also indicated.
(a)
(b)
Fig. 10: Two prototypes of LCC resonant converter
(a) Scaled-down prototype with 1:2 transformer and one-stage multiplier rectifier
(b) Prototype with 1:15 transformer and three-stage multiplier rectifier
Before the measurement in the simplified prototype, the corresponding large-signal simulations have
been executed. Fig. 11 shows selected results. The cases are set as the following: a) referenced output
current step changes from 2 A to 4 A at constant output voltage (440 V) condition; b) output voltage
step changes from 880 V to 3000 V, while the referenced output current is kept constant at 4 A. It can
be seen from Fig. 11 that for the specified step reference, the estimated output current can follow the
reference signal with the settling time less than 1 millisecond and has almost no overshoot; for a large
scale output voltage step change, the undershoot of the estimated output current is about 15 % and the
settling time is about 1 millisecond.
(a)
(b)
Fig. 11: The large-signal simulations of the closed current control loop
The corresponding experimental measurements are executed on the aforementioned simplified
equivalent power prototype. Fig. 12 shows the results, which represent the process from initial state to
the referenced steady states of the control variables: fs(t) and d(t), resonant current iL(t) and estimated
output current iest(t), respectively. The cases are set as the following: a) referenced output current is set
to 2 A at constant referenced output voltage (440 V) condition; b) referenced output current is set to
4 A at constant referenced output voltage (880 V) condition. Comparing Fig. 12 with Fig. 11, we can
see that the referenced output current and voltage conditions in Fig. 12 (a) and (b) are same as the
setting conditions before the step changes in Fig. 11 (a) and (b) (the two framed areas), respectively.
The experimental measurements in Fig. 12 agree well with the predicted estimated output current in
framed cases of Fig. 11, which have no overshoot and the settling times are less than 1 millisecond.
These large-signal simulations and experimental measurements on prototype support the conclusions
of above analyses and controller design.
(a)
(b)
Fig. 12: Closed-loop current mode controller verification through measurements on prototypes
6 Conclusion
The topology of LCC resonant inverter followed by symmetrical three-stage voltage multiplier circuit
can be adopted in the high voltage very low frequency test systems. The modulation of the switching
frequency and the duty cycle are combined to enlarge output voltage and load ranges. In the studied
frequency range, it is confirmed that the reduced-order transfer functions have almost the same
dynamics as those of the original complex ones, which enables a simpler linear controller design. The
analyses and design are verified by simulations and experimental measurements on prototype.
Due to the wide ranges of output voltage and load, it is difficult to balance the phase and gain margins
and control bandwidth of closed-loop transfer functions using a conventional PI controller, especially
in the duty cycle modulation region. Some nonlinear control schemes are suggested for improving the
performance in the future.
Appendix A
I Ls =
8U e K 2
2
2
4 K1 + K 2
(A1)
I Lc =
16U e K1
2
2
4 K1 + K 2
(A2)
I Lc
C sω s
I
= − Ls
C sω s
U ss =
(A3)
U sc
(A4)
Uo =
I LP R0 (1 − cos(θ ss ))
2π
2
I LP = I Ls + I Lc
2
⎛ πD ⎞
U e = ω s C pU in sin ⎜
⎟
⎝ 2 ⎠
2
K1 = πα + γ ss − παC s Lsω s
(A5)
(A6)
(A7)
(A8)
(
K 2 = −2 sin 2 (θ ss ) + παCs Rsωs
sin (2θ ss )
γ ss = π − θ ss +
2
⎛
2π ⎞⎟
θ ss = 2tg −1 ⎜
⎜ R0C pω s ⎟
⎝
⎠
C
α= p
Cs
)
(A9)
(A10)
(A11)
(A12)
Appendix B
Kv =
4
π
sin(
π
2
D)
Ed = 2U in cos(
Es = Ls I Lcω0
Ec = Ls I Lsω0
Z L = Lsω s
Gs = Csωs
J c = CsU ssω0
J s = CsU scω0
U I
H c = o Ls2
Ro I LP
Hs =
U o I Lc
2
Ro I LP
π
2
(B1)
D)
(B2)
(B3)
(B4)
(B5)
(B6)
(B7)
(B8)
(B9)
(B10)
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