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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 21, NO. 3, MAY 2006
Multiphase Digital Pulsewidth Modulator
Raymond Foley, Richard Kavanagh, Senior Member, IEEE, William Marnane, Member, IEEE, and
Michael Egan, Member, IEEE
Abstract—This letter describes a digital pulsewidth modulator
that enables the generation of a large, adjustable number of
pulsewidth modulated (PWM) outputs of programmable duty
cycle and dead time, yet requiring just a small, fixed architecture.
The design achieves a resolution of 255 ps using a composite PWM
strategy that also minimizes clock frequency and area. It provides
a practical solution to the problem of efficiently generating multiple high-resolution gate-drive signals and is particularly suited to
the next generation of synchronously switched multiphase voltage
regulator modules.
Index Terms—DC–DC power conversion, digital control,
field-programmable gate arrays (FPGA), switched-mode power
supplies.
I. INTRODUCTION
IGITAL methods are being used with increasing frequency in the field of power electronics [1], enabling
designers to meet evolving performance specifications, achieve
improved efficiency, and implement additional functionality
with greater ease. In particular, it is expected that digital control
will be the regulation method of choice for voltage regulator
modules (VRMs) in the near future [2]. This letter deals with
a key issue in digital VRM control—pulsewidth modulation
(PWM)—approached from the perspectives of area-efficiency
and enhanced resolution. A novel multiphase digital pulsewidth
modulator (DPWM) is proposed. It uses a small, fixed architecture to generate high-resolution versatile gate-drive signals
and incorporates on-line calibration circuitry. Experimental
verification using a field-programmable gate arrays (FPGA) is
also described.
D
Fig. 1. Possible implementations of an 8-to-1 MDL decomposition, showing
A and A
totals for each branch.
resolution. However, even this approach reaches a practical
limit in terms of area and clock frequency as the underlying
resolution is increased.
B. Heterogeneous DPWM
An r-to-1 multiplexer/delay-line (MDL) pair may be decomposed into a logically equivalent chain of
2 -to-1 MDL
. The index represents the position
pairs, where
of a pair in the chain from output
1 to input
. The
total distributed multiplexer (MUX) area may be quantified in
terms of primitive 2-to-1 MUX components. Here
(1)
where 2
is the number of 2-to-1 primitives required to
implement each 2 -to-1 MUX. The number of delay elements
at any level of the MDL chain may be found using the recursion
II. HIGH RESOLUTION TIMING GENERATION
A. Existing Architectures
Counter-comparator [3], [4] and delay-line [5], [6] methods
have been used to generate PWM signals. Unfortunately, these
methods can be unsuited to very-high resolution applications
since either an excessive clock frequency or implementation
area is needed. Techniques such as dithering [7] and –
PWM [8] can improve the time-averaged resolution but may
add an extra ac ripple to the converter output. Instead, the
hybrid counter-with-delay-line approach of [9], [10] seems to
reach a good compromise between area, clock frequency and
Manuscript received November 30, 2005; revised February 21, 2006. This
work was supported by the Irish Government through Enterprise Ireland Contract ATRP/01/314. This work was presented in part at the 36th Annual IEEE
Power Electronics Specialists Conference, Recife, Brazil, June 12–16, 2005.
Recommended by Associate Editor J. Sun.
The authors are with the Power Electronics Research Laboratories, Department of Electrical and Electronic Engineering, University College Cork, Cork,
Ireland (e-mail: rfoley@pei.ucc.ie).
Digital Object Identifier 10.1109/TPEL.2006.875569
(2)
where
therefore
1. The total number of distributed delay elements is
(3)
A tree displaying all the possible implementations of an
8-to-1 MDL decomposition is shown in Fig. 1. It may be shown
is minimized and
maximized when
1, i.e.,
that
no decomposition of the original MDL pair, while
is maxminimized when
1,
imized and
implying full decomposition.
i.e.,
This tradeoff is the key to minimizing the area of the
pulsewidth modulator: a semi-decomposed structure is required whose elements are chosen to satisfy area, linearity and
monotonicity criteria. When the area consumed by a single
delay element is comparable to that required to implement a
MUX primitive, an area-minimizing decomposition may be
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 21, NO. 3, MAY 2006
843
Fig. 2. Heterogeneous DPWM architecture.
Fig. 4. Relationships between the phases of an eight-phase converter with syn( ) to
( ) represent top-switch gate-drive inchronous rectifier. Signals
puts, while signals ( ) to ( ) represent bottom-switch gate-drive inputs.
S t
Q t Q t
S t
III. MULTIPHASE PULSEWIDTH MODULATOR
In an -phase interleaved quasi-square-wave buck converter
[12], with phase separation of seconds and duty-cycles in each
phase assumed to be equal, it follows, in general, that
(4)
k
Fig. 3. Area tradeoff between ring oscillator/MUX ( -bit) and auxiliary delay
line ( -bit). The minimum area occurs when = .
l
k l
computed. The proposed heterogeneous DPWM, shown in
Fig. 2, extends the hybrid DPWM [9], [10] by adding an -bit
auxiliary delay stage in series with a -bit ring-oscillator/MUX,
creating a semi-decomposed MDL structure [11]. In this de7 is chosen and, from Fig. 3, the minimum area
sign,
. However, to guarantee
criterion may be satisfied when
monotonicity with such fine time intervals, a 2-b auxiliary delay
line has been found to achieve a more satisfactory performance
and is used here, in conjunction with a 5-b ring-oscillator delay
line, without an excessive area penalty. (On an FPGA, further
shrinking may be realized by substituting a group of high-resolution elements with a single higher latency component, since
the concept of fixed resource allocation is more crucial than
actual area consumption. However, this is not a required step.)
In this design, the auxiliary delay-line elements are look-up
tables (LUTs), which are found to have an average latency
255 ps (at a die temperature of 30 C)—approximately
25% of that of the flip-flops used in the ring-oscillator delay
line. The operation of the circuit is similar to that of the hybrid
DPWM, but it achieves considerably enhanced resolution with
a comparable area requirement.
where
and
are the respective instantaneous values
of the top- and bottom-switch gate-drive signals in phase , and
(5)
is the switching frequency. Though there are many
where
individual switching events per period, there are just four dis,
,
and
, as shown
tinct event types:
in Fig. 4. Each event type occurs in an ordered sequence—a
fact that can be exploited to facilitate asynchronous time sharing
of timing-generation components, rather than using a separate,
area-intensive dedicated timing generator for each edge/phase,
as has been done up to now [5], [9], [13]. The architecture shown
in Fig. 5 is used to accomplish this [11].
The timing-generation circuit consists of four heterogeneous
DPWMs. Each sub-DPWM is required to have identical timing
characteristics, because it is desirable that the outputs be accurately matched. To achieve this, just one delay line is used
to establish all timing events—further optimizing the area. In
each switching cycle, the memory is updated with an array of
event-data vectors, representing the required switching instants
phases. This data is grouped by
of each of the converter’s
event type and fed to one of the four sub buses of the bus array,
, such that a sub bus carries data corresponding to just one
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844
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 21, NO. 3, MAY 2006
Fig. 6. All-digital phase-locked loop, used to lock the DPWM switching frequency to that of a reference clock.
Fig. 5. Multiphase DPWM architecture.
event type. Each sub bus is updated times per cycle when its
memory bank is incremented (via the event bus) due to the previous event of the same type having been resolved, i.e., a pulse is
generated at the output of the corresponding “AND” gate. Each
signal of the event bus is a train of pulses that must be directed
to the correct or ports of the 2 output latches to generate
the PWM waveforms. This is done using four 1-to- counters, which keep track of each of the event bus signals. When
a counter output is decoded into a 1-of- format, the resulting
signals may be used to enable the or port of a particular
output latch before its next expected event.
The only practical limit to the number of phases is the finite
time, , it takes to increment the memory from one value to
. In this implementation
the next. For correct operation
the 1-to- counters have a maximum value of , which may
be set by the user, enabling the number of output phases to be
adjusted either dynamically, for phase shedding at light loads, or
on an application-specific basis. The average frequency of these
counters is equal to the product of the number of phases and the
converter switching frequency.
IV. CALIBRATION
If the rising edge of signal
is viewed as the time origin
in each period, each subsequent event in the switching cycle
occurs some programmable interval thereafter—including the
next rising edge of the signal itself. By detecting this edge and
resetting the main counter and the ring oscillator at this instant,
a new cycle is initiated. Thus, the circuit behaves like a digitally
controlled oscillator (DCO). Since the switching period is now
programmable, variable frequency operation is accomplished.
, is
The range of possible switching frequencies,
(6)
where is the latency of a single auxiliary delay-line component
and is the aggregate number of bits of resolution of each subDPWM circuit.
Frequency calibration is achieved using an all-digital phase
locked loop (DPLL), which may be constructed using a DCO,
an up-down counter (acting as a loop filter, the output of which
determines the switching period) and a digital phase detector
(DPD) [14], as shown in Fig. 6. The DPD used here compares
and a reference clock.
the phases of the rising edge of
rising edges
When it is detected that there are two or more
per period of the reference clock then the up-down counter
is incremented, thus reducing the frequency of the DCO. The
rising edge
DCO frequency is increased when there is one
(or none) per period of the reference clock [15]. When both
signals have locked, the switching period varies within a range
of adjacent values, resulting in jitter, and thus inaccuracy, in the
calibration cycle. This is due to the simple phase detector circuit
so that the counter output
having a single output
enters a limit cycle oscillation at or near lock. This is exacerbated
by the asynchronous reset used in the DPD, the effect of which
is most acute near to lock when the reference clock and
edges occur almost simultaneously: timing violations then cause
signal to be resolved incorrectly. This results in
the
limited, though discernible, excursions about the ideal switching
period value. However, the magnitude of this jitter has been
measured to be within the tolerances of typical VRM output filter
components, so its effect may be disregarded in this application.
V. EXPERIMENTAL VERIFICATION
The multiphase heterogeneous-DPWM architecture described in this letter has been implemented on a Xilinx Virtex
XC2V3000-4FG676 FPGA. The 32-element ring-oscillator
delay lines were constructed using the dedicated flip-flops
available on this device. These have a latency of approximately
1 ns, measured at a die temperature of 30 C. This time interval is further divided into finer-grain increments, with an
average value of 255 ps at the same temperature, using the
auxiliary delay stages, thus providing 11 b of resolution at a
switching frequency of approximately 1.9 MHz. These fine
time increments are illustrated in Fig. 7, where a sequence
of five top-switch falling edges are shown as the duty-cycle
is changed between a number of consecutive values. The
variation of output frequency with temperature is of interest,
since the ambient temperature in which the circuit should
operate can vary substantially. This has been investigated using
an on-die temperature sensor with ambient heating, and the
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 21, NO. 3, MAY 2006
845
Fig. 9. Pulsewidth modulated output of the implemented eight-phase heterogeneous DPWM operating at a switching frequency of 1.9084 Mhz per phase.
TABLE I
SUMMARY OF CIRCUIT PERFORMANCE
Fig. 7. Waveforms numbered 1–5 show the falling edge of a single top-switch
output as the duty cycle is varied between five consecutive values, thus demonstrating the high resolution of the heterogeneous-DPWM architecture.
VI. CONCLUSION
Fig. 8. Normalized output frequency response versus die temperature.
frequency-to-temperature response of the circuit, normalized at
30 C, is shown in Fig. 8. At approximately 0.11% per C, the
measurements correspond well to similar experiments in the
literature [16]. However, calibration of the delay line during
normal operation may be used to overcome the temperature
dependency of the output frequency.
The DPWM was configured to eight phases to demonstrate a
typical output, shown in Fig. 9—a screen shot of a logic analyzer
display, showing 16 top- and bottom-switch gate-drive waveforms. The number of phases is not confined to this value, however, and may be adjusted as required. The eight-phase design
(excluding the memory) is fully implemented in just 203 LUTs,
and careful multiplexer placement using interleaving techniques
ensures monotonicity and excellent linearity. The required imof that of an archiplementation area is approximately 3 2
tecture not optimized in this way, where, again, is the number
of converter phases. Some performance figures for this circuit
are summarized in Table I.
A multi-output DPWM has been introduced for use with multiphase interleaved dc–dc buck converters, generating versatile
waveforms with variable switching frequency, programmable
dead times, adjustable phasing and online calibration capability. This is achieved using a novel architecture that also
exploits the phased nature of the switching signals required
by this topology to minimize the overall area consumed. The
heterogeneous-DPWM structure, on which the design is based,
achieves a resolution of 255 ps, but without a large clock-frequency or silicon-area requirement.
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