Power Supply Noise Reduction in Broadcast-Based Compression Environment for At-Speed Scan Testing Presenter: Chun-Yong Liang Advisor: Jiun-Lang Huang Graduate Institute of Electronics Engineering National Taiwan University Abstract — Power supply noise induced test yield loss is challenging at-speed scan testing. This work is the first attempt to reduce power supply noise for at-speed testing in the broadcast-based test compression environment. The core technology is the X-slice creation technique; it comprises the scan-chain skew-insertion hardware and the skew configuration generation algorithm. With the created X-slices, the efficiency of X-slice filling to lower the launch cycle switching activities is improved. Effectiveness of the proposed technique is validated with ISCAS89 and ITC99 benchmark circuits. Skew insertion hardware & timing diagram (a) The skew-insertion hardware comprises the enable generator, the scan-in data buffer, the control registers, and the MUX network. (b) The scan operation consists of three steps, load skew configuration, initial scan-in data buffer, and scan. Skew insertion example (a) The scan chain without any skew insertion where flip-flops that receive the same scan-in bit are connected by a dashed line. (b) Scan chain 2 is skewed by one cycle. (c) Aligns scan cells according to the new linear dependency. Launch-WSA reduction flow The first step is to identify patterns that violate the launch-WSA constraint and the set of faults that are exclusively detected by these patterns. The flow then starts modifying each pattern . The first stage is the simple slice-flipping heuristic without X-slice creation; the reason is to reduce overhead. The second stage applies the proposed X-slice creation technique to patterns that still fail the constraint. X-slice creation example Although the ratio of X-bits is 75%, there is only one Xslice. If scan chain 2 is skewed by one cycle, the available X-slice count increases from one to three.