2013 18th IEEE European Test Symposium (ETS)
!
!
A Layout-aware X-Filling Approach for Dynamic Power
Supply Noise Reduction in At-Speed Scan Testing
Saman Kiamehr, Farshad Firouzi and Mehdi B. Tahoori
Karlsruhe Institute of Technology (KIT)
76131 Karlsruhe, Germany
Email: {kiamehr, farshad.firouzi, mehdi.tahoori}@kit.edu
Abstract—Power Supply Noise (PSN) has emerged as an
important resilience issue in nano-scale CMOS technology. Due
to simultaneous switching of various gates, the actual supply
voltage seen by individual gates inside the circuit might be lower
than the nominal supply voltage, leading to extra delays. Since
in at-speed scan testing simultaneous switchings are higher than
the functional mode, test invalidation due to excessive PSN can
happen, which may impact yield loss. In this paper, we propose a
Linear Programming-based X-filling approach to minimize PSN
in at-speed scan test by assigning appropriate values to X-bits
in partially specified test patterns. In this paper, spatial and
transition time correlations due to circuit layout, power mesh,
and netlist are taken into account to increase the accuracy of
dynamic PSN estimation and for the first time the delay of the
circuit is directly targeted to minimize the effect of PSN during
the at-speed scan test.
I. I NTRODUCTION
In nanoscale VLSI circuits, the actual supply voltage level
seen by individual devices is lower than the nominal voltage
due to switching current. This phenomena which is called
Power Supply Noise (PSN), causes the gate delay to increase and eventually reduces the system performance. By
technology scaling, the supply voltage scales, however, the
threshold voltage remains relatively constant [1]. As a result,
the sensitivity of the gate delay to the PSN increases. A 10%
voltage drop results in a 8% increase in the gate delay in
180nm technology [2], while, the delay variation for the same
amount of voltage drop (10%) is around 30% for 130nm
technology [3]. For 90nm technology, 4% gate delay variation
is induced due to 1% variation in supply voltage [4].
Smaller feature sizes and higher operating frequencies have
made timing-related defects one of the major sources of circuit
failure in nano-scale digital circuits. At-speed scan testing
is the most widely used strategy for delay testing to ensure
that fabricated VLSI chips meet the timing requirements. PSN
severely challenges the Launch Off Capture (LOC) at-speed
scan testing due to the higher switching activity of the entire
circuit during test mode in comparison with normal mode [5].
The PSN effect in test mode is 16% larger than normal mode
based on the analysis of [6]. Thereby, test-induced yield loss
occurs when functionally good chips fail under the test process
due to timing failure induced by large PSN during test mode.
This problem is referred to as supply noise induced yield
loss [7]. The supply noise induced yield loss is getting worse
and more costly as CMOS feature size scales and test-cycle
decreases.
There have been a number of techniques proposed to reduce
978-1-4673-6377-8/13/$31.00 ©2013 IEEE
PSN-induced malfunction in at-speed scan testing. The main
disadvantage of previous work is that, instead of directly
minimizing PSN-induced delay, they try to minimize the
effect of PSN by minimizing other metrics such as Weighted
Switching Activity (WSA) [8], [9], [10] over the entire circuit.
Moreover, most of the previous techniques do not consider the
spatial and/or temporal correlation of switching activity of the
nodes inside the circuit [11], [7] which results in an inaccuracy
in PSN-induced delay estimation.
In this paper, we propose a Linear Programming (LP) based
X-filling method to minimize the PSN-induced delay increase
during scan-test to avoid PSN-induced test yield loss. We accurately consider the temporal and spatial correlations among
switching activity of nodes. Moreover, we try to minimize the
effect of PSN on the circuit delay during the at-speed scan
delay test by considering the delay itself as the optimization
metric. Additionally, since our objective is to minimize the
delay of paths sensitized by the test pattern, the sensitization
criteria is also taken into account. Experimental results show
that our proposed technique reduces PSN-induced delay during
at-speed scan test (42% more than minimum transition xfilling) with reasonable runtime.
The rest of the paper is organized as follows. Related work
is presented in Section II. Section III summarizes the overall
flow as well as the motivation of our work. The proposed
LP-based X-filling methodology is described in Section IV.
Experimental results are demonstrated in Section V. Finally,
Section VI concludes the paper.
II. R ELATED WORK
There have been several methods targeting the PSN induced
yield loss in at-speed scan test. However, due to the space
limitation we discuss only a few of them.
a) Pattern generation and compaction: In [12], [13] an
IR-drop tolerant transition delay fault test pattern generation
method is proposed based on the Switching Cycle Average
Power (SCAP). However, the spatial correlation of switching activity is not considered in this work. A layout-aware
transition-delay fault pattern generation is proposed in [9] to
minimize IR-drop during the test. In order to minimize IR-drop
induced power supply noise, a delay test compaction method
is proposed in [8] which considers the weighted switching
activity as a metric to minimize IR-drop.
b) X-filling method: Since a large portion of the test
cube are don’t care (X) bits, X-filling can be used to minimize
!
!
G4
TT-G3
G3
Voltage
Voltage
G1 G2
time
TT-G4
Since Launch Off Capture (LOC) is the most common
clocking scheme for at-speed test, we focus on LOC in this
paper. The cycle between launch capture and capture response
is called test cycle and it is equivalent to the functional
operating frequency of the circuit. In this cycle, due to large
launch switching activity, PSN severely challenges at-speed
test. Therefore, PSN should be minimized in this cycle to avoid
test-induced yield loss.
In X-filling method, the don’t-care bits (X-bits) of test cube
are assigned in a way that the PSN is minimized. As a result,
for a partially-specified test cube with n don’t-care bits, 2n
patterns need to be considered to find the best test cube in
terms of PSN. Obviously, exhaustive search is infeasible for
intermediate and large circuits with a large number of X-bits.
The locality of switching activity is an important parameter
which has to be considered in the PSN estimation. The
switching nodes likely draw a majority of their current form
the nearest power pad. Due to presence of parasitic elements
between two switching nodes, if a switching occurs at a node
A which is far from node B in circuit layout, it has minimum
average
TT-G2
III. OVERALL F LOW OF P ROPOSED T ECHNIQUE
effect on the PSN which is seen by node B. In other words,
even two simultaneous switching of nodes which are not close
in the circuit layout, have minimum effects on each other.
Moreover, the gates which are in the same power grid, share
the same supply voltage profile (see Figure 1). These effects
are referred to as spatial correlation of PSN in this paper.
TT-G1
power supply noise. The key idea behind X-filling is to
assign an appropriate value (0/1) to an X value in a partiallyspecified test cube in such a way that IR-drop is reduced [14].
A justification-probability-based fill (JP-fill) for X-filling is
proposed in [11] to minimize IR-drop by means of minimizing
launch induced switching activity. Authors in [10] proposed a
critical path aware X-filling method to reduce IR-drop in atspeed scan test. The exploit metric in their method is WSA
considering logical distances of the gates in critical paths. An
X-filling-based technique is presented in [7] to generate test
patterns with low launch cycle power supply noise in the linear
decompressor-based test pattern compression environment. In
order to reduce IR-drop, WSA is minimized by a layout-aware
X-filling approach proposed in [15].
c) Other models and methods: A current-based dynamic
method is proposed in [16] to estimate power supply noise.
This model is then used to predict the effect of power supply
noise on path delay. Although the method has a good accuracy,
it suffers from high runtime which makes it infeasible to be
used for estimation/minimizing power supply noise. Authors
in [17], propose a method to reduce peak power supply noise
during scan chain shifting by using a partitioning technique to
reduce the flip-flop density belonging to the same test clock. A
new metric which considers Transition Time Relation (TTR)
is proposed in [18] for capture-safety checking. TTR metric,
take the temporal correlation by considering transitions that
only occur earlier than (not later than) any transition at each
on path node.
In this work, we directly target the delay of the sensitized
path during at-speed scan test as the optimization metric as
opposed to existing techniques which target other metrics such
as WSA. Moreover, we consider both spatial and temporal
correlation among switching activity of internal nodes unlike
previous approaches which only partially consider them.
time
Fig. 1. Voltage profile seen by different gates: TT-Gi: Transition Time of Gi
Additionally, the supply voltage which is seen by different
gates in the same grid is different according to their transition
times. To clarify this, consider the simple example shown in
Figure 1. In this example, the voltage levels at the transition
time of the gates G1 and G2 are different and lower than the
average voltage of their power grid. As a result, if the average
voltage is considered as their effective supply voltage, it causes
an underestimation in their propagation delay. However, the
supply voltage which is seen by G3 and G4 are higher than
the average voltage value of their corresponding power grid.
This means that, if the average supply voltage of the grid is
considered as their effective voltage in the timing estimation, it
leads to an overestimation in their delay calculation. Moreover,
the transitions which occur later (much earlier) than the
transition at a target node, have no (minimum) effect on the
the supply voltage seen by the target node. These effects
are referred to as temporal correlation of PSN in this paper.
Moreover, minimizing PSN over the whole circuit or even
over the critical paths does not necessarily reduce the test
invalidation. For this purpose, the PSN has to be minimized
over the sensitized paths during at-speed scan test.
In this paper, both temporal and spatial correlations are
considered in PSN estimation (dynamic PSN) in order to
increase the accuracy of timing analysis used in our method.
The objective is to minimize the PSN-induced delay increase
of the sensitized paths by the test (pair) cube using an Xfilling method based on Linear Programming (LP) approach.
Figure 2 shows the overall flow of this work. As shown
in this figure, for each circuit, the library cell delays and
leakage (for different load capacitance and supply voltages),
gate level netlist, layout, and the delay test patterns and their
Gate Delay &
Leakage
Gate Level
Netlist
Layout
Delay test
Patterns &
Corresponding
Sensitized Paths
LP Generator
LP Format Netlist
LP Solver
Optimized Test Vector For All Patterns
Fig. 2.
Overall flow of the proposed methodology
!
!
corresponding sensitized paths are given to an LP generator.
The LP generator, creates an LP formulation which is given to
an LP solver. The library cell delays and gate level netlist are
used to obtain possible transition times and dynamic current
of the gates in order to consider temporal correlation among
switching activity of the nodes. Moreover, the circuit layout
is used to obtain the spatial correlations. This information, in
addition to cell leakage, is used to obtain dynamic PSN. The
output of the LP solver is an optimized assignment to don’t
care bits for each test pattern which minimizes the maximum
delay over all its sensitized paths.
inputs of the CUT after the last shift clock. In the same way,
IN P U T0 is the input of CUT at the Launch Capture and is
composed of P I0 and P P I0 . It should be noted that, P P I0
is the output of Flip-Flops (FFs) after the Launch Capture
and is a function of IN P U T−∞ = {P I−∞ , P P I−∞ }. Due
to switching activity caused by changing the inputs of CUT
from IN P U T−∞ to IN P U T0 , the actual supply voltage level
seen by individual gates of CUT decreases. The objective is
to minimize delay which can be expressed as follows:
M inimize
D = max D(Pi )
(2)
IV. LP F ORMULATION
In this section, we present the proposed LP formulation for
obtaining X-filling to minimize PSN in LOC test.
where Pi s are sensitized paths for the target test pattern. The
output of the LP solver is a set of suitable values for don’t
care bits of IN P U T−∞ and P I0 .
A. Linear Programming
C. LP Constraint
Linear Programming is an optimization technique to find the
minimum or maximum of a linear objective function subject
to linear equality/inequality constraints. The LP problem can
be expressed as follows:
In this section, we present the process of obtaining all the
necessary constraint for our LP problem. To demonstrate the
LP-based methodology, all the following steps are explained
for a simple circuit which is shown in Figure 4. For the sake
of simplicity, in this example we assumed that the delay of
inverters, NAND and NOR gates are equal to 1.5 ps, 2 ps
and 2.5 ps, respectively. However, in general, the delay of the
gates can be any real number.
1) Signals before test cycle (−∞): As mentioned before
P P I0 is a function of IN P U T−∞ which is obtained by a set
of constraint. For example, as shown in Figure 4(b), The signal
value of node d at launch capture (Sd0 ) is equal to the signal
value of node h at the last shift clock (Sh−∞ ). To obtain P P I0
as a function of IN P U T−∞ , the constraint of the signal in
the first copy of the circuit (last shift clock) has to be obtained.
According to Figure 4(b):
M inimize : CT x
Subject to : Ax ≥ b
(1)
where C x is the objective function and Ax ≥ b is the set of
constraints.
T
B. Objective
A sequential Circuit Under Test (CUT) example and its
equivalent circuit model for extracting power supply noise is
depicted in Figure 3. The first part of the unrolling version
of the circuit represents the state of the circuit after the last
shift clock. The second part, is a representative of the circuit
at Launch Capture where PSN occurs.
We define IN P U T−∞ as the combination of Primary
Inputs (PIs) and Pseudo Primary Inputs (PPIs) which are the
PI
PPI
Combinational
Core
PO
PPO
Scan
FFs
Pi
Se−∞ = Sd−∞
Sf−∞ = (Sa−∞ ) (Sb−∞ )
Sg−∞ = (Sc−∞ ) (Se−∞ )
Sh−∞ = (Sf−∞ ) (Sg−∞ )
where
represents the signal value of node in the last
shift clock (first copy). However, all the constraints have to be
represented in a linear form. In order to convert the constraints
(a) A sequential CUT
a
b
U2
c
e
U3
f
U4
Last shift
clock
PI-∞
PPI-∞
Launch
Response
Capture
Capture
Power Supply
Noise
PI0
Test
Combinational
Combinational Response
Copy1
Copy2
PPI0
INPUT-∞ = (PI-∞, PPI-∞) INPUT0 = (PI0, PPI0)
PPI0 = f(PI-∞, PPI-∞)
d U1
CUT and its unrolled version
h
g
FF
(a) A sequential running example
Launch Capture
a{-∞}
b{-∞}
U2
f{-∞}
c{-∞}
U3
U1
e{-∞}
d{-∞}
g{-∞}
(b) Time-frame expansion of a Sequential Circuit to be used
for LP-formulation
Fig. 3.
(3)
−∞
Snode
a{0}
b{0}
h{-∞}
U4
d{0}
c{0}
U1
U2
U3
e{1.5}
f{2}
h{4.5,6}
U4
g{2,3.5}
(b) The unrolled version of the example
Fig. 4.
Example circuit and all possible transition times for each node
!
!
D
which are used in Equation (3) to a linear form, the constraint
of Table I are used.
Finally the constraint for P P I0 can be obtained:
SET
CLR
Q
Q
Vdd
D
SET
CLR
D
Q
Q
SET
CLR
Q
Q
D
SET
CLR
Sd0
=
Sh−∞
D
(4)
2) Signals at test cycle: Before writing the constraints of all
signals at the test cycle, the Possible Transition Times (PTT)
of all internal nodes is extracted based on the gate delays.
P T T (nodei ) = [t1nodei , t2nodei , ..., tm
nodei ],
tknodei ≤ tk+1
nodei
(5)
where tjnodei is the time at which node i may have a transition
and can be obtained by static timing analysis. According to
the Figure 4(b), node g may have transitions at times {2, 3.5}
while node f may have a transition only at time {2}. After
extracting all possible transition times for each node, the
signals at possible transition times can be obtained by a set of
equations as follows:
Se1.5 = Sd0
Sf2 = (Sa0 ) (Sb0 )
Sg2 = (Sc0 ) (Se−∞ )
Sh6 = (Sf2 ) (Sg3.5 )
Fig. 5.
(6)
t
is the signal value of node at transition time t.
where Snode
3) Transitions at test cycle: After obtaining all signal
constraints, a new set of binary variables is defined to represent
the transition of internal node at transition times.
=
=
tk−1
tk
(Snode
) ∧ (Snode
)
tk
tk
(T rnode
) ∨ (T fnode
)
LP CONSTRAINTS FOR BASIC LOGIC OPERATIONS
Function
INV
Logic operation
b = N OT (a)
NAND
c = N AN D(a, b)
NOR
c = N OR(a, b)
AND
c = AN D(a, b)
OR
c = OR(a, b)
Constraints [19]
b+a=1
c≤2−a−b
c≥1−a
c≥1−b
c ≥ 1 − (a + b)
c≤1−b
c≤1−a
c ≥ −1 + a + b
c≤a
c≤b
c≤1+a+b
c≥a
c≥b
Q
Q
All power
drawn from
highlighted grid
T imeSteps = [T S1 , T S2 , ..., T SNT ]
T S1 = [0, T1 )
T Si = [Ti−1 , Ti )
T SNT = [TNT −1 , Tcycle ]
(8)
where Tcycle is the test cycle. Moreover, it is assumed that the
circuit layout is divided into Mg power grids.
P owerGrids = [grid1 , grid2 , ..., gridMg ]
(9)
For each grid at time step T Si the total current drawn from
the grid can be calculated by:
TS
Gk
Gk
Igridj i =
(Idyn
(T Sj ) + Ileak
)
(10)
Gk
where Gk ’s are all gates inside the power grid gridi . Ileak
is the leakage current of the gates which is obtained by cell
Gk
characterization. Idyn
(T Sj ) is the dynamic current of the gate
Gk at time step T Sj which can be obtained by the following
equation:
0
no P T T at T S
Gk
Idyn
(T Sj ) = T rants · C · f · vdd t ∈ T Sj
(11)
L
s
j
s
T rantnode
(7)
k
is a binary variable which shows node has
where T rantnode
tk
a transition (= 1) at transition time tk or not (= 0). T fnode
tk
and T rnode are the corresponding variables for rise and fall
transitions, respectively.
4) Constraints for Current: In order to obtain dynamic
PSN, the test cycle is divided into NT equal time steps.
TABLE I
Q
Equivalent circuit model of a power grid
node
t
tk
tk
k−1
T rnode
= (Snode
) ∧ (Snode
)
tk
T fnode
k
T rantnode
Q
Gk ∈gridi
Sg3.5 = (Sc0 ) (Se1.5 )
Sh4.5 = (Sf2 ) (Sg2 )
SET
CLR
is the transition variable for the output
where
node of the gate Gk if it has a possible transition time at
time step T Sj (Tj−1 ≤ ts ≤ Tj ). CL , f and vdd are the
gate load capacitance, frequency and nominal supply voltage,
respectively. CL is obtained from cell characterization and gate
level netlist.
5) Constraints for PSN: In this paper, the power grid
is modeled as an R-network distributed over the die (see
Figure 5) [20]. The supply voltage which is seen by grids
at each time step can be obtained by [21]:
V T Si = G−1 I T Si
(12)
where V T Si and I T Si are the voltage and current matrix of the
mesh network at time step T Si . G is the conductance matrix.
Since in the R-network model the capacitance of the power
network is ignored, it may lead to an inaccuracy in the dynamic
PSN estimation. In other words, in the R-network model, the
current drawn in one time step has no effect on the voltage
of next time steps which is not accurate due to the capacitive
characteristic of the power network. In order to increase the
accuracy of the PSN estimation, a history parameter (h) is
defined here which is a real number between 0 and 1. With
the help of this parameter, Equation (12) can be rewritten as
follows:
V T Si = G−1 (I T Si + h1 · I T Si−1 + ... + h(i−1) · I 1 )
(13)
!
!
This equation presents a linear solution to consider the capacitive characteristic of power network. By simulating of
the power network, a suitable value can be obtained for h
to increase the accuracy of the model.
6) Constraints for Delay: After obtaining the constraints
for the grid voltages, the following linear constraints can be
used for the delay of the gates inside the circuit.
T Sk
D(Gi ) = α · Vgrid
+ β · CL
j
(14)
where D(Gi ) is the delay of gate Gi which is on a sensitized path for a given scan test pattern. gridj is the gate’s
corresponding grid. T Sk is the time step which the output of
T Sk
the gate has a possible transition time in that step. Vgrid
is
j
the supply voltage value of its corresponding grid (gridj ) and
time step (T Sk ). The coefficient α/β are obtained from cell
characterization using a regression method. The next step is to
find the suitable constraint for all sensitized paths for special
test pattern.
D(Pi ) =
D(Gk )
(15)
Gk ∈Pi
Finally the total delay which is our objective to be minimized
can be obtained by the following equation:
D = max D(Pi )
Pi
(16)
However max operation is not a linear operation. Since we
try to minimize the delay (D), Equation (16) can be rewritten
in the following linear format:
∀Pi
D ≥ D(Pi )
(17)
Since maximum is taken over the delay of all paths sensitized
by the scan pattern (obtained from ATPG and timing analysis
tools), the dynamic sensitization criteria is already met. Therefore, there is no need to explicitly add nonlinear constraints
to obtain the sensitized paths along all critical paths.
7) Constraints to avoid test escape: Minimizing PSN during at-speed scan test is not necessarily a good objective as
it may even become less than PSN in the functional mode of
operation and may lead to test escapes. A more appropriate
objective is to minimize PSN to a level comparable to that in
functional mode. The proposed method can handle this case
by introducing an extra linear constraint as the following:
D ≥ D(f unctional)
(18)
where D(f unctional) is the delay of the circuit during its
functional mode due to the margin added for PSN.
V. E XPERIMENTAL R ESULTS
Figure 6 shows the flow of the proposed LP-based X-filling
approach to minimize the PSN during at-speed scan test. The
flow is explained for path delay test, however, the same method
can be applied for the transition delay test. The experiments
are conducted on ISCAS’89 benchmark circuits using Nangate
45 nm library [22].
As shown in Figure 6, first, all standard cells in the library
are characterized using accurate SPICE simulation to obtain
the gate delay and leakage for different supply voltages and
load capacitances. This information is stored in Look-Up
Tables (LUTs). Moreover, a regression method is applied to
these data to find the suitable coefficients (α and β) to be used
in Equation (14). Next, the circuit is synthesized and the gate
level netlist is generated using Synopsys Design Compiler.
Afterwards, the gate level netlist is placed using Cadence SOC
Encounter to obtain the layout. Besides, the critical paths are
extracted using Synopsys PrimeTime. Then, gate level netlist
and the list of critical paths are given to Synopsys Tetramax
to obtain the path delay test patterns and their corresponding
sensitized paths. In the next step, test patterns (with don’t
care bits), their corresponding sensitized paths, the layout
of the circuit and the delay/leakage LUTs are given to an
LP generator to generate an LP format netlist based on the
procedure explained in Section IV. The extracted LP netlist is
given to an LP solver (CPLEX) to solve the problem [23]. The
output of the LP solver is the X-filled test pattern resulting in
a minimum PSN-induced delay to avoid yield loss.
Table II shows the results of the proposed X-filling method
in comparison with other methods. The columns 3-6 are the
PSN-induced delay increase due to different X-filling method
compared to the nominal delay (the delay when the PSN is
totally neglected and nominal vdd is applied to obtain the
delay). The second and third columns (min_MC and max_MC)
are minimum and maximum PSN-induced delay increase
which are obtained by Monte-Carlo random X-filling. For
small circuits MC simulation is performed for 10,000 different
randomly filled patterns while, 100,000 different vectors are
simulated for larger circuits. The fifth column is the PSNinduced delay increase obtained by the Minimum Transition
Random (MTR) X-filling method [24]. This method is a well
known technique to reduce the amount of power dissipation
during scan-based testing. As shown in this table, the proposed
method can obtain the best X-filling to minimize the PSNinduced delay increase during at-speed scan path delay test
while it provides suitable runtime. Here we present the results
for only one test pattern. However, simulation results show
that, although there are some minor differences from one
to another test pattern, the overall trend of results in terms
of both improvement and runtime is almost the same for
different test patterns. According to the results, PSN-induced
delay increase ranges from 12%-30% in average during the
test cycle. Moreover, MC is less accurate compared to the
LP-based method for larger circuits. Compared to MTR, the
proposed techniques reduces PSN-induced delay increase by
42% in average.
VI. C ONCLUSION
Due to the large switching activities during at-speed scan
test, PSN is a major challenge for delay testing which may
result in yield loss. In this paper, we propose an X-filling
technique to minimize the effect of PSN during scan test
using a linear programming approach. Instead of targeting
the switching activity, for the first time, the objective is to
minimize the maximum delay of all paths which are sensitized
by the targeted test vector. Additionally, we consider spatial
!
!
Cell Characterization Circuit-level Simulation Layout Extraction
Technology
Circuit
Library
Place&Route
Description
(SOC encounter)
Cell
Synthesis Tool
Characterization
Layout (.def)
(Design Compiler)
(tcl, Hspice)
Gate Delay &
Leakage
Gate Level
Netlist
Die Partitioning
Critical Path
Test Pattern
Critical Path
extraction
(PrimeTime)
Test Pattern
Generator
(Tetramax)
List of
Critical
Paths
Delay test
Activated
Patterns
Paths
(.wgl)
LP Generator (C++)
LP Solver (CPLEX)
Optimized test vector
Fig. 6.
Benchmark
Circuit
s344
s349
s382
s386
s400
s420
s444
s510
s641
s713
s820
s838
s953
s1196
s1238
s1423
s1488
s5378
s9234
s13207
average
The detailed flow of the proposed methodology
# of
X-filling ΔDelay
Proposed
Gates min_MC max_MC MTR Proposed runtime [s]
153
6.5%
26.4% 18.2%
6.5%
0.06
124
1.8%
20.9% 20.5%
1.8%
0.06
145
13.5%
23.6% 20.6% 13.5%
0.01
116
13.3%
22.2% 13.9% 13.3%
0.02
147
22.1%
43.2% 27.1% 22.1%
0.03
186
10.4%
18.9% 18.5% 10.4%
0.00
143
20.4%
33.7% 23.9% 20.3%
0.03
237
21.0%
24.8% 21.0% 21.0%
0.02
232
14.1%
44.9% 24.6% 14.1%
0.58
220
14.7%
23.7% 14.7% 14.7%
0.03
311
8.6%
26.6% 12.3%
8.6%
0.12
366
8.9%
13.1% 10.9%
8.9%
0.00
415
11.8%
29.0% 23.5% 11.8%
0.05
456
8.2%
38.3% 14.6%
8.2%
0.87
479
10.5%
61.8% 35.5%
8.7%
11.22
759
4.3%
25.9% 12.6%
4.3%
14.76
509
7.7%
25.3% 10.8%
7.7%
0.06
1282 12.0%
27.4% 15.6%
8.5%
0.81
1245 14.2%
37.3% 22.5%
9.9%
7.60
3251 15.4%
41.3% 26.2% 10.6%
5.89
12.0%
30.4% 19.4% 11.2%
TABLE II
PSN- INDUCED DELAY INCREASE DUE TO DIFFERENT X- FILLING
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
METHODS
and temporal correlation of switchings due to layout and netlist
of the circuit to increase the accuracy of PSN estimation.
Our results show that the proposed method can efficiently
reduce dynamic PSN-induced delay during the at-speed scan
test compared to the minimum transition X-filling.
[15]
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