A low-power, high-speed, 9-channel germaniumsilicon electro-absorption modulator array
integrated with digital CMOS driver and
wavelength multiplexer
A. V. Krishnamoorthy,1* X. Zheng,1 D. Feng,3 J. Lexau,2 J. F. Buckwalter,1 H. D.
Thacker,1 F. Liu,2 Y. Luo,1 E. Chang,2 P. Amberg,1 I. Shubin,1 S. S. Djordjevic,1 J. H.
Lee,1 S. Lin,1 H. Liang,3 A. Abed,3 R. Shafiiha,3 K. Raj,1 R. Ho,2 M. Asghari,3 and J. E.
Cunningham1
1
3
Oracle Netra Systems & Networking, San Diego CA 92121, USA
2
Oracle Labs, Redwood Shores, CA 94065 USA
Mellanox Technologies, 2630 Corporate Place, Monterey Park, CA 91754 USA
*
ashok.krishnamoorthy@oracle.com
Abstract: We demonstrate the first germanium-silicon C-band electroabsorption based waveguide modulator array and echelle-grating-based
silicon wavelength multiplexer integrated with a digital CMOS driver
circuit. A 9-channel, 10Gbps SiGe electro-absorption wavelengthmultiplexed modulator array consumed a power of 5.8mW per channel
while being modulated at 10.25Gbps by 40nm CMOS drivers delivering
peak-to-peak voltage swings of 2V, achieving a modulation energyefficiency of ~570fJ/bit including drivers. Performance up to 25Gbps on a
single-channel SiGe modulator and CMOS driver is also reported.
©2014 Optical Society of America
OCIS codes: (200.4650) Optical interconnects; (250.7360) Waveguide modulators; (250.5300)
Photonic integrated circuits.
References and links
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#208635 - $15.00 USD Received 24 Mar 2014; revised 28 Apr 2014; accepted 29 Apr 2014; published 13 May 2014
(C) 2014 OSA
19 May 2014 | Vol. 22, No. 10 | DOI:10.1364/OE.22.012289 | OPTICS EXPRESS 12289
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1. Introduction
The gradual adoption of optical interconnects into computing and switching systems over the
last decade has paved the way for new photonic technologies to be incorporated into the
computing system hierarchy. We will soon witness ubiquitous incorporation of optical
interconnect technologies at the board, backplane, and rack level server systems at 25Gbps
and beyond [1]. Parallel silicon-based photonic links will naturally replace other optical
solutions for applications that require a combination of high-speed, high-density, and tight
integration to VLSI application specific integrated circuits including switches, processors,
gate arrays, and memory modules. Both WDM and multi-core fiber techniques are being
investigated for further density improvements, and it is possible that one or both of these
technologies will ultimately see wide-spread use in commercial systems.
Regardless of the multiplexing method, it is critical to achieve low-power, high-density
silicon transmitters and associated receivers to support the ever-growing bandwidth demand
to bandwidth-hungry chips including switches, processors, and field-programmable gate
arrays. A germanium-silicon (GeSi) Franz-Keldysh Effect (FKE) electro-absorption (EA)
waveguide modulator is expected to become an integral part of a high-speed energy-efficient
multi-wavelength interconnect platform [2]. In earlier work, GeSi EA modulators were
originally designed and operated with sub-micron-thick silicon-on-insulator (SOI)
waveguides [3–5], and subsequently fabricated with an optimized 3-micron-thick, large-core
SOI waveguides in the L-band [6] and C-band [7] wavelength ranges. A 4-channel modulator
array based on this platform was recently reported in [8]. In this letter, we present a compact,
broad-band 9-channel 10Gbps/channel GeSi waveguide modulator array with a
monolithically integrated echelle-based wavelength multiplexer – hybrid integrated to a lowpower CMOS driver circuit designed in a 40nm CMOS process. We also present a singlechannel GeSi FKE modulator with CMOS driver at 25Gbps.
Fig. 1. (a) Insertion loss and extinction ratio vs wavelength and reverse-bias voltages (b) total
equivalent modulator link power penalty showing that a bandwidth of 30nm obtained at
approx. 9.5dB total penalty.
#208635 - $15.00 USD Received 24 Mar 2014; revised 28 Apr 2014; accepted 29 Apr 2014; published 13 May 2014
(C) 2014 OSA
19 May 2014 | Vol. 22, No. 10 | DOI:10.1364/OE.22.012289 | OPTICS EXPRESS 12290
2. Multi-wavelength modulators and multiplexers
The GeSi EA modulator array based on the FKE is fully integrated with 3µm thick rib
waveguides on a high-resistivity SOI substrate with an operational wavelength in the C-band.
The insertion loss and extinction ratio of an FKE modulator versus reverse-bias voltage is
shown in Fig. 1(a). The equivalent modulator link power penalty [9] is plotted in Fig. 1(b).
With an applied peak-to-peak swing of 2V, each modulator in the array has an operating
wavelength range in excess of 30nm for a modulator optical power penalty of ~10dB.
Assuming the total modulator power penalty should be controlled to within a fixed range
(e.g. <10dB for 30nm), the working wavelength range can, to an extent, be traded for a
working temperature range. The rate of the band edge shift is ~0.8nm/°C [7]. Consequently,
the insertion loss and extinction ratio curves in Fig. 1(a) shift to longer wavelengths, but no
modulation performance degradation is observed. Hence, we can use this modulator at
elevated temperatures without closed-loop temperature control (see Section 3). Practical
limits to temperature excursions potentially arise due to fiber-to-chip packaging and the
WDM mux/demux - which moves only at ~0.1nm/°C. For instance, as temperature ranges
across 40°C, the band edge will shift ~32nm while the operating wavelength (to align with the
mux) will likewise shift ~4nm to keep total modulator penalty below 10dB.
Figures 2(a) and 2(b) show the device before and after integration with the VLSI circuit.
Each device has a size of approximately 20µm × 40µm, including contacts. Each modulator
is electrically isolated and has two 15µm × 15µm flip-chip pads to connect to the driver
circuit. Edge-coupled waveguides (one per modulator) provide external laser input (Fig. 2(c)).
The EA modulator array is monolithically integrated with an echelle-grating-based
multiplexer to achieve a 9-channel WDM transmitter chip with one output waveguide. The
area of the echelle grating (bounding box) is approx. 1.7mm × 2.6mm. Two additional
waveguides are used for optical alignment and one additional input port not attached to a
driver is used to test the echelle multiplexer. The WDM transmitter assembly (Figs. 2(d) and
2(e)) has a footprint of ~5mm × 14mm and an aggregate bandwidth of over 100 Gbps when
operated at its maximum speed of 12Gbps per channel. The clocked driver array circuit was
fabricated in a 40nm TSMC CMOS process and is based on a pulsed cascode-design [10]. An
external clock at half the data rate is provided to the CMOS driver chip. Each driver cell
incorporates a level-shifter to create a 1-2V swing that is complemented to a 0-1V swing to
create an effective 2V peak-to-peak modulation signal followed by the final cascaded driver.
Each modulator driver cell has a size of approximately 15µm x 15µm and additionally
incorporates two 15µm x 15µm pads with a center-to-center spacing of ~48µm to connect to
the corresponding modulator.
The combined minimum footprint of a modulator plus associated driver circuit was
approximately 30µm × 100µm. Although not done in this case, the circuits can be placed
underneath the flip-chip pads for 3-D photonics-on-CMOS integration [11] to achieve even
higher density. Small-signal measurements were performed on a representative device on an
unpackaged chip to measure the electro-optic response of the FKE modulators (Fig. 3(a)) at
bias voltages of 0V, 1V, and 2V. At zero bias, the modulator bandwidth was 20GHz. At a
reverse-bias voltage between 1V and 2V, a 3dB bandwidth in excess of 40GHz was
measured. To model the device, s11 parameter measurements were taken, and a circuit model
made (Fig. 3(b)). With the circuit diagram and extracted parasitics, excellent fitting was
obtained at all voltages. The extracted values (Table in Fig. 3(c)) indicate a modulator device
capacitance (junction plus parasitic) of ~50fF at 1V. The substrate capacitance does not
significantly affect device performance because of the high-resistivity SOI substrate.
#208635 - $15.00 USD Received 24 Mar 2014; revised 28 Apr 2014; accepted 29 Apr 2014; published 13 May 2014
(C) 2014 OSA
19 May 2014 | Vol. 22, No. 10 | DOI:10.1364/OE.22.012289 | OPTICS EXPRESS 12291
Fig. 2. (a) GeSi modulator micrograph; (b) infrared micrograph of the modulator array after
bonding to CMOS chip showing flip-chip pads and I/O waveguides; (c) Micrograph of the
3µm GeSi EA WDM modulator array (face-up) integrated with the 40nm TSMC driver chip
(face-down); (d) Schematic of the driver chip integrated to the 3-micron silicon-on-insulator
chip containing the Si/Ge FKE electro-absorption modulators array and the echelle
multiplexer; (e) After fiber attach on packaged system test board.
Fig. 3. (a) Small-signal bandwidth of the GeSi FKE modulator (b) equivalent circuit based on
S11 measurements and parameter fitting (c) Table of extracted values of junction, parasitic,
and substrate capacitance and series resistance.
3. WDM transmitter array testing
The CMOS-FKE EA WDM transmitter assembly is packaged into a fixture that provides heat
spreading, mechanical stability, and support for edge-coupled fiber attach (Fig. 2(e)). Figure 4
shows the transmission of the unpackaged 10-channel modulator with echelle mux
normalized to the fiber-coupling loss. This is a representation of the loss and non-uniformity
#208635 - $15.00 USD Received 24 Mar 2014; revised 28 Apr 2014; accepted 29 Apr 2014; published 13 May 2014
(C) 2014 OSA
19 May 2014 | Vol. 22, No. 10 | DOI:10.1364/OE.22.012289 | OPTICS EXPRESS 12292
of the array before fiber-coupling and packaging. The non-uniformity is primarily due to the
modulator array insertion loss variation across the wavelength range (~1.8dB) and variation
due to echelle mux and wafer non-uniformity (≤1dB). Ten channels separated by ~200GHz
spacing (~1.6nm) were provisioned, of which nine channels around 1535nm were connected
to modulator devices. The fiber-attached array is mounted on a custom printed circuit board
and wire-bonded for power and control.
The chip-assembly was thermally-imaged (Fig. 5(a)) and a temperature scan (Fig. 5(b))
shows that the temperature of the VLSI chip and attached photonic chip rises 7-8°C,
relatively uniformly across the entire photonic array. Further, the actual modulator
temperature rises about 2°C above the VLSI chip temperature. Given that this effect is
predictable, the Si-Ge FK band edge and mux can be engineered and optimized for operation
at this elevated temperature.
Fig. 4. Transmission of an unpackaged 10-channel modulator + multiplexer array chip
normalized to fiber coupling loss; Worst-case isolation is >20dB on adjacent channels spaced
at 100GHz.
The transmitter assembly was tested at speed. On-chip PRBS generators created digital
electrical signals which were applied to each modulator by its respective driver circuit. Figure
5(c) shows the optical eye when one channel is driven at the maximum data-rate of 12Gbps
supported by the VLSI chip with 4dBm of input optical power. The measured output
extinction ratio is ~4.3dB. Optical and electrical crosstalk between channels is negligible. As
shown in Fig. 6, nine channels of the parallel WDM transmitter were simultaneously
modulated at 10.25Gbps with open eyes with extinction ratios ranging from 4dB to 5.5dB.
The power dissipation per channel is measured by enabling a modulator channel and
measuring the on-chip power. A power dissipation of 5.82mW per channel is measured at the
bit-rate of 10.25Gbps which takes into account the dynamic power consumed by the driver +
modulator (~1.5mW) the absorbed photo-current power of the EA device (~1.5mW) as well
as leakage current power, which was significant in this case (~2.5mW). The corresponding
modulator energy per bit is ~570fJ/bit including driver circuit at an average photo-current of
0.7mA. We expect this can be reduced to ~300fJ/bit or below with device improvements.
The small channel footprint, wide bandwidth, and low capacitance of the GeSi EA
modulator and driver array enable a compelling, low-power, high-density silicon-photonic
WDM transmitter solution. By scaling the modulator transmitter chip with more channels and
operating the silicon driver chip at higher bitrates with 25Gbps and faster driver circuits, we
anticipate a potential transceiver array with a total bandwidth on the order of up to 10Tbps
#208635 - $15.00 USD Received 24 Mar 2014; revised 28 Apr 2014; accepted 29 Apr 2014; published 13 May 2014
(C) 2014 OSA
19 May 2014 | Vol. 22, No. 10 | DOI:10.1364/OE.22.012289 | OPTICS EXPRESS 12293
and a power dissipation in the range of 10-20W for ubiquitous photonic communication
applications.
Fig. 5. (a) Thermal profile of flip-chip assembly when powered ON. Powered modulator array
can be seen as a vertical column on the left. (b) Scan of temperature across the assembly
showing a temperature difference of ~10°C with peak temperature at EA modulator. (b) Eye
diagram of a channel running at 12Gbps with on-chip PRBS data generator.
Fig. 6. Test of the integrated multi-wavelength transmitter showing simultaneous modulation
on all nine channels at 10.25Gbps. Center wavelength was 1532nm and separation between
channels was 1.6nm
We also tested a single-channel CMOS-FKE EA modulator with driver circuits at 25Gbps
to evaluate transmitter performance with higher-speed drivers for packaging into a 100Gbps
transceiver. The high-speed drivers were based on push-pull (inverter) amplifiers integrated in
130nm CMOS SOI and are similar to the circuits reported previously [12]. The output driver
stage is illustrated in Fig. 7 and consists of a pair of push-pull drivers that are driven with
complementary data signals. Additionally, the two data signals are level-shifted with respect
to ground to allow complementary voltage swing across the p-n junction which does not
forward bias the junction but also avoids exceeding the voltage swing limitations of the
CMOS devices. The size of the push-pull driver transistors is related to the capacitance of the
FK modulator and, therefore, can be directly related to the power consumption of the driver
circuits. Figure 8 shows the transmitter eye at 25Gbps when integrated with the 130nm
CMOS high-speed driver. In this experiment, the driver die was located adjacent the FKE EA
modulator and wire-bonded with low-inductance ribbon bonds. The capacitance of the
#208635 - $15.00 USD Received 24 Mar 2014; revised 28 Apr 2014; accepted 29 Apr 2014; published 13 May 2014
(C) 2014 OSA
19 May 2014 | Vol. 22, No. 10 | DOI:10.1364/OE.22.012289 | OPTICS EXPRESS 12294
bondpads on the driver and the modulator can be incorporated into a broadband pi-network
with a bandwidth of more than 20GHz. Excluding the off-chip laser power, the transmitter
consumed below 70mW per channel (2.8pJ/bit) at 25Gbps including the 25Gbps electrical I/O
circuit. This power can be reduced with flip-chip integration of the modulator chip onto the
driver die.
Fig. 7. Schematic of the 130nm CMOS SOI driver stage. Two push-pull driver stages control
the swing across the p-n junction.
Fig. 8. Test of a single-channel version of the FK transmitter driven by a 130nm CMOS driver
at 25Gbps/lane package: optical output eye at 25Gbps.
Acknowledgments
The authors gratefully acknowledge Dr. Guoliang Li for RF measurements, Chaoqi Zhang for
thermal simulation, Dr. J. Mitchell and C. Stephen of Oracle Labs and J. Malinge formerly of
Kotura Inc. for their support of this project. This work was supported in part by DARPA
under Agreement HR0011-08-09-0001 under the supervision of Dr. J. Shah. The view
expressed are those of the authors and do not reflect the official policy of the Dept. of
Defense or the U. S. government. Approved for public release; distribution unlimited.
#208635 - $15.00 USD Received 24 Mar 2014; revised 28 Apr 2014; accepted 29 Apr 2014; published 13 May 2014
(C) 2014 OSA
19 May 2014 | Vol. 22, No. 10 | DOI:10.1364/OE.22.012289 | OPTICS EXPRESS 12295