a
Evaluation Board
AD976/AD976A 16-Bit,100/200 kSPS ADC
EVAL-AD976/AD976ACB
Preliminary Technical Data
FEATURES
Versatile Analog Signal Conditioning Circuitry
Jumper Selectable Analog Input Ranges
Analog and Digital Prototyping Area
Flexible Power and Grounding Schemes
On-Board Reference and Buffers
16-Bit Parallel Buffered Outputs
Ideal For DSP and Data Acquisition Card Interfaces
EVAL-CONTROL BOARD Compatibility
PC Software for Control and Data Analysis
The EVAL-AD976/AD976ACB is ideal for use as either a
stand-alone evaluation board to interface with customer
application, or with the EVAL-CONTROL BOARD, also
available from Analog Devices. The design offers the
flexibility of applying external control signals and is
capable of generating 16-bit conversion results as parallel
buffered outputs.
On-board components include an AD780, a +2.5V ultra
high precision bandgap reference, an AD845 signal
conditioning op-amp, and digital buffers. The board
interfaces with a 96-way connector for the EVAL-CONGENERAL DESCRIPTION
The EVAL-AD976/AD976ACB is an evaluation board for TROL BOARD, and a 40-pin IDC connector for parallel
the AD976/AD976A 16-bit ADC. The AD976/AD976A is output data. BNC connector is provided for the low noise
capable of a 100/200 ksps throughput rate, operates from a analog signal source and BNC connector is provided for
an external read/convert input.
single +5V supply and uses a parallel interface.
The AD976/AD976A evaluation board is designed to
demonstrate the ADC's performances and to provide an
easy to understand interface for a variety of system applications. A full description of the AD976/AD976A is available in the AD976/AD976A data sheet and should be
consulted when utilizing this evaluation board.
FUNCTIONAL BLOCK DIAGRAM
+ /-5 V
A IN
S IG N A L
C O N D IT IO N IN G
AD 8 4 5
V IN
S E L E C T A BL E
S U P PL Y
D0
.
.
D15
AD976/
AD976A
+ /-1 2 V
VCC
DA T A
BU F F E R
40
P IN
CONN
96
P IN
C ONN
BUSY
RE F 2 . 5 V
A D 78 0
RE F
R/ C
B
U
F
F
E
R
S
BY T E
CS
PRELIM. F
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
EVAL - AD976/AD976ACB
OPERATING THE EVAL-AD976/AD976ACB
The EVAL-AD976/AD976ACB is a four-layer board
carefully laid out and tested to demonstrate the specific
high accuracy performance of the device. Figure 2 shows
the schematics of the evaluation board. Figure 3 shows the
component side silk-screen. The layouts of the board are
given in :
Component layer - Figure 4
Power layer - Figure 5
Ground layer - Figure 6
Circuit side layer - Figure 7.
The EVAL-AD976/AD976ACB is a flexible design that
enables the user to choose among many different board
configurations. The available test points are listed in
Table I and a description of each selectable jumper is
listed in Table II.
The evaluation board schematic shows the factory installed jumper selections. The EVAL-AD976/AD976ACB
is configured to be powered through the EVAL-CONTROL BOARD, the AD780 external reference applied to
the REF pin, the signal conditioning op-amp set with a
gain of -2 and on-board R/C generation used. Conversion
data is available at the outputs of two 8-bit registers, U4
and U5 for parallel transfer via the 40-pin IDC connector,
P5 or the 96-pin DIN connector, P4. The AD976/
AD976A conversion control inputs, R/C and CS, are
configured to provide continuous conversions with the CS
input is set low and the R/C input connected to the output
of the counter, U7.
AN ALO G
PO W E R SU P P LIE S
+ 1 5 V G N D -1 5 V
+ V C C A G N D -V E E
P3
P4
D IG IT A L
S Y S T E M P O W ER
+5V GN D
+5V GN D
VA NA A G N D
P1
P2
V D IG D G N D
Figure 1. Power Connection Diagram
Assembly Options
The AD976 and AD976A on the evaluation board is
configured for offset adjust and operation with the AD780
external reference. Remove the header shunt from JP4 to
operate the AD976/AD976A with its internal reference.
Connecting the header shunt to position A of JP4 allows
trim adjusment of the AD976/AD976A gain error.
Offset adjustment is provided with the resistor, R6,
connected as shown in the evaluation board schematic, and
in Figure 7 of the datasheet.
To operate the AD976 without offset adjustment remove
the 33.2 kΩ resistor, R6, and install it into the open
location for resistor, R5.
To operate the AD976A without offset adjustment remove
the 33.2 kΩ resistor, R6, and connect 66.4 kΩ resistor
between VIN, pin 1, and VANA, pin 27 of the AD976A.
The EVAL-AD976CB and EVAL-AD976ACB differ only
by the frequency of the oscillator U8 which is respectively
1MHz and 2MHz for the AD976 and the AD976A.
TABLE I. EVAL-AD976CB/AD976ACB Test Points
Test Point
TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
Power Supplies and Grounding
The EVAL-AD976/AD976ACB power supply connectors
and ground planes are configured to provide the multiple
power and grounding configurations used in most system
applications.
The evaluation board ground plane is separated into two
sections: a plane for the digital interface circuitry and an
analog plane for the AD976/AD976A and its analog input
and external reference circuitry. To attain high resolution
performance the board was designed to ensure that all
digital ground return paths do not cross the analog ground
return paths.
Available Signal
VANA
AGND
+VS
-VS
VDIG
SYSTEM DGND
AIN GND
VIN
CAP
AGND2
DGND
BUSY
R/C GND
The EVAL-AD976/AD976ACB has three power supply
blocks: a single 5V supply for the AD976/AD976A V ANA
and VDIG power pins (P1), a 5V supply for the digital
interface circuitry (P2), and a +/-12V supply for the
analog signal conditioning circuitry (P3). All supplies are
decoupled to ground with 10 µF tantalum and 0.1 µF
ceramic capacitors. Figure 1 shows the recommended
power connection diagram.
–2–
PRELIM. F
PRELIMINARY TECHNICAL DATA
EVAL - AD976/AD976ACB
EVAL-CONTROL BOARD Interface
The EVAL-AD976/AD976ACB interfaces to the EVALCONTROL BOARD through the 96-way connector.
RUNNING THE EVAL-AD974CB SOFTWARE
Software Description
The EVAL-AD976/AD976ACB comes with software for
analyzing the AD976/AD976A. Through the EVALCONTROL BOARD one can perform a histogram to
determine code transition noise, and Fast Fourier Transforms (FFT's) to determine the Signal-to-Noise Ratio
(SNR), Signal-to-Noise-plus-Distortion (SNRD) and
Total-Harmonic-Distortion (THD). The front-end PC
software has three screens as shown in Figure 8, 9 and 10.
Figure 8 is the Setup Screen where sample rate, number
of samples are selected. Figure 9 is the Histogram Screen,
which allows to display the code distribution for DC input
and computes the mean and standard deviation. Figure 10
is the FFT Screen, which performs an FFT on the
captured data, computes the Signal-to-Noise Ratio
(SNR), Signal-to-Noise-plus-Distortion (SNRD) and
Total-Harmonic-Distortion (THD).
Software Installation
The EVAL-AD976/AD976ACB software runs under DOS
4.0 or higher. It requires a minimum of 386-based
machine, with 500kB of base RAM and 500kB of free
hard disk space and uses the COM1 serial port. It may be
necessary to disable some TSR's ( network TSR's for
example) or load them into high memory, to ensure that
adequate base memory is available. Operation under
Windows 3.x is not recommended since the Windows
COM interrupt can interfere with communication between
the PC and the EVAL-CONTROL BOARD. For PC
running under Windows 95, it is recommended to shutdown it using the option restart the computer in MS-DOS
mode.
The EVAL-AD976/AD976ACB software installation
process is:
- Create a new directory on the main PC drive and label
this "AD976".
- Copy into this directory all files contained in the disk
which accompanies the EVAL-AD976/AD976ACB.
- The software can be started typing "AD976".
Note that the Mouse Driver on the PC should be
enabled before running the software. If this has
not been loaded then the program will not run.
PRELIM. F
–3–
EVAL - AD976/AD976ACB
TABLE II. JUMPER DESCRIPTION
Jumper
Designation
Function
JP1,2
These two jumpers are used to select the configuration of the op amp, U2. To configure the op-amp as
an inverter install the header shunt of JP1 to position A and JP2 to position B. To configure the op-amp
as a follower install the header shunt of JP2 to position A, and JP1 to position B.
JP3
The position of JP3 determines the source of the analog signal for the AD976/AD976A. To apply the
AD976/AD976A analog input signal directly from the BNC connector, J1; set JP3 to position A. To
select the output of the op-amp set JP3 to position B.
JP4
With JP4 set to position A, the AD976/AD976A uses its own internal reference but allows for an
external gain adjustment through R8. Placing JP4 in position B selects the AD780 for use as an external
reference. To use the AD976/AD976A internal reference without gain adjustment remove the shunt
header of JP4.
JP5
The R/C control input to the AD976/AD976A can be driven from either an external source or an
onboard clock source. With JP7 set to position A; JP5 selects the control input for the R/C pin of the
AD976/AD976A. Set JP5 to position A to use the on-board square wave from the 74HC190 or set JP5
to position B to select an external R/C waveform from the BNC connector, J2.
JP6
Install JP6 to set the AD976/AD976A CS input to a logic low. Remove this jumper to allow an external
CS input to be applied.
JP7
JP7 selects either one of the two external R/C control inputs from JP5 or the R/C output from the
EVAL-CONTROL BOARD.
JP8
Install the header shunt of JP8 to position A to set the AD976/AD976A BYTE input to a logic low.
Select position B to control the BYTE input to the AD976/AD976A by the EVAL-CONTROL
BOARD.
JP9
The header shunt for JP9 should be installed when the power to the EVAL-AD976CB/AD976ACB is
supplied from the EVAL-CONTROL BOARD or when a single power supply is applied to the EVALAD976/976ACB. Otherwise the shunt header should be left unconnected.
JP11
JP11 selects the digital power source for the AD976/AD976A. Install the shunt header to provide power
from a +5 V supply (VANA) from the power block, P1. Remove the shunt header to apply a separate
external +5 V supply for the VDIG pin of the AD976/AD976A or to monitor the current to the ADC.
JP12
JP12 is used to connect the +5V analog power plane, VANA, to the power plane for the digital interface
circuitry, VDIG. Install the jumper to provide a single+5V external supply to all of the on-board
components. Removal of this header shunt seperates the power supply for the AD976/AD976A from the
supply of the digital interface circuitry. When used in conjunction with the EVAL-CONTROL
BOARD, JP12 must be unconnected; VANA is the analog power, +5V, and VDIG is digital interface
circuitry power, VCC, provided seperately from the EVAL-CONTROL BOARD.
JP14
The header shunt for JP14 connects the ground plane of the AD976/AD976A to the digital interface
circuitry ground plane. Connect the header shunt on JP14 only when JP12 is installed.
JP15
JP15 selects the analog power source for the AD976/AD976A. Install the shunt header to provide power
from a +5V supply (VANA) from the power block, P1. Remove the shunt header to apply a seperate
external +5V supply for the VANA pin of the AD976/AD976A or to monitor the current to the ADC.
JP16,17
JP16 and JP17 select the power source for the analog amplifier. Position B allows an external bipolar
power supply to be connected to the 3-pin power block P3. Position A selects the +/-12 V supply
provided at the 96-pin connector, P4.
–4–
PRELIM. F
PRELIM. F
TP7
J1
Figure 2. Schematic
–5–
VANA
50k Ω
C5
0.1 µ F
B
B
4
3
2
1
NC
500Ω
R3
1k Ω
R2
TP1
U3
6
5
TR IM
7
VOUT
NC
8
3
2
VCC
U6
TP9
74 HC 24 0
C22
0.1µ F
-V S
+ VS
R5
2.2 µ F
C2
R6
B
A
+ VS
10µ F
C9
D5 17
12 D9
14 DGND
U1
D4 18
1 1 D 10
D7 15
D6 16
D3 19
1 0 D 11
13 D8
D2 20
D1 21
D0 22
23
R/C 24
BYT E
AD976
26
CS 25
BUS Y
V AN A 2 7
V DIG 2 8
0.1µ F
C17
B
9 D 12
8 D 13
7 D 14
6 D15(M S B)
5 AG N D 2
4 C AP
3 RE F
10µ F
C8
TP4
0.1µ F
C16
VANA
JP11
TP3
B
CS
JP6
TP12
-V S
A
JP15
JP17
P3
+ VC C A G N D -V E E
JP16
2 AG N D 1
1 V IN
TP8
R4
+ 1 2V
TP11
20 0 Ω
TP10
JP3
A
TP6
P2
V D IG D G N D
33.2k Ω
10µ F
C11
10µ F
C10
0.1µ F
C15
2.2 µ F
C1
(10,1,19)
14
V D IG
C3
100 µ F
B
A
0.1µ F
C12
6
0.1µ F
C13
VANA
50k Ω
R7
4
7
R1
C6
2kΩ
2n F
10µ F
C18
V D IG
U2
A D 8 45
TP5
JP4
JP14
JP12
O /P
S E LE C T
R9
576 k Ω
AD780
GND
TE M P
+ V IN
VANA
JP2
JP1
C7
C14
R8
A
A
1 0 µF
VANA
+5V
0.1µ F
P1
A D9 76/A D 97 6A
R ev. B E valuation B oard
S chem atic D iag ram
1µ F
C4
A IN
TP2
A G N D VAN A
R 13
10 k Ω
-1 2 V
2
QD
GND
7
8
CLK
R /C
D
C
LO AD
M X /M N
RCO
CLK
A
9
10
11
12
13
14
15
16
B Y TE
16
6
14
U6
VANA
12
11
U6
9
13
JP8
JP7
GND
B
B
U8
X TA L *
OUT
+V
VANA
A
A
*1 M Hz for A D 9 76
*2 M H z for A D 9 76A
JP5
B
C23
C21
A
0.1µ F
0.1µ F
VANA
U6
U6
7
R 10
39
40
2
49.9Ω
R 11
50kΩ
J2
R 12
50kΩ
P4
R /C
V D IG
AG ND
JP9
TP13
(C -19 )
(C -18 )
(B -18)
(A -18)
(B -17)
(B -15)
(B -14)
(B -13)
(B -11)
(B -10)
(B -9)
(B -7)
(B -6)
(B -5)
(B -3)
(B -2)
VCC
-1 2 V
(A ,B ,C -8 )
(A -30)
+ 1 2V (C -30 )
A V D D (A ,B ,C -3 2 )
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
(C -10 )
(B -1)
(A -17)
9 6-P IN D IN C O N N .
F L1
F L0
IR Q 2 (C -17 )
CS
AG ND
(A,B ,C-2 1 ,2 2,2 3,24 ,
2 5,2 6 ,2 9 B -27 ,28 ,3 0
DGND DGND
(A ,B ,C-4 ,1 2 ,16 ,20 )
VCC
-1 2 V
+ 1 2V
+5V
4 0-P IN ID C C O N N .
P5
BUSY
D0
D2
D3
D4
D14
D15
D5
D6
D12
D13
D7
D8
D9
D10
D11
D10
D9
D11
D12
D13
D1
8
11
12
13
14
15
16
17
18
19
0.1µ F
D15 1
D14
7 4H C 5 7 4
CLK
Y8
Y7
Y6
Y5
Y4
Y3
Y2
Y1
D8
C20
V D IG
D7
D6
D5
D4
D3
D2
D1
D0
C19
0.1µ F
U4
GND
A8
A7
A6
A5
A4
A3
A2
A1
20
11
O U T_ EN V C C
VCC
U6
U7
4
10
9
8
7
6
5
4
3
2
1
74 HC 19 0
QC
D /U
C TE N
QA
QB
B
18
6
5
4
3
2
1
U6
D15
D14
D13
D12
D11
D10
D9
D8
U5
12
13
14
15
16
17
18
19
20
Y8
Y7
Y6
Y5
Y4
Y3
Y2
Y1
7 4H C 5 7 4
GND
10
A7
A6
A8
8
D6
A5
A4
A3
A2
A1
O U T_ EN V C C
9
7
D5
D7
6
5
4
3
2
1
D4
D3
D2
D1
D0
V D IG
PRELIMINARY TECHNICAL DATA
EVAL - AD976/AD976ACB
EVAL - AD976/AD976ACB
Figure 3. Component side silkscreen ( Not to Scale).
Figure 5. Power Layer ( Not to Scale).
Figure 4. Component side ( Not to Scale).
Figure 7. Circuit Side ( Not to Scale).
Figure 6. Ground layer ( Not to Scale).
–6–
PRELIM. F
PRELIMINARY TECHNICAL DATA
EVAL - AD976/AD976ACB
Figure 8. Setup screen.
Figure 9. Histogram screen.
PRELIM. F
–7–
EVAL - AD976/AD976ACB
Figure 10. FFT screen.
–8–
PRELIM. F