NP-ATL-ROD-ABCDEC1-001-RPT
University of Oxford
Department of Physics
Interim Report
Project Name:
Atlas Binary Chip Decoder (ABC Decoder)
Project Code:
NP-ATL-ROD-ABCDEC1
Group:
ATLAS
Version:
DRAFT
Date:
04 February 1998
Distribution List:
A. Grillo
D. Cambell
S. Cooper
M. Goodrich
N. Kundu
A. J. Lankford
G. Myatt
G. Noyes
R. Nickerson
A. Parker
A. Segar
P. Shield
R. L. Wastie
A. R. Weidberg
UCSC
RAL
Cambridge
UCI
RAL
Cambridge
Additional copies may be obtained from S. Geddes (s.geddes1@physics.ox.ac.uk)
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1.0 Related projects and documents
1.1 Projects
NP-ATL-FEE-ABCRDOT
NP-ATL-ROD-BIPHALD
NP-ATL-ROD-ABCDEC1
ABC readout
BiLED
ABC decoder
Oxford University
Oxford University
Oxford University
1.2 Documents
[1] ABC (Atlas Binary Chip) Project Specification, D. Campbell, RAL,
web page:- http://scipp.ucsc.edu/groups/atlas/sct-docs.html
[2] SCT Off-Detector Electronics Requirements Document, A. J. Lankford, UCI,
web page:- http://scipp.ucsc.edu/groups/atlas/sct-docs.html
[3] NP-ATL-FEE-ABCRDOT-001-RPD, ABC Readout Report, N. Kundu, Oxford.
[4] DORIC, A Front End Clock and L1 Distribution Chip, J. R. Gorbold and P. Seller.
[5] DORIC (Digital Opto-Receiver Integrated Circuit) Project Specification, D. J.
White, RAL.
[6] LDC (LED Driver Circuit) Project Specification, D. J. White, RAL.
[7] Trigger-DAQ Steering Group Requirement Document, web page: http://scipp.ucsc.edu/groups/atlas/sct-docs.html
[8] N-ATL-ROD-BLD-001-PRS, Biphase Mark Encoder and LED Drive Control
Chip, R.L.Wastie, Oxford University.
[9] Digital Readout Chip for Silicon Strip Detectors at SDC, K. Shankar, RAL, N.
Kundu, Oxford.
[10] NP-ATL-ROD-ABCDEC1-001-PRS, Atlas Binary Chip Decoder (ABC
Decoder) Project Specification, R.L.Wastie, Oxford University.
2.0 Introduction
This document describes a ROD ABC Decoder based on one chip. This chip would be
implemented with an FPGA or a cell based ASIC design.
As shown in the “ROD Data Paths”( page 7 ), a ROD would consist of four ABC
Decoder ASICs each with it own external buffer (Buffer 1). These four buffers are
read by one Event Builder which assembles whole events into an external buffer
(Buffer2) supplying a 1Gbit/s ROD-ROB link (delivering event data to a ROB). There
is a Host CPU for control, monitoring and various other housekeeping tasks.
The ABC Decoder receives eight serial links form the front-end modules, decodes the
data, check and handling various data errors and building the event fragments for each
channel. These fragments are stored in chip/strip order in the external buffer (Buffer
1).
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3.0 ROD Model
3.1 Physics Model
The physics data was take from the TDR. Several assumptions have been made about
the data, which are listed as follows: The occupancy in the silicon detector is 2% (1% TDR) with a Poisson distribution to
allow for fluctuations and to allow for any error in the Monte Carlo simulations.
The distribution of strips hit in the module is assumed to be uniform with 50% of the
hits having neighbours. The strip hit distribution don’t affect the data rate. The L1
trigger rate is 100 kHz with a exponential distribution of interval time.
The decoder must not be the limiting factor in the data flow. That is it must take data
at 40 Mbits/s or approx. 19 hits with 50% neighbours per L1 accept continues at 100
kHz average trigger rate. Figure 1 shows the L1 trigger interval distribution with 106
L1 triggers 10s of LHC real-time. Figure 2 shows the distribution of the number of
hits per trigger for the same simulation.
The model generates data for one ABC module which is fed into all eight decoder
channels.
Figure 1
Distribution of L1 triggers
12000
10000
Number of trigger
8000
6000
Series1
4000
2000
0
0
20
40
60
Interval time uS
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100
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NP-ATL-ROD-ABCDEC1-001-RPT
Figure 2
Hit Distribution
70000
60000
The mean is 23 hits per
trigger
50000
40000
Series1
30000
20000
10000
0
0
10
20
30
40
50
60
70
Number of Hits per trigger
3.2 Decoder Model
Data
The ADC Decoder model can handle all the physics data types and all the ABC error
codes. The configuration data is not included yet.
The data is written into the output buffer (buffer 0) as 32-bit words. The data format is
as Table 1. If there is an odd number of hits the 2nd hit will be padded by zeros.
Each block of data for an event (L1 accept) is written in the buffer with a header word
at the beginning which contains the trigger information. At the end of the event a
trailer word is written into the buffer as shown in Table 2. This format allows for a
variable number of hits to be identified in the buffer. There can be several events in
the buffer. This is an intermediate data format used by the event builder.
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Table 1
Packet
type
[31:28]
Hit data
tttt
0000
Strip
address
[20:14]
Hit data
[27:25]
Chip
addesss
[24:21]
[13:11]
Chip
addesss
[10:7]
Strip
address
[6:0]
ddd
cccc
sssssss
ddd
cccc
sssssss
2nd hit data
1st hit data
Table 2
Packet
type
1111
1110
L1ID
BCID
0000 0000 0000 0000 LLLL
bbbbbbbbbbbb
0000 0000 0000 0000 0000 0000 0000
Header Word
Trailer Word
Errors
Error handling is implemented in the model in a limited fashion. One or many errors
can be selected to be counted in one error counter. The counter can be masked to
count only selected errors if required. Errors are also written into a buffer, but that is
as far as this implementation is modeled. I need to know from the wider ATLAS
community what error information is need at the ROB/DAQ level.
Buffers
The results of the simulation show that the buffers sizes are relatively small.
Buffer Zero the internal buffer in the decoder would have a depth of 2 by 32 bits for
each channel. Buffer One the buffer between the decoder and the event builder would
have a depth of 416 by 32 bits for each channel. Buffer One would have to be
implemented as 512 x 32bits.
Data is read from buffer zero for each decoder channel in turn starting with channel
one. When channel eight has been read out there is a delay equivalent to the readout
time of 24 decoder channels. This was done to simulate the event builder handling 32
decoder channels.
L1 & BC
The checking of the L1ID and BCID would best be implemented in the event builder.
I came to this conclusion from evaluating the first decoder architecture. In that
architecture the check was implemented for each receiver channel (module). This
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required that each channel needed a LIID/BCID buffer, consequently this made the
design much larger that the second approach.
4.0 Model simulation results
Total number of L1 Accepts
Total number of Hits
Average hits
Maximum hits per trigger
Number of errors
Maximun nuber of L1’s waiting
Maximum words in Buffer Zero
Channel
Max Words
1
409
1000000
23754903
23b
66
30616a
16
2
Maximum words in Buffer One
2
3
4
5
410
411
413
413
6
414
7
415
8
416
Note a
These errors are ABC buffer overflow errors. This happens when the number of
triggers in the ABC event FIFO exceeds eight. This number of errors is a 0.51% data
loss.
Note b
This is an occupancy of 3%.
5.0 Further work
Module
To improve the model the module data would have to be generated for each decoder
channel separately and with different data.
Decoder
The issue of the error data needs to be addressed, where and what to do with the error
data. There needs to be a global look at errors, and where they are processed. Some
errors could be better handled in the event builder or somewhere else. Then the error
handling can have a more complete implementation.
Event Builder
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The formatting of the event packets to the slink is still to be implemented. The amount
of data to the slink is far to high, data compression encoding schemes to reduce the
data to an acceptable level will need to be investigated.
5.0 Document Control
All documentation will be archived according to the ATLAS Document Management
Protocol. All documents will be kept for the lifetime of the ATLAS experiment.
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1Gb/s
ROD Data Paths
Fibre to ROB
Slink Fibre Tx
32
For Local Data readout during
Barrel testing.
Derandomizing
FIFO
32Kx32
Host Bus: Event Builder
Setup
Trigger Type
Module ID
Control
Status
Error Statistics
Errors
Buffer 2
32
L1A
L1ID
EVENT BUILDER
BCID
Data
WR1 RD0 RD1
BCR
32
Buffer 1
VME
WR1
0
DUAL PORT
RAM
RD1
4Kx32
WR1
1
DUAL PORT
RAM
RD1
4Kx32
WR1
2
DUAL PORT
RAM
RD1
4Kx32
WR1
3
DUAL PORT
RAM
RD1
4Kx32
Host
CPU
4
32
32
32
32
16
Host Bus: Decoders
Setup
Channel Masking
Control
Status
Error Statistics
Errors
0
ABC
Decoder
RD0
L1A
A
1
ABC
Decoder
RD0
8 Links
8 Links
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L1A
2
ABC
Decoder
RD0
L1A
8 Links
3
ABC
Decoder
RD0
8 Links
Buffer 0
L1A