PAC-POWR1220AT8-EV
Evaluation Board
March 2006 Application Note AN6065
Lattice Semiconductor’s Power Manager II ispPAC ® -POWR1220AT8 device simplifies power supply design by integrating the analog and digital functions of power supply management (sequencing, monitoring, trimming/margining, measurement) into a single device. This device provides designers with a rich set of features: A/D and D/A conversion, precision comparators with a built-in voltage reference, MOSFET drivers with programmable slew rates, an easy-to-use closed-loop power supply voltage trim system, and a programmable logic device (PLD) for sequencing and supervisory logic functions. All of these blocks can be accessed via I 2 C for enhanced flexibility in systems employing an on-board microcontroller. Configuration for all subsystems in the ispPAC-POWR1220AT8 device is stored in non-volatile E 2 CMOS ® memory. Programming is performed via the industry-standard JTAG
IEEE 1149.1 interface.
The PAC-POWR1220AT8-EV evaluation board (Figure 1) allows the designer to quickly configure and evaluate the
ispPAC-POWR1220AT8 device on a fully assembled printed-circuit board. The four-layer board supports a 100-pin
TQFP package, pads for user I/O, a JTAG programming cable connector, and a connector for the device's I
2
C interface. JTAG programming signals can be generated by using an ispDOWNLOAD
®
programming cable connected between the evaluation board and a PC’s parallel (printer) port. Both analog and digital features of the ispPAC-
POWR1220AT8 device can be easily configured using PAC-Designer
®
software. The actual size of the board is 5” x
4” (12.5 x 10 cm).
The I 2 C interface includes circuitry to allow the use of either an ispDOWNLOAD cable or standard open collector
I 2 C bus. The I 2 C software utility that is included in PAC-Designer makes use of the ispDOWNLOAD cable interface to allow designers to evaluate the device’s I 2 C capabilities without having to buy additional cables or adapters.
More information about this software tool can be found in application note AN6067, ispPAC-POWR1220AT8 I 2 C
Hardware Verification Utility Users Guide.
Extra pads are provided adjacent to the I 2 C connector to allow the user to easily access the SDA and SCL signals as well as the regulated 3.3 volt VCC supply. Connection to a standard I 2 C bus or cable is done simply by connecting to the SDA, SCL, and GND pins of J5; pin #3 is left floating. Connection to an ispDOWNLOAD cable is done simply by mating the ispDOWNLOAD cable’s connector to the I 2 C header (J5).
Figure 1. PAC-POWR1220AT8-EV Evaluation Board www.latticesemi.com
1 an6065_01.1

Lattice Semiconductor PAC-POWR1220AT8-EV Evaluation Board
Lattice Semiconductor’s ispDOWNLOAD cable can be used to program the ispPAC-POWR1220AT8 device on the evaluation board. This cable plugs into a PC-compatible's parallel port connector, and includes active buffer circuitry inside its DB-25 connector housing. The other end of the ispDOWNLOAD cable terminates in an 8-pin 0.100” pitch header connector which plugs directly into a mating connector provided on the PAC-POWR1220AT8-EV evaluation board (J4).
The ispPAC-POWR1220AT8 device operates with analog and digital core power supplies of 3.3V, To simplify evaluation work, the evaluation board was designed to operate from a single 4.5V to 5.5V power supply, which may be brought in through either a pair of banana plugs (J2 and J3), or a standard 5mm power plug (J1 - center tip positive). The evaluation board provides a linear regulator to provide the appropriate operating voltages for the ispPAC-
POWR1220AT8 device, as well as reverse polarity protection.
Connectors are provided for key functions and test points on this evaluation board, as shown In Figure 2. Power
may be supplied in one of two ways; either through two color coded (RED = +, BLACK = -) banana jacks in the upper right corner of the board or through a 5mm (center pin +) DC power connector (J1), The JTAG programming cable is connected to a keyed header (J4) in the upper right corner of the board. Another header (J5) provides access to the device’s I
2
C port. This header is pinned-out, and associated with interface circuitry so that in addition to providing a standard I
2
C bus connection (with on-board 2K pull-ups to 3.3V), it may also be driven by the Lattice
DL2download cable when the “Power Manager I
2
C Utility” in PAC-Designer is used.
Access to a subset of the ispPAC-POWR1220AT8 device’s I/O pins is available along the left edge of the assembly, where a 2x34 block of pads supports the attachment of test probes or a ribbon-cable connector. Pads for accessing the ATDI and TDISEL signals are provided immediately below the JTAG header (J4). An auxiliary connection for
OUT5/SMB Alert is provided on a pad below the I
2
C header (J5).
Figure 2. I/O Connections, Controls and Indicators
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Lattice Semiconductor PAC-POWR1220AT8-EV Evaluation Board
Two momentary switches, S2 and S3, are provided on the evaluation board. They are connected to IN4 and IN5, respectively. An 8-position dipswitch (S1) is provided on the evaluation board for the purpose of setting device inputs. Table 1 shows the options controlled by each switch:
Table 1. Switch S1 User Configuration Functions
Position
1
2
3
6
7
4
5
8
Function (when ON)
VPS1 – Voltage Profile Select bit 1
VPS0 – Voltage Profile Select bit 0
TDISEL
IN1
IN2
IN3
VMON12_POT
VMON11_POT
Switch positions 1 through 6 control logic inputs. When the switch is turned ON, the corresponding logic input goes
HIGH. If a logic input is to be driven from an external signal source, then its associated DIP switch should be set to the OFF position.
Switch positions 1 and 2 control Voltage Profile Select pins VPS1 and VPS0, respectively. If the device has been programmed for voltage profile control via VPS0 and VPS1, then these switches are used to select the active voltage profile.
Switch position 3 controls the TDI selector pin, TDISEL. This switch should be in the ON position in order to program the device through J4.
Switch positions 4-6 control logic inputs IN1-IN3, respectively.
When in the ON position, switches 7 and 8 connect VMON11 and VMON12 to the two linear potentiometers provided on the board. This lets the user interactively apply analog voltages to the VMON11 and VMON12 inputs without the use of additional hardware. Note that the ground-sense pins for VMON11 and VMON12 have been hardwired to ground in order to support this feature.
Several red LEDs are also provided on the evaluation board to indicate proper function and as aids to debugging.
LED D2 indicates that the on-board 3.3V supply is powered up. LED D3 is connected to the ispPAC-
POWR1220AT8 device’s TDO line, and will briefly flash when downloading, indicating that download data has made it to the device.
LEDs are also provided on digital outputs OUT5 through OUT20 so that a user may easily monitor the progress of sequence programs run on the evaluation board. Each of these LEDs uses a dual-resistor bias circuit that provides
CMOS-3.3V compatible logic levels.
The following four figures comprise the schematics for the the ispPAC-POWR1220AT8-EV evaluation board.
Figure 3 shows the on-board power-supply circuitry, Figure 4 shows the LED display and I
2
C adapter circuitry,
Figure 5 shows user control circuits, while Figure 6 shows connections to the device itself.
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Lattice Semiconductor
Figure 3. On-Board Power Supply
J3
D1
+5 V BA N A N A
(RED)
J2
C1
10µF
+
G N D BA N A N A
(BLACK)
C3
0.1µF
5mm
Po w er Jack
J1
+
PAC-POWR1220AT8-EV Evaluation Board
3
4
I N
I N
U2
OUT
TPS77733
OUT
5
6
C4
0.1µF
1 2
+
C2
10 µF
+3.3V
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Lattice Semiconductor
Figure 4. LED Indicators and I
2
C Port Interface
+3.3
V
R1
2K
PAC-POWR1220AT8-EV Evaluation Board
+3.3
V
14
R2
2K
D2
13
D4
1 2
D5
3 4
D6
5 6
D7
7 12
D 8
11 10
D9
9 8
‘P W R’
OUT5
OUT6
OUT7
OUT 8
OUT9
OUT10
+3.3
V
14
R3
2K
OUT11
OUT12
OUT13
OUT14
OUT15
OUT16
D10
13 12
D11
11 10
D12
1 2
D13
3 4
D14
5 6
D15
7 8
OUT17
OUT1 8
OUT19
OUT20
TDO
RESET
SDA
SCL
ATDI
D16
13 12 11
D17
1 2
D1 8
3 4
D19
5 6
D20
8 9 10 7
Q1
+3.3
V
R12
4.7k
R11
4.7k
Q2
R6
4.7k
R5
4.7k
+3.3
V
V CC
SDA
SDI N
J1.1
J1.2
J1.3
G N D
SCL
J1.7
J1.
8
5

Lattice Semiconductor
Figure 5. User Controls
V PS1
V PS0
TDISEL
I N 1
I N 2
I N 3
V MO N 12
V MO N 11
I N 4
I N 5
R13
1k
R14
1k
R15
1k
R16
1k
R17
1k
R1 8
1k
R19
1k
R20
1k
13 1 2 3 4 5 6 7
S2
S3
S1
5
6
7
8
1
2
3
4
PAC-POWR1220AT8-EV Evaluation Board
+3.3
V
R10
220
C10
0.1
u F
+3.3
V
R 8
1k
V MO N 12
+3.3
V
R7
1k
V MO N 11
R9
220
C9
0.1
u F
14 R4
2K
6

PLDCLK
MCLK
V PS0
V PS1
SDA
SCL
RESET b
V CCPROG
I N 1
I N 2
I N 3
I N 4
I N 5
I N 6
V MO N 1
V MO N 1GS
V MO N 2
V MO N 2GS
V MO N 3
V MO N 3GS
V MO N 4
V MO N 4GS
V MO N 5
V MO N 5GS
V MO N 6
V MO N 6GS
V MO N 7
V MO N 7GS
V MO N8
V MO N8 GS
V MO N 9
V MO N 9GS
V MO N 10
V MO N 10GS
V MO N 11
V MO N 12
Lattice Semiconductor
Figure 6. Device Connections
PAC-POWR1220AT8-EV Evaluation Board
+3.3
V
13 3 8 5 60 94 33
97
1
2
4
6
7
I N 1
I N 2
I N 3
I N 4
I N 5
I N 6
95
96
8 9
90
93
92
91
PLDCLK
MCLK
V PS0
V PS1
SDA
SCL
RESET b
47
46
50
4 8
52
56
55
5 8
51
54
53
57
62
61
64
63
66
65
6 8
67
70
69
72
71
V MO N 1
V MO N 1GS
V MO N 2
V MO N 2GS
V MO N 3
V MO N 3GS
V MO N 4
V MO N 4GS
V MO N 5
V MO N 5GS
V MO N 6
V MO N 6GS
V MO N 7
V MO N 7GS
V MO N8
V MO N8 GS
V MO N 9
V MO N 9GS
V MO N 10
V MO N 10GS
V MO N 11
V MO N 11GS
V MO N 12
V MO N 12GS
39
V CCPROG
PO
U1 ispPAC-
W R1220AT
3 22 36 43 88 9 8
8
45
1 8
19
20
21
23
24
25
12
14
15
16
17
8 6
8 5
42
40
8
9
10
11
H V OUT1
H V OUT2
H V OUT3
H V OUT4
OUT5/SMBA
OUT6
OUT7
OUT 8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
OUT15
OUT16
OUT17
OUT1 8
OUT19
OUT20
TRIM1
TRIM2
TRIM3
TRIM4
TRIM5
TRIM6
TRIM7
TRIM 8
8 4
8 3
8 2
8 0
79
75
74
73
ATDI
TDISEL
TDO
TDI
TMS
TCK
31
2 8
37
30
32
34
8 7
TRIM1
TRIM2
TRIM3
TRIM4
TRIM5
TRIM6
TRIM7
TRIM 8
H V OUT1
H V OUT2
H V OUT3
H V OUT4
OUT5
OUT6
OUT7
OUT 8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
OUT15
OUT16
OUT17
OUT1 8
OUT19
OUT20
ATDI
TDISEL
+3.3
V
V CC
TDO
TDI
TMS
G N D
TCK
J4.1
J4.2
J4.3
J4.6
J4.7
J4.
8
+3.3
V
C5 C6 C7 C 8
0.1
u F
(94)
0.1
u F
(13)
0.1
u F
(3 8 )
0.1
u F
(60)
7

Lattice Semiconductor
Figure 7. Silk Screen
PAC-POWR1220AT8-EV Evaluation Board
Figure 8. Component Side Copper (Layer 1)
8

Lattice Semiconductor
Figure 9. Ground Plane (Layer 2)
PAC-POWR1220AT8-EV Evaluation Board
Figure 10. Power Plane (Layer 3)
9

Lattice Semiconductor
Figure 11. Solder-side Copper (Layer 4)
PAC-POWR1220AT8-EV Evaluation Board
Quantity
2
8
1
2
2
2
2
1
4
1
4
1
1
2
1
1
1
8
1
18
1
Reference Designators
C1, C2
C3 to C10
D1
D2 to D19
J1
J2
J3
J4, J5
Q1
Q2
R1, R2, R3, R4
R5, R6, R11, R12
R7, R8
R9, R10
S2, S3
R13 to R20
S1
U1
U2 n/a n/a
Description
10 µ F 10V tantalum cap, Nichicon F931A106MBA
0.1
µ F 0603 SMD cap, Panasonic ECJ-1VB1C104K
Schottky diode, International Rectifier MBRS130LTR
Red LED, SMD1206 package, LiteOn LTST-C150KRKT
5mm DC power connector, CUI PJ-102BH
Banana Jack, red, SPC Technology 845-R
Banana Jack, Black, SPC Technology 845-B
8-position pin header, Molex 22-28-4084
MMBT3904LT1 NPN transistor, On-Semiconductor
MMBT3906LT1 PNP transistor, On-Semiconductor
2K resistor network, CTS 768141202G
4.7K 5% 0805 resistor, Yageo 9C08052A4701JLHFT
35mm slide pot, 1K, Alpha-Taiwan RA3043-20-10EB1-B13
220 Ohm 5% 0805 resistor, Yageo RC0805JR-07220RL
Momentary switch, Panasonic EVQPAD04M
1k ohm 5% 0805 resistor, Yageo 9C08052A1001JLHFT
8-position dipswitch, CTS 206-8ST ispPAC-POWR1220AT8
3.3V fixed regulator SOIC8, Texas Instruments TPS77733D
Printed circuit board, 4” x 5”, 4-layer
Rubber feet, 3M SJ-5003
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Lattice Semiconductor PAC-POWR1220AT8-EV Evaluation Board
• ispPAC-POWR1220AT8 Data Sheet
• Lattice Application Note AN6067, ispPAC-POWR1220AT8 I2C Hardware Verification Utility Users Guide.
Hotline: 1-800-LATTICE (North America)
+1-503-268-8001 (Outside North America) e-mail: isppacs@latticesemi.com
Internet: www.latticesemi.com
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