High Definition Audio
SoundMAX Codec
AD1882
FEATURES
FOUR 96 kHz ADCs
2 stereo headphone amplifiers
Microsoft Vista Premium logo for notebook and desktop
95 dB audio outputs, 90 dB audio inputs
Internal 32-bit arithmetic for greater accuracy
Impedance and presence detection on all jack pins
Digital synthesis PCBeep
C/LFE channel swapping
2 general-purpose digital I/O (GPIO) pins
Advanced power management modes
EAPD control for internal speakers
48-lead, Pb-free LFCSP_VQ package
2 independent stereo ADC pairs
Simultaneous record of up to 4 channels
Independent 8 kHz, 11.025 kHz, 16 kHz, 22.05 kHz, 32 kHz,
44.1 kHz, 48 kHz, 88.2 kHz, and 96 kHz sample rates
16-, 20-, and 24-bit resolution
SIX 96 kHz DACs
Stereo CD input w/GND sense
Mono out pin for internal speakers or telephony
Analog PCBeep input pin
3 independent stereo DAC pairs
Independent 8 kHz, 11.025 kHz, 16 kHz, 22.05 kHz, 32 kHz,
44.1 kHz, 48 kHz, 88.2 kHz, and 96 kHz sample rates
16-, 20-, and 24-bit PCM resolution
Selectable stereo mixer on outputs
S/PDIF OUTPUT
Supports 44.1 kHz, 48, kHz 88.2 kHz, and 96 kHz sample rates
16-, 20-, and 24-bit data widths; PCM and AC3 formats
Digital PCM gain control
DEDICATED AUXILIARY PINS
AD1882
DIGITAL
BEEP
H
D
A
U
D
I
O
I
N
T
E
R
F
A
C
E
DAC0
⌺
DAC1
⌺
DAC2
⌺
PORT G
⌺
MONO OUT
⌺
ADC0
⌺
PORT F
HP
HP
PORT D
PORT A
⌺
PORT C
⌺
PORT E
PCBEEP
PORT B
CD IN
ADC1
Figure 1. AD1882 Block Diagram
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel:781.329.4700
www.analog.com
Fax:781.461.3113
©2008 Analog Devices, Inc. All rights reserved.
AD1882
TABLE OF CONTENTS
Features ................................................................. 1
Revision History ...................................................... 2
General Description ................................................. 3
Additional Information .......................................... 3
Jack Configuration ................................................ 3
Specifications .......................................................... 4
Test Conditions .................................................... 4
Performance ........................................................ 4
General Specifications ............................................ 4
HD Audio Link Specifications .................................. 6
Power-Down States ............................................... 6
Absolute Maximum Ratings .................................... 7
ESD Caution ........................................................ 7
Environmental Conditions ...................................... 7
Pin Configuration and Function Descriptions ................. 8
HD Audio Widgets ................................................ 11
HD Audio Parameters ............................................. 12
Outline Dimensions ............................................... 16
Ordering Guide ..................................................... 16
REVISION HISTORY
4/08—Rev. 0 to Rev. A
Changed analog and digital power supply specifications......6
Changed analog and digital specifications and revised footnotes
in Power-Down States ............................................... 6
Changed revision ID in Widget Parameters .................. 13
Rev. A |
Page 2 of 16 |
April 2008
AD1882
GENERAL DESCRIPTION
The AD1882 audio codec and SoundMAX® software provides
superior HD audio quality that exceeds Vista Premium performance. The AD1882 has six DACs and four ADCs, two stereo
headphone ports, C/LFE swapping, digital and analog PCBeep,
and S/PDIF output, making the AD1882 the right choice for
desktop PCs where performance is the primary consideration.
The jack retasking feature on this product supports various configurations including platforms for 5.1 on 5 or 3 jacks, and front
panel jack retasking.
The AD1882 is available in a 48-lead RoHS compliant lead
frame chip scale package in both reels and trays. See Ordering
Guide on Page 16.
ADDITIONAL INFORMATION
This data sheet provides a general overview of the AD1882
SoundMAX codec’s architecture and functionality. Additional
information on the AD1882 is available in the AD1882 Programmers Reference Manual. Please contact your local Analog
Devices, Inc., sales representative for more information. For
information on SoundMAX codecs and software, see Analog
Devices website at www.analog.com/soundMAX.
Table 2. Typical Desktop Configuration with 5.1 on 3 Jacks
Port
Port A
Port B
Port C
Port D
Port E
Table 3. Typical Notebook Configuration
Port
Port A
Port B
Port C
Port D
Port E
JACK CONFIGURATION
The guidelines shown in Table 1 through Table 3 should be
used when selecting ports for particular functions.
Table 1. Typical Desktop Configuration with Discreet Jacks
Port
Port A
Port B
Port C
Port D
Port E
Port F
Port G
Function
Front Panel Headphone
Front Panel Microphone
Rear Panel Line-In
Rear Panel Line-Out/Headphone
Rear Panel Microphone
Rear Panel Surround
Rear Panel C/LFE
Rev. A |
Function
Front Panel Headphone
Front Panel Microphone
Rear Panel Line-In/Surround
Rear Panel Line-Out/Headphone
Rear Panel Microphone / C/LFE
Page 3 of 16 |
April 2008
Function
Headphone
Microphone
Internal Microphone
Internal Stereo Speakers
Docking Station Line-In/Microphone
AD1882
SPECIFICATIONS
TEST CONDITIONS
Parameter
Temperature
Digital Supply
Analog Supply
MIC_BIAS_IN (via Low-Pass Filter)
Sample Rate fS
Input Signal (Frequency Sine Wave)
Amplitude for THD + N
Analog Output Pass Band
DAC
Test Condition
25°C
3.3 V
3.3 V
5.0 V
48 kHz
1008 Hz
–3.0 dB Full Scale
20 Hz to 20 kHz
10 kΩ Output Load: Line Out Tests
32 Ω Output Load: Headphone Tests
0 dB Gain
ADC
PERFORMANCE
Parameter
Line-Out Drive (10 kΩ Loads—DAC to Pin)
Total Harmonic Distortion (THD + N)
Dynamic Range (–60 dB in Ref to fS A-Weighted)
Signal-to-Noise Ratio
Headphone Drive (32 Ω Loads—DAC to Pin)
Total Harmonic Distortion (THD + N)
Dynamic Range (–60 dB in Ref to fS A-Weighted)
Signal-to-Noise Ratio
Input Ports (Pin to ADC, Mic Boost = 0 dB)
Total Harmonic Distortion (THD + N)
Dynamic Range (–60 dB in Ref to fS A-Weighted)
Signal-to-Noise Ratio
Min
Typ
Max
Unit
–85
95
95
dB
dB
dB
–83
95
95
dB
dB
dB
–81
90
90
dB
dB
dB
GENERAL SPECIFICATIONS
Table 4. AD1882 General Specifications
Parameter
DIGITAL DECIMATION AND INTERPOLATION FILTERS—fS = 8 kHz to 192 kHz1
Pass Band
Pass-Band Ripple
Stop Band
Stop-Band Rejection
Group Delay
Group Delay Variation Over Pass Band
ANALOG-TO-DIGITAL CONVERTERS
Resolution
Gain Error (Full-Scale Span Relative to Nominal Input Voltage)2
Interchannel Gain Mismatch (Difference of Gain Errors)
ADC Offset Error1
ADC Crosstalk1
Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L)
Line Inputs to Other
Rev. A |
Page 4 of 16 |
Min
Typ
0
Max
Unit
0.4 fS
±0.005
Hz
dB
Hz
dB
1/fS
μs
0.6 fS
+20
0
–100
24
–85
–100
April 2008
±10
±0.5
±5
Bits
%
dB
mV
–80
dB
dB
AD1882
Table 4. AD1882 General Specifications (Continued)
Parameter
DIGITAL TO ANALOG CONVERTERS
Resolution
Gain Error (Full-Scale Span Relative to Nominal Input Voltage)1
Interchannel Gain Mismatch (Difference of Gain Errors)
Total Audible Out-of-Band Energy (Measured from 0.6 × fS to 100 kHz)1
DAC Crosstalk (Input L, Zero R, Read R_OUT; Input R, Zero L, Read L_OUT)1
DAC VOLUMES
Step Size (DAC-0, DAC-1, DAC-2)
Output Gain/Attenuation Range
Mute Attenuation of 0 dB Fundamental1
ADC VOLUMES
Step Size (ADCSEL-0, ADCSEL-1)
PGA Gain/Attenuation Range
Mute Attenuation of 0 dB Fundamental1
ANALOG MIXER
Signal-to-Noise Ratio (SNR) Input to Output
CD to Port D Output
Port B, C, or E to Port D Output
Port A to Port D Output
Port D to Port A Output
Step Size: All Mixer Inputs
Input Gain/Attenuation Range: All Mixer Inputs
ANALOG LINE LEVEL OUTPUTS
Full-Scale Output Voltage
Ports C, E, F, and G Mono Out
Output Impedance1
External Load Impedance1
Output Capacitance1
External Load Capacitance
ANALOG HP DRIVE OUTPUTS
Full-Scale Output Voltage
Ports A and D
Output Impedance1
External Load Impedance1
Output Capacitance1
External Load Capacitance1
ANALOG INPUTS
CD, Port D (When Used as Input)
Min
±10
±0.5
–85
–95
1.5
–58.5
+22.5
dB
dB
dB
–80
95
95
95
95
95
1.5
–34.5
1.0
2.83
+12.0
1.0
300
10
15
1000
7.5
V rms3
V p-p
V rms3
V p-p
V rms3
V p-p
V rms3
V p-p
V rms3
V p-p
kΩ
pF
15
Input Impedance1
Input Capacitance1
April 2008
V rms3
V p-p
Ω
kΩ
pF
pF
1000
0.5
32
Boost = 30 dB
dB
dB
dB
dB
dB
dB
dB
V rms3
V p-p
Ω
Ω
pF
pF
1.0
2.83
1
2.83
1
2.83
0.316
0.894
0.1
0.283
0.032
0.089
20
5
Bits
%
dB
dB
dB
dB
dB
dB
1.5
–58.5
Unit
0
–80
Boost = 20 dB
Page 5 of 16 |
Max
24
Microphone Boost Amplifier, Ports B, C, or E Boost = 0 dB
(When Used as Inputs)
Boost = 10 dB
Rev. A |
Typ
AD1882
Table 4. AD1882 General Specifications (Continued)
Parameter
Digital GPIO Pins: GPIO_0, GPIO_1/EAPD
Input Signal High (VIH)
Input Signal Low (VIL)
Input Leakage Current (Signal High, (IIH)
Input Leakage Current (Signal Low, (IIL)
IOUT = –500 μA
Output Signal High (VOH)
Output Signal Low (VOL)
IOUT = +1500 μA
S/PDIF_OUT
Output Signal High (VOH)
IOUT = –500 μA
IOUT = +1500 μA
Output Signal Low (VOL)
Power Supply
Analog (AVDD) 3.3 V ± 5%
Power Supply Range
Power Dissipation
Supply Current
Digital (DVDD) 3.3 V ± 10%
Power Supply Range
Power Dissipation
Supply Current
Digital I/O (DVIO) 3.3 V ± 10%
Power Supply Range
Power Dissipation
Supply Current
Power Supply Rejection (100 mV p-p Signal @ 1 kHz)1
Min
Typ
Max
150
50
DVIO × 0.72
0
DVIO
V
DVIO × 0.24 V
nA
μA
DVIO
V
DVIO × 0.10 V
DVIO × 0.72
0
DVIO
V
DVIO × 0.10 V
DVIO × 0.60
0
Unit
3.13
3.30
116
35
3.46
V
mW
mA
2.97
3.30
162
49
3.63
V
mW
mA
2.97
3.30
3.96
1.20
80
3.63
V
mW
mA
dB
1
Guaranteed but not tested.
Measurements reflect main ADC.
3
RMS values assume sine wave input.
2
HD AUDIO LINK SPECIFICATIONS
HD Audio signals comply with the High Definition Audio specifications. Please refer to these specifications at
www.intel.com/standards/hdaudio.
POWER-DOWN STATES
Table 5. Power-Down States
Parameter
Function Node In D0, All Nodes Active
Function Node in D3
Codec in RESET
Individual block power savings
DAC Pair Powered Down Saves (Each)
ADC Pair Powered Down Saves (Each)
Mixer Power Control (and Associated Amps) Saves
MIC_BIAS Powered Down Saves1
1
IDVDD Typ
49
16
3
IAVDD Typ
35
0.7
3
Unit
mA
mA
mA
6
5
0
0
6
4.4
3
1.0
mA
mA
mA
mA
Powering down the MIC_BIAS powers down all port MIC_BIAS pins. This disables all microphone bias circuits set to 100% or 50%, setting them to the high-Z state. The
0 Ω and high-Z states remain unaffected by the MIC_BIAS power state.
Rev. A |
Page 6 of 16 |
April 2008
AD1882
ABSOLUTE MAXIMUM RATINGS
ENVIRONMENTAL CONDITIONS
Stresses greater than those listed below may cause permanent
damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions above
those indicated in the operational section of this specification is
not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Ambient Temperature Rating:
Power Supplies
Digital (DVDD)
Digital I/O (DVIO)
Analog (AVDD)
Input Current (Except Supply Pins)
Analog Input Voltage (Signal Pins)
Digital Input Voltage (Signal Pins)
Ambient Temperature (Operating)
Storage Temperature
Rating
–0.30 V to +3.65 V
–0.30 V to +3.65 V
–0.30 V to +3.65 V
±10.0 mA
–0.30 V to AVDD + 0.3 V
–0.30 V to DVIO + 0.3 V
0°C to +70°C
–65°C to +150°C
TAMB = TCASE – (PD × θCA)
TCASE = case temperature in °C
PD = power dissipation in W
θCA = thermal resistance (case-to-ambient)
θJA = thermal resistance (junction-to-ambient)
θJC = thermal resistance (junction-to-case)
All measurements per EIA-JESD51 with 2S2P test board per
EIA-JESD51-7.
Package
LFCSP_VQ
ESD CAUTION
ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary protection circuitry, damage
may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to
avoid performance degradation or loss of functionality.
Rev. A |
Page 7 of 16 |
April 2008
θJA
θJC
θCA
47
15
32
Unit
°C/W
AD1882
SPDIF_OUT
GPIO_1/EAPD
RESERVED (NC)
RESERVED (NC)
PORT-G_R
PORT-G_L
AVSS
PORT-A_R
MONO_OUT
PORT-A_L
AVDD
RESERVED (NC)
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
48
47
46
45
44
43
42
41
40
39
38
37
DVCORE
1
36
PORT-D_R
GPIO_0
2
35
PORT-D_L
DVI/O
3
34
SENSE_B/SRC_A
DVSS
4
33
MIC_BIAS_IN
SDATA_OUT
5
32
RESERVED (NC)
BIT_CLK
6
31
MIC_BIAS-E
30
RESERVED (NC)
29
MIC_BIAS-C
28
MIC_BIAS-B
27
VREF_FLT
AD1882JCPZ
TOP VIEW
DVSS
7
(Not To Scale)
PCBEEP
12
25
AVDD
15
16
17
18
19
20
21
22
23
Figure 2. AD1882 48-Lead Package and Pinout
Rev. A |
Page 8 of 16 |
April 2008
24
PORT-C_R
14
PORT-E_R
13
PORT-C_L
AVSS
PORT-B_R
26
PORT-B_L
11
CD_R
RESET
CD_GND
10
CD_L
SYNC
PORT-F_R
9
PORT-F_L
DVDD
PORT-E_L
8
SENSE_A/SRC_B
SDATA_IN
AD1882
Table 6. AD1882 Pin Descriptions
Mnemonic
DIGITAL INTERFACE
SDATA_OUT
Pin No.
Function
Description
5
I
BIT_CLK
SDATA_IN
SYNC
RESET
DIGITAL I/O
GPIO_0
GPIO_1/EAPD
6
8
10
11
I
I/O
I
I
Link Serial Data Output. AD1882 input stream. Clocked on both edges of the
BIT_CLK.
Link Bit Clock. 24.000 MHz serial data clock.
Link Serial Data Input. AD1882 output stream Clocked only on one edge of BIT_CLK.
Link Frame Sync.
Link Reset. AD1882 master hardware reset
2
47
I/O
I/O
SPDIF_OUT
JACK SENSE AND EAPD
SENSE_A/SRC_B
SENSE_B/SRC_A
ANALOG I/O
PCBEEP
PORT-E_L
PORT-E_R
PORT-F_L
PORT-F_R
CD_L
CD_GND
48
O
General-Purpose Input/Output Pin. Digital signal used to control external circuitry.
General-Purpose Input/Output Pin/EAPD Pin. Digital signal used to control external
circuitry. Defaults to high-Z. When used as EAPD: high-Z = amp-on, DVSS = amp off.
S/PDIF_OUT. Supports S/PDIF output.
13
34
I/O
I/O
JACK SENSE A-D Input/Sense B Drive.
JACK SENSE E-H Input/Sense A Drive.
12
14
15
16
17
18
19
LI
LI, MIC, LO, SWAP
LI, MIC, LO, SWAP
I/O
I/O
LI
LI
CD_R
PORT-B_L
PORT-B_R
PORT-C_L
PORT-C_R
PORT-D_L
PORT-D_R
PORT-A_L
MONO_OUT
PORT-A_R
PORT-G_L
PORT-G_R
FILTER/REFERENCE
MIC_BIAS-B
MIC_BIAS-C
MIC_BIAS-E
DVCORE
20
21
22
23
24
35
36
39
40
41
43
44
LI
LI, MIC, HP, LO
LI, MIC, HP, LO
LI, MIC, LO
LI, MIC, LO
LI, HP, LO
LI, HP, LO
LI, MIC, HP, LO
LO
LI, MIC, HP, LO
LO, SWAP
LO, SWAP
Monaural Input from System for Analog PCBeep.
Auxiliary Input/Output Left Channel.
Auxiliary Input/Output Right Channel.
Auxiliary Input/Output Left Channel.
Auxiliary Input/Output Right Channel.
CD Audio Left Channel.
CD Audio Analog Ground Reference (for Differential CD Input). Must be connected to
AGND via 0.1 mF capacitor if not in use as CD_GND.
CD Audio Right Channel.
Front Panel Stereo MIC/Line-In.
Front Panel Stereo MIC/Line-In.
Rear Panel Stereo MIC/Line-In.
Rear Panel Stereo MIC/Line-In.
Rear Panel Headphone/Line-Out.
Rear Panel Headphone/Line-Out.
Front Panel Headphone/Line-Out.
Monaural Output to Internal Speaker or Telephony Subsystem Speakerphone.
Front Panel Headphone/Line-Out.
Rear Panel C/LFE Output.
Rear Panel C/LFE Output.
Switchable Microphone Bias. For use with Port B (Pins 21, 22).
Switchable Microphone Bias. For use with Port C (Pins 23, 24).
Switchable Microphone Bias. For use with Port E (Pins 14, 15).
CAUTION: DO NOT APPLY 3.3 V TO THIS PIN!
Filter connection for internal core voltage regulator.
This pin must be connected to filter caps: 10 μF, 1.0 μF, and 0.1 μF connected in
parallel between Pin 1 and DVSS (Pin 4).
VREF_FLT
27
O
Voltage Reference Filter. This pin must be connected to filter caps: 1.0 μF and 0.1μF
connected in parallel between Pin 27 and AVSS (Pins 26, 42).
The symbols used in this table are defined as: I = Input, O = Output, LI = Line level input, LO = Line level output, HP = Output capable of
driving headphone load, MIC = Input supports microphones with MIC bias and boost amplifier, SWAP = Outputs can swap L/R channels
(typically used to support C/LFE or shared C/LFE function).
28
29
31
1
O
O
O
O
Rev. A |
Page 9 of 16 |
April 2008
AD1882
Table 6. AD1882 Pin Descriptions (Continued)
Mnemonic
POWER AND GROUND
DVI/O (3.3V)
DVSS
DVDD (3.3 V)
Pin No.
Function
3
4, 7
9
I
I
I
Description
Connect to the I/O Voltage Used for the HD Audio Controller Signals.
Digital Supply Return (Ground).
Digital Supply Voltage 3.3 V. This is regulated down to DVCORE on Pin 1 to supply the
internal digital core internal to the AD1882.
25, 38
I
CAUTION: DO NOT APPLY 5.0 V TO THESE PINS!
AVDD (3.3 V)
Analog supply voltage 3.3 V ONLY.
Note: AVDD supplies should be well regulated and filtered as supply noise degrades
audio performance.
MIC_BIAS_IN
33
I
Source Power for Microphone Bias Boost Circuitry.
AVSS
26, 42
I
Analog Supply Return (Ground). AVSS should be connected to DVSS using a
conductive trace under, or close to, the AD1882.
The symbols used in this table are defined as: I = Input, O = Output, LI = Line level input, LO = Line level output, HP = Output capable of
driving headphone load, MIC = Input supports microphones with MIC bias and boost amplifier, SWAP = Outputs can swap L/R channels
(typically used to support C/LFE or shared C/LFE function).
Rev. A |
Page 10 of 16 |
April 2008
AD1882
HD AUDIO WIDGETS
In the following table, node IDs that are not shown are reserved
for future use.
Table 7. HD Audio Widgets
Node ID
00
01
02
03
04
05
08
09
0B
0C
0D
10
11
12
13
14
15
16
17
18
19
1A
1B
1D
1E
20
21
22
23
24
26
27
29
2A
2C
2D
2F
37
39
3A
3C
Name
ROOT
FUNCTION
S/PDIF DAC
DAC_0
DAC_1
DAC_2
ADC_0
ADC_1
S/PDIF Mix Selector
ADC Selector 0
ADC Selector 1
Digital Beep
Port A (Headphone)
Port D (Front L/R)
Mono Out
Port B (Front Mic)
Port C (Line In)
Port F (Surr Back)
Port E (Rear Mic)
CD In
Mixer Power-Down
Analog PCBeep
S/PDIF Out
S/PDIF Mixer
Mono Out Mixer
Analog Mixer
Mixer Output Atten
Port A Mixer
VREF Power-Down
Port G (C/LFE)
Port E Mixer
Port G Mixer
Port D Mixer
Port F Mixer
Port C Mixer
Stereo Mix Down
BIAS Power-Down
Port A Out Selector
Port B Boost
Port C Boost
Port E Boost
Type ID
x
x
0
0
0
0
1
1
3
3
3
7
4
4
4
4
4
4
4
4
5
4
4
2
2
2
3
2
F
4
2
2
2
2
2
2
F
3
3
3
3
Type
Root
Function
Audio Output
Audio Output
Audio Output
Audio Output
Audio Input
Audio Input
Audio Selector
Audio Selector
Audio Selector
Beep Generator
Pin Complex
Pin Complex
Pin Complex
Pin Complex
Pin Complex
Pin Complex
Pin Complex
Pin Complex
Power Widget
Pin Complex
Pin Complex
Audio Mixer
Audio Mixer
Audio Mixer
Audio Selector
Audio Mixer
Vendor Defined
Pin Complex
Audio Mixer
Audio Mixer
Audio Mixer
Audio Mixer
Audio Mixer
Audio Mixer
Vendor Defined
Audio Selector
Audio Selector
Audio Selector
Audio Selector
Rev. A |
Description
Device identification
Designates this device as an audio codec
S/PDIF digital stream output interface
Headphone/surround side (7.1) channel digital/audio converters
Stereo front channel digital/audio converters
Stereo C/LFE channel digital/audio converters
Stereo record channel 1 audio/digital converters
Stereo record channel 2 audio/digital converters
Selects which ADC drives the S/PDIF mixer
Selects and amplifies/attenuates the input to ADC_0
Selects and amplifies/attenuates the input to ADC_1
Internal digital PCBeep signal
Front panel headphone/microphone jack
Rear panel front/headphone jack
Monorail output pin (internal speakers or telephony system)
Front panel microphone/headphone jack
Rear panel line-in jack
Rear panel surround-rear (5.1) jack
Rear panel mic jack
Analog CD input
Powers down the analog mixer and associated amps
External analog PCBeep signal input
S/PDIF output pin
Mixes the selected ADC with the digital stream to drive S/PDIF out
Selects which source drives the mono out signal
Mixes individually gainable analog inputs
Attenuates the mixer output to drive the Port mixers
Mixes the Port A selected DAC and mixer output amps to drive Port A
Powers down the internal and external VREF circuitry
Rear panel C/LFE jack
Mixes DAC_1 and mixer output amps to drive Port E
Mixes DAC_1 and mixer output amps to drive Port G
Mixes DAC_0 and mixer output amps to drive Port D
Mixes DAC_2 and mixer output amps to drive Port F
Mixes the Port C selected DAC and mixer output amps to drive Port C
Mixes the stereo L/R channels to drive mono output
Powers down the internal MIC_BIAS_FILT and all MIC_BIAS pins
Selects the Port A DAC (0, 1)
Microphone boost amp for Port B
Microphone boost amp for Port C
Microphone boost amp for Port E
Page 11 of 16 |
April 2008
AD1882
HD AUDIO PARAMETERS
The SSID value is set on codec power-up only. SSID is not reset
by link or soft reset in order to preserve modifications by BIOS
control.
Table 8. Root and Function Node Parameters
Node ID
00
01
1
Name
ROOT
FUNCTION
Vendor ID
00
01
0x11D4 1882
Revision ID
021
03
0x0010 0300
Sub Node
Count
04
0x0001 0001
0x0002 003B
Func. Group Audio F.G.
Type
Caps
05
08
GPIO Caps
11
0x0000 0001 0x0001 0C0C 0x4000 0002
Subject to change with silicon stepping.
Table 9. Subsystem ID1
Node ID
0x01
1
Name
FUNCTION
Type
Function
Value
0xBFD2 0000
31:16
SSID
0xBFD2
The default SSID is over-written by platform BIOS after power on. It is preserved across HD Audio link reset and verb reset.
Rev. A |
Page 12 of 16 |
April 2008
15:8
SKU
0x00
7:0
ASM ID
0x00
AD1882
Table 10. Widget Parameters
Node ID
01
02
03
04
05
08
09
0B
0C
0D
10
11
12
13
14
15
16
17
18
19
1A
1B
1D
1E
1F
20
21
22
23
24
26
27
29
2A
2C
2D
2F
37
39
3A
3C
Widget
Capabilities
09
00000480
0003031D
00000405
00000405
00000405
00100501
00100501
00300301
0030010D
0030010D
0070000C
0040018D
0040058D
0040050C
00400081
0040018D
0040018D
0040098D
00400001
00500500
00400000
00400301
00200303
00200103
00F00100
0020010B
0030010D
00200103
00F00100
0040098D
00200103
00200103
00200103
00200103
00200103
00200100
00F00100
00300101
0030010D
0030010D
0030010D
PCM Size,
Rate 0A
000E01FF
000E01E0
000E01FF
000E01FF
000E01FF
000E01FF
000E01FF
Stream
Formats
0B
00000001
00000005
00000001
00000001
00000001
00000001
00000001
Pin
Input Amp ConnList
Capabilities Capabilities Length
0C
0D
0E
80000000
00000001
00000000
00000000
00000000
00000001
00000001
00000002
00000008
00000008
00000000
0000373F
00000001
0001003F
00000001
00010010
00000001
00003727
00000000
00003737
00000001
00000017
00000001
00003737
00000001
00000020
00000000
00000002
00000020
00000000
00000010
00000001
80000000
00000002
80000000
00000002
00000010
00000001
80051F17
00000008
00000001
80000000
00000002
00000008
00000017
00000001
80000000
00000002
80000000
00000002
80000000
00000002
80000000
00000002
80000000
00000002
00000001
00000003
00000002
00000001
00000001
00000001
Rev. A |
Page 13 of 16 |
April 2008
Power
States
0F
00000009
00000009
00000009
00000009
00000009
00000009
00000009
00000009
Output
Processing Amp
Caps
Capabilities
10
12
00052727
80052727
00052727
00052727
00052727
80053627
80053627
800B0F0F
80000000
80000000
80051F1F
80000000
80000000
80000000
00000009
80051F1F
80000000
00270300
00270300
00270300
Volume
Knob
Capabilities
13
AD1882
Table 11. Connection List
Node ID
02
03
04
05
08
09
0B
0C
0D
10
11
12
13
14
15
16
17
18
19
1A
1B
1D
1E
1F
20
21
22
23
24
26
27
29
2A
2C
2D
2F
37
39
3A
3C
Connections
[0–3]
0000001D
0000000C
0000000D
00000908
18BC3911
18BC3911
[4–7]
20123B3B
20123B3B
0
1
NID
1D
I
0C
0D
08
11
11
00000022
00000029
0000002D
22
29
2D
0000002C
0000002A
00000026
2C
2A
26
00002120
20
00000002
00000B01
00002104
00000002
12113A39
00000020
00002137
A2209811
00000027
00002105
00002105
00002104
00002106
00002131
0000001E
00171514
00000403
00000014
00000015
00000017
02
01
04
02
39
20
37
11
27
05
05
04
03
03
1E
14
03
14
15
17
1A183B3C
BC30AE24
2
3
I
4
NID
I
5
NID
I
6
NID
I
7
NID
I
NID
NID
I
NID
09
39
39
1
1
3C
3C
18
18
3B
3B
3B
3B
12
12
20
20
3A
11
12
3C
3B
18
1A
21
18
20
22
24
2E
30
21
0B
21
1
1
21
21
21
21
21
15
04
Rev. A |
17
Page 14 of 16 |
April 2008
1
1
3C
AD1882
In Table 12, default configuration values are set on codec
power-up only. Default configuration values are not reset by
link or soft reset to preserve modifications by BIOS control.
Table 12. Default Configuration Bytes
31:30
29:28
27:24
23:20
19:16
15:12
Location
Name
Port A (Headphone)
Port D (Front L/R)
Mono Out
Port B (Front Mic)
Port C (Line In)
Port F (Surr Back)
Port E (Rear Mic)
CD IN
Analog PCBeep
S/PDIF Out
Port G (C/LFE)
Value
0221401F
01014010
901701F0
02A190F0
01813021
01011012
01A19020
9933012E
90F701F0
014511F0
01016011
Connectivity
Jack
Jack
Fixed
Jack
Jack
Jack
Jack
Fixed
Fixed
Jack
Jack
Chasis
External
External
Internal
External
External
External
External
Internal
Internal
External
External
7:4
3:0
Def Assn
1
1
F
F
2
1
2
2
F
F
1
Sequence
F
0
0
0
1
2
0
E
0
0
1
Misc.
Position
Front
Rear
N/A
Front
Rear
Rear
Rear
Special 3
N/A
Rear
Rear
Rev. A |
8
Def. Device
HP Out
Line Out
Speaker
Mic In
Line In
Line Out
Mic In
CD
Other
SPDIF Out
Line Out
Page 15 of 16 |
Conn Type Color
1/8” Jack
Green
1/8” Jack
Green
Other Analog Unknown
1/8” Jack
Pink
1/8” Jack
Blue
1/8” Jack
Black
1/8” Jack
Pink
ATAPI
Unknown
Other Analog Unknown
Optical
Black
1/8” Jack
Orange
April 2008
JD Over
Ride
0
0
1
0
0
0
0
1
1
1
0
AD1882
OUTLINE DIMENSIONS
Dimensions are shown in millimeters.
7.00
BSC SQ
0.60 MAX
0.60 MAX
37
36
PIN 1
INDICATOR
TOP
VIEW
1
5.25
5.10 SQ
4.95
(BOTTOM VIEW)
25
24
12
13
0.25 MIN
5.50
REF
0.80 MAX
0.65 TYP
12° MAX
PIN 1
INDICATOR
48
EXPOSED
PAD
6.75
BSC SQ
0.50
0.40
0.30
1.00
0.85
0.80
0.30
0.23
0.18
0.05 MAX
0.02 NOM
0.50 BSC
SEATING
PLANE
0.20 REF
COPLANARITY
0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
Figure 3. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
7 mm x 7 mm Body, Very Thin Quad
(CP-48-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD1882JCPZ1
AD1882JCPZ-RL1
1
Temperature Range
0°C to 70°C
0°C to 70°C
Package Description
48-Lead LFCSP_VQ
48-Lead LFCSP_VQ, 13” Tape and Reel
Z = RoHS Compliant Part.
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06826-0-4/08(A)
Rev. A |
Page 16 of 16 |
April 2008
Package Option
CP-48-1
CP-48-1