Dr. Aravind Dasu, Assistant Professor Electrical and Computer Engineering Department, Utah State University Director of the Micron Research Center http://www.usu.edu/mrc Reconfigurable Computing Group http://www.usu.edu/rcg Education 1997: Bachelor of Engineering in Electronics & Communication. Bangalore University, India 2000: MS in Electrical Engineering, Arizona State University, Tempe Arizona 2004: PhD in Electrical Engineering, Arizona State University, Tempe, Arizona Employment History 1999: Summer Intern, Motorola Video Processing Research Labs. Schaumburg, IL 2001: Summer + Fall Intern, ARM Microprocessor Design Center, Austin, TX Sept 2004 to present: Assistant Professor, ECE department. Utah State University Research, Scholarly and Creative Activities Director of the Micron Research Center (3D Integrated Circuit Technologies): An Interdisciplinary research involving faculty from the departments of Mechanical and Aerospace Engineering, Physics and Electrical and Computer Engineering. Director of the Utah Centers of Excellence on Hybrid and Adaptive Multimedia Processors: A first time research and development center intended to license technologies and spin out a startup company on the innovation campus Journal Publications J1. Sudarsanam, Hauser, Dasu, Young “A Power Efficient Linear Equation Solver on a Multi‐ FPGA Accelerator”, accepted to the International Journal of Computers and Applications. Jan 2009. J2. Phillips, Sudarsanam, Samala, Carver, Kallam, Dasu. “Methodology to derive Polymorphic Soft‐IP Cores for FPGAs”, in print IET CDT (formerly IEE CDT), 2008. J3. Hauser, Dasu, Sudarsanam, Young. “Performance of a LU decomposition on a Multi‐ FPGA system compared to a low power commodity microprocessor system”, Proc. Special Issue of Journal of Scalable Computing: Practice and Experience High Performance Reconfigurable Computing (HPRC). Pg: 373‐385. Vol. 8, no. 4. Dec 2007. J4. Dasu, Sudarsanam, Panchanathan “Design of Embedded Compute Intensive Processing Elements and Their Scheduling in a Reconfigurable Environment”, Canadian Journal of Electrical and Computer Engineering (an IEEE publication). Vol. 30, No. 2, Spring 2005. J5. Dasu and Panchanathan. “A Wavelet Based Sprite Codec”, IEEE Transactions on Circuits and Systems for Video Technology, Vol. 14, No 2, February 2004. Pg(s) 244‐255. J6. Dasu and Panchanathan. “Reconfigurable Media Processing”, Parallel Computing (Elsevier) 28 (2002). Pg(s) 1111 ‐ 1139. J7. Dasu and Panchanathan. “A Survey of Media Processing Approaches”, IEEE Transactions on Circuits and Systems for Video Technology, Vol. 12, No 8, Aug 2002. Pg(s) 633 – 645. Journal papers submitted in 2008 JS1. Barnes, Dasu, Carver, Kallam, “Dynamically Reconfigurable Systolic Array Accelerators: A case Study with EKF and DWT Algorithms”, in‐review with the IET Proceedings on Computers and Digital Techniques. JS2. Dasu, Carver, Phillips, “An FPGA Simulated Annealing Kernel Accelerator for Space Borne Applications”, in‐review with the International Journal of Reconfigurable Computing. JS3. Peak, Dasu, Voddi, Carver, “Bio‐inspired Self Healing of Soft Errors in Many‐Core Processors”, in‐review with the IEEE Transactions on Computers. JS4. Clements, Chandrakar, Dasu, “Analysis of Pixel Distribution on FPGA BRAMs for Block Motion Estimation”, submitted to and rejected by the IEEE Transactions on Circuits and Systems for Video Technology. This paper is being revised and resubmitted. Refereed conference papers C1. Akoglu, Dasu, Panchanathan. “Application specific low power hybrid FPGA architecture design”, Proc. of SPIE’s conference on embedded processors for Multimedia Communications. Volume 5683, pp. 21‐31. San Jose Jan. 2005. C2. Dasu, Sudarsanam, “High Level ‐ Application Analysis Techniques & Architectures ‐ to Explore Design possibilities for Reduced Reconfiguration Area Overheads in FPGAs executing Compute Intensive Applications”, Proc. of the 19th IEEE IPDPS conference. pp. 158a. April 2005. Denver, Colorado. C3. Young, Sudarsanam, Dasu, Hauser. “Memory Support Design for LU Decomposition on the Starbridge Hypercomputer”, Proc. of the IEEE International conference on Field Programmable Technology (ICFPT) Dec. 2006, Thailand. C4. Phillips, Areno, Rogers, Dasu, Eames. “An investigation into On‐Chip load balancing architectures for accelerating Molecular Dynamics computations”, Proceedings of the 2007 IEEE IPDPS conference. March 2007. Pages: 1‐6. C5. Areno, Eames, Dasu. “An automated Micro‐architecture design tool for FPGAs”, Proceedings of the 2007 Reconfigurable Summer Systems Institute (RSSI) July 2007 C6. Dasu, Phillips. “Deriving FPGA based custom soft‐core microprocessors for Mission Planning Algorithms”, Proceedings of the 21st annual Small Satellite conference. Aug. 2007. C7. Dasu, Phillips. “An ASIP architecture framework to facilitate automated design space exploration and synthesis for Iterative Repair solvers”, Proceedings of the NASA Science and Technology Conference (NSTC) 2007. C8. Phillips, Dasu, "Deriving an efficient, application‐specific, fpga‐based pipelined processor," Proceedings of the 4th annual reconfigurable summer systems institute conference (RSSI), 2008., July 2008 C9. Barnes, Dasu, “Hardware software co‐designed extended kalman filter on an FPGA”, Proc. Of the Engineering of Reconfigurable Systems and Algorithms (ERSA), July 14‐ 17, Las Vegas, NV. 2008 C10. Dasu, Panchanathan. “Reconfigurable Media processors”, Proc. of ITCC 2004, Las Vegas. C11. Dasu, Akoglu, Panchanathan. “An Analysis Tool Set for Reconfigurable Media Processing,” ERSA 2003, Las Vegas, Nevada C12. Dasu, Panchanathan, “Lifting kernel based sprite codec,” Proc. of VCIP 2001, California, January 2001. C13. Nagaraj, Dasu, Panchanathan, “Complexity analysis of Sprite encoding in MPEG‐4,” Proc. of SPIE, Media Processors 2001, California, January 2001. C14. Mohan, Dasu, Panchanathan. “Temporal Partitioning for advanced partially Reconfigurable architectures,” Proc. Of Reconfigurable Technology. FPGAs and Reconfigurable Processors for Computing and Communications III. Denver, August 2001. C15. Dasu, Nagaraj, Subramaniam, Panchanathan, “Arithmetic Precision for Perspective Transform in Sprite Decoding of MPEG‐4,” Proc. of SPIE, Media Processors 2000, California, January 2000. C16. Raghavendra, Dasu, Panchanathan. “Complexity analysis of Sprites in MPEG4”, Proc. SPIE Vol. 4313, p. 69‐73, Media Processors 2001 Non‐refereed Conference posters Cp1. Phillips, Hariharan, Dasu and Peak. “FPGA‐based Modeling of Spatio‐temporal Interactive Systems”, Presented at the 8th Military and Aerospace Conference on Programmable Logic Devices conference (MAPLD 05). September. 2005. Washington D.C. Cp2. Gakkhar, Dasu. “Hardware Implementation of 2‐D Wavelet Transforms in Viva on Starbridge Hypercomputer” Presented at the 8th MAPLD conference. A NASA sponsored conference. September. 2005. Washington D.C. Cp3. Phillips, Areno, Dasu, Eames. “An FPGA‐Based Dynamic Load‐Balancing Processor Architecture for Solving N‐body Problems”, Presented at the 10th HPEC workshop, MIT Lincoln Labs. Sept 2006. Invited Conference Organization • Invited to organize a special session at the International Conference on Engineering of Reconfigurable Systems and Algorithms http://webest.uk.com/ersa08/. Topic of special session: Reconfigurable Computing in Space based Applications. External Funding: Total = $1.53 million after joining USU • • • • • Dasu (PI) “Micron Research Center. Theme – 3D integrated circuits” Micron Technology Foundation, Jan 2008 – Dec 2012, $ 1 million Dasu (PI), Gunther (Co‐PI) “CHAMP center for hybrid and adaptive multimedia processors” Utah Centers of Excellence program (COEP) July 1007 – June 2008, $ 50,000 Dasu (PI) “An Integrated Software Environment to Design Polymorphic Fault Tolerant Processors for Command and Control Functions on RadHard FPGAs.” NASA, March 2006‐ June 09, $ 288,827 Eames (PI), Dasu (Co‐PI) “C to FPOA compiler” MathStar Inc., Nov 2007 – June 2008, $ 65,000 Hauser (PI), Dasu (Co‐PI) “Lower/Upper decomposition and solutions on FPGAs”, • • Lockheed Martin Corp. August 2005‐ Sept 06, $ 99,095 Dasu (PI) “USU development project”, Starbridge Systems Inc. Oct 2004‐ Oct 05, $ 15,600 Dasu (PI) “Development of polymorphic fundamental Image processing objects”, Starbridge Systems Inc., June 2005‐ June 06, $ 15,600 Technology Transfer, Patents and Royalties • 2008: Two Provisional Patents filed o Architecture Template for Simulated Annealing Processor Derivation o Method for Deriving an Efficient, Application‐Specific, FPGA‐Based Pipelined Processor • 2008: Royalty payment received from Mathstar Inc. for technology related to the second provisional patent ($ 10K) Mentoring of Students MS Thesis (Plan A): 1. Mr. Seth Young (graduated Fall 2006) and employed by Micron 2. Mr. Chandrakar Shant (expected graduation date June 2009) 3. Mr. Hari Samala (expected graduation date June 2009) 4. Mr. Robert Barnes (graduated Nov 2008) and employed by Sandia National Labs 5. Mr. Jeff Carver (defense date Feb 2009) 6. Mr. Ram Kallam (expected graduation date June 2009) 7. Mr. Varun Voddi (defense date Feb 2009) 8. Mr. Abe Clements (expected graduation date June 2010) 9. Ms. Saranya Chandrasekaran (expected graduation in 2010) PhD: 1. Mr. Jonathan Phillips (graduated Oct 2008), employed by SDL 2. Mr. Arvind Sudarsanam (expected defense date June 2009) Undergraduates: 1. Mr. Abe Clements (concurrent program) is participating in the Micron Research Center activities 2. Mr. Josh Templin (concurrent program) is participating in the NASA project Publications with students: 22 (All of my publications involve students) Service • Invited by the Dean to serve on the ECE department Head search Committee • Invited by the Department of Energy to serve a reviewer to a program on Nuclear Non­ proliferation @ Los Alamos National Labs • Program committee member on ERSA, RSSI, ReConFig and other FPGA related conferences • ECE department graduate committee member • Reviewer to journals in the IEEE and ACM • Proposal review panel member for NSF and NASA