CMOS ICs are being produced
using a variety of processes,
and considerable data is now
available on their reliability
and failure mechanisms.
Reliability of CMOS
Integrated Circuits
There are basic differences between MOS and
bipolar digital integrated circuits, and between
CMOS and other digital MOS technologies. Some of
those differences have an impact on the reliability of
the various types of digital integrated circuits.
Accelerated-life tests and field use, along with other
available data on CMOS reliability, indicate that
CMOS devices, properly made, are equal in reliability to bipolar digital circuits of equal complexity. In
this article, we look at CMOS packaging, circuit
complexity, and electrostatic gate protection and
compare CMOS to other types of digital IC
technology.
CMOS IC Technology
The basic building block for CMOS integrated
circuitry1-4 is shown in Figure 1. In contrast to other
types of MOS integrated circuits, the CMOS circuits contain no load resistors; this results in very
low quiescent dissipation. The voltage transfer
characteristics of a basic CMOS inverter are shown
in Figure 2, and typical curves of dynamic dissipation versus frequency in Figure 3.
CMOS ICs were originally produced in volume in
1968. The technology has evolved from that used for
the original RCA CD4000 series' devices (6-15 volts)
to the CD4000A series (3-15 volt) devices2 in 1971,
and to the 4000B series (3-20 volt) devices 3,6 in
1974. The introduction, in 1970, of plasticencapsulated devices5 was instrumental in achieving even wider acceptance of the popular 4000
series.
CMOS ICs are being produced by a number of
manufacturers using a variety of different processes.2'2w5-'9 Ion implantation is being used to form
p-wells, 3,20 to adjust thresholds,6 and to avoid field
inversion. Metallization materials have included
aluminum, polycrystalline silicon, and titaniumpalladium-gold or titanium-platinum-gold.52'2 Tech6
0018-9162/78/1000-0006$00.75 O 1978 IEEE
niques for attaching the die to the substrate have in-
cluded gold-silicon eutectic bonding and epoxy attachment.' Although most CMOS ICs being
manufactured today are bulk silicon types, devices
fab'ricated on thin-film silicon-on-sapphire
substrates are being produced.3'7"1'9-1419
At present, 4000A series CMOS ICs are commercially available from more than 10 suppliers, and
standardized 4000B series devices22 are or will be
available from at least nine. Devices qualified to
MIL M-38510, Class A are also commercially
available.4
The packages used for CMOS devices are similar
to those used for other types of MOS devices and for
bipolar devices. The same potential failure
mechanisms apply to chip-to-substrate bonds, wire
bonds, and packages.2 All MOS devices are,
however, more surface-sensitive than digital bipolar
devices, and higher voltages are applied to MOS
devices than to digital bipolar devices.
MOS vs. bipolar ICs
MOS ICs have had a major impact on the digital
electronics industry. Not only have they displaced
bipolar ICs for many applications, but they have
also made possible a large number of totally new applications. As a result, they are now being produced
in volumes roughly comparable to those of bipolar
devices. Because bipolar devices antedate MOS
devices, more information has been published on the
reliability of bipolar circuits than on the reliability
of MOS circuits. Also, bipolar circuits were initially
used to a large extent in high-reliability military and
aerospace applications, whereas' MOS circuits have
been used principally in consumer and commercial
applications. Also, while most early MOS devices
were hermetically packaged, a large portion of all
MOS ICs produced today are encapsulated in
plastic.1,13
COMPUTER
+ VDD
VDD
SUBSTRATE
VOUT
INPUT
Q-
GATES
G
0 OUTPUT
l_n
p - WELL
-vss
Figure 1. The basic building block for CMOS integrated
circuits.
The first commercially available MOS devices
based on p-channel enhancement-mode MOS
transistors with aluminum gates. Accordingly, considerable information is available on the reliability
of this type of device, and on possible failure
mechanisms.ss-27 Devices that have since become
commercially available include CMOS, silicon-gate,
n-channel, depletion-mode, floating-gate, CCD, and
CMOS/SOS devices. Considerable data is now
available on the reliability and possible failure
mechanisms of CMOS devices,
on ICs containing silicon-gate transistors,51-" and on devices
based on n-channel transistors.55-"
A number of fundamental differences between
MOS and bipolar devices have an impact on
reliability. The principal differences are that MOS
ICs have a higher substrate resistivity and use
higher applied voltages, and the properties of the
gate oxide of MOS devices are more important.
The process of MOS fabrication is simpler than
bipolar fabrication.5,23 Accordingly, it is easier to attain higher chip complexity with MOS, and thus
higher gate-to-pin ratios. Since wire-bond failures
are a significant factor in limiting the reliability of
small-scale ICs, MOS can significantly improve
reliability by reducing the number of wire bonds and
external interconnections. Moreover, with MOS
technology, there is lower power dissipation per
function, which improves reliability by lowering
chip temperatures. In typical bipolar ICs (TTL),
device dissipation is significant.
MOS, particularly CMOS, also has an advantage
over bipolar devices in that the high impedance of
MOS devices does not result in high current densities in the metal interconnections, and thus electromigration (current-induced mass transport) is
not a common problem in MOS devices. Problems of
high current density at metal-silicon contacts are
also less frequent. The high impedance of MOS
devices also makes multilevel interconnections
feasible in complex arrays without significantly
were
October 1978
VIN
Figure 2. Voltage
CMOS inverter.
transfer characteristics of
a
basic
compromising circuit properties. Diffused
crossunders in the single-crystal silicon are effective, and if another level of interconnections is required in addition to that provided by the metallization layer, polycrystalline silicon, deposited as part
of the silicon-gate process, is quite effective as an interconnection level. By contrast, an additional level
of interconnections. in bipolar arrays means use of
metal-over-metal 'crossovers, which requires additional technology and introduces possible new
failure mechanisms.
Since localized defects in silicon are a factor in IC
reliability, one advantage of MOS compared to
bipolar circuits is that no epitaxial layer is required
for conventional monolithic MOS devices. MOS
devices are thus fabricated in silicon of better
AMBIENT TEMPERATURE (TA) - 250C
POWER DISSIPATION P = CVDD2f + PQUIESCENT
103
104
105
106
107
INPUT FREQUENCY (fl) - Hz
Figure 3. Typical relationship between dynamic dissipation of CMOS
integrated circuits and frequency.
10
7
crystallographic perfection, with no possibility of
epitaxial stacking faults or of epitaxial spikes that
cause device problems and damage the masks used
for photolithography. Finally, since MOS processing is simpler than bipolar processing and requires
fewer steps, fewer manufacturing errors are possible.
Failure rates for devices of various complexities
are often lumped together and reported as a failure
rate for a particular device family. Since MOS
devices tend to be more complex than bipolar
devices, equal reported failure rates per packaged
part actually represent lower failure rates per gate.
MOS ICs use many of the same materials and processes that bipolar ICs and small-signal transistors
do. Accordingly, improvements in silicon
materials,'9 oxidation,65-69 photolithography,50'70-7'
diffusion,20'72 metallization,7' passivation,78'" and
plastic encapsulation,"23"3'97-79 and also in device
physics, design, process control,'8 automation,80 and
electrical characterization have resulted in substantial improvements in the reliability of both types of
devices.
Reliability advantages of CMOS
CMOS technology provides a number of reliability advantages over other MOS technologies, 34,7-9,14,21,28 For example, since both p-type
and n-type diffusions are part of the normal process,
both are available to use as channel stoppers or as
part of a more effective input protection circuit. The
low dissipation of CMOS ICs results in lower chip
temperatures, which substantially improve reliability. The wide range of CMOS operating voltages permits greater reliability of operation, including allowing functional testing at voltages substantially
_above and below the ultimate operating voltage.
Moreover, because of low dissipation per gate,
CMOS can be used to fabricate very complex chips
without introducing reliability problems resulting
from excessively high chip temperatures."'0"4 By
contrast, power dissipation in large chips is a problem with TTL integrated circuits and, to some extent, PMOS and NMOS circuits. Finally, CMOS
technology represents a mature, high-volume
technology with an extensive history of reliability.
Potential failure mechanisms are well understood,
and production processes and process controls have
been specifically selected to ensure against the
possibility of manufacturing errors that might
adversely affect reliability.
Other factors of importance to the reliability of
CMOS ICs include device and design features
>(dielectric thickness and quality, design rules,
device complexity, in-process controls), specifications (maximum and minimum operating voltages,
operating temperature range), electrical testing
(tests performed on the wafer and on packaged
devices), and screening (amount of burn-in or other
screens applied). Operating conditions of impor-,
tance include chip temperature, applied voltage,
8
voltage transients, moisture content of the ambient,
and exact circuit usage.5
CMOS packaging
CMOS ICs are available in all of the common
package configurations. The conventional
hermetically sealed ceramic package containing a
cavity filled with dry gas is generally used for highreliability military and aerospace applications. The
frit or Cerdip package, with the final seal made by
fusion of a devitrifying solder glass, is the least expensive hermetic package for high-volume commercial application. Beam-lead sealed-junction devices
may also be considered hermetically sealed devices
in that the silicon nitride provides junction
hermeticity. The use of a gold-based metallization
system and an overlying amorphous inorganic
passivation layer provides additional protection
against possible deleterious reactions over the life of
the device.
Most ICs being manufactured in 1978, including
CMOS as well as other MOS and bipolar types, are
encapsulated in plastic rather than in hermetic
packages. Plastic encapsulation provides a number
of significant advantages, including lower product
cost, freedom from potential problems with loose
particles (in molded devices), mechanically strong
dual-in-line packages, good resistance to- shock and
vibration, no leak-test requirement, and possibility
of small packages.
A number of possible limitations of plasticencapsulated integrated circuits were identified",2"28
in studies of early plastic encapsulation systems applied to both bipolar and MOS ICs. These included
moisture penetration effects, effects due to mismatches between the coefficients of linear thermal
expansion of plastics and those of silicon and the
various interconnect metals, and the presence of
ionic materials and other contaminants in certain
plastics.
The knowledge of potential limitations of certain
plastics has led to the use, in recent years, of vastly
improved materials and processes for fabricating
plastic-encapsulated devices.5,2",36"37'41,48,76 An example is the use of high-purity novolac epoxy plastics
with high glass transition temperatures.23'7'
Modifications in assembly techniques have also
been made. As a result of these changes, plasticencapsulated devices manufactured in the 1976 to
1978 period have been significantly more reliable
than devices fabricated a number of years ago.
Humidity levels above 85 percent can greatly accelerate 'possible failure mechanisms in plasticencapsulated silicon devices."523,""i7'41,48.76'78 Consequently, high-humidity tests, particularly under
bias conditions, have been used to quantitatively
assess the integrity of IC passivation and encapsulation systems, and have been the basis for process improvements as well as quality control tests.
The effect of high humidity in accelerating failure
mechanisms has been the basis for a number of
detailed studies."37'48,64
COMPUTER
CMOS failure modes and mechanisms
temperature-deposited glass-like inorganic passivation materials can be very effective in reducing the
possibility of aluminum corrosion. Specific factors
that can result in chemical corrosion of aluminum
and electrochemical corrosion at cathode and anode
regions have been identified.
Failures in plastic-encapsulated devices are frequently attributable to penetration of moisture or
other iohic impurities along the chip-plastic interface. Figure 4 shows a cross-section of a typical
dual-in-line plastic package. The two paths by which
water vapor can enter such packages are through
the plastic and along the leads.' Pl:astic devices rarely fail in normal field use unless the wrong package
is selected for the system environment.'
Gate oxide breikdown may be due to localized
breakdown at defects or to intrinsic breakdown of
thin oxides at input circuits. Breakdown at inputs is
principally attributable to overstress from static
electricity discharges, particularly when the devices
are mishandled. While virtually all MOS ICs contain an input protection circuit, such circoits vary
considerably in design, principle of operation, and
effectiveness.",990-96 The susceptibility of silicon
devices to static electricity effects is not unique to
MOS circuits; it has also been reported to occur with
bipolar integrated circuits"""'97-" and with other
electronic components. Improved input protection
circuits in CMOS integrated circuits have been
shown to provide additional protection against
static electricity discharges.446',8 " Figure 5 shows
the improved input protection network" being used
on all new CD4000B devices.
Some information has been published on the
reliability of silicon-on-sapphire CMOS ICs, and on
possible failure mechanisms for that type of construction.88'89'42 While new failure mechanisms are
possible with CMOS/SOS, the principal failure
mechanisms are frequently similar to those observed with bulk CMOS devices.
MOS failure modes can be classified into the
categories of shorts, opens, and degradations.
Shorts are most commonly due to dielectric failure
of the gate (thin) oxide. Dendrite formation in goldmetallized devices can ilso result in resistive shorts.
Electrical opens may be due to microscopic cracks in
the metallization at topographic steps-, to photolithography problems, to corrosion of metallization,
to fusion of metal due to overstress, or to open wire
bonds. Degradation effects are attributable to the
motion of ions (such as Na+) in the silicon dioxide,
or to surface-charge-spreading effects and consequent inversion.
Considerable information is available on the
distribution of failure mechanisms in CMOS devices
that failed during accelerated-life stress tests or
field use. The principal failure mechanisms in
CMOS are due to parameter changes caused by motion of charge in or on oxides, and to shorts through
gate oxides. (The relative distribution of CD4000A
CMOS field failure mechanisms6 is shown in Table
1.) These failure mechanisms are similar to the principal failure mechanisms of other MOS device types.
There is,- however, a considerable variance in the
distribution of mechanisms: depending on the
source issuing the informatioii The -reports of users,
who include electronic equipment manufacturers as
well as government agencies and industrial organizations performing government-funded reliability
studies, tend to indicate that there are large, variations between products from different suppliers.
Several forms of alkali ion migration are possible,
including the commonly reported transverse Na+
ion movement in an electric field at an elevated
temperature, and lateral Na + ion movement followed by transverse movement. The net result of
alkali ion migration is to increase the threshold
voltage of p-channel transistors, to decrease the
threshold of n-channel transistors, or to decrease the
field inversion voltage'of n-type regions. Because
MOS structures have proven an excellent tool for Data on CMOS Reliability
the study of silicon-silicon dioxide interface properVarious sources of data on the reliability of CMOSties, a vast amount of information has been
available to- apply to the improvement of the pro- -integrated circuits exist, including data generated
cess, as well as to the design and control of device by device manufact-urers,"4"59,8,283,29,0,"6,"7,89,4041,48 by
users, and by government agencies and
fabrication.8'
Aluminum metal corrosion in integrated circuits
has been the subject of considerable study in recent
TRANSFER MOLDING
years."'9,23,48,'-89 It has been shown that low1/4"
e MATERIAL
NOVOLAC EPOXY
Table 1.
DIstrIbutIon of mechanisms that normally
occur In field failures.
FAILURE
MECHANISM
FALSE PULLS
GATE OXIDE SHORTS (HANDLING)
BLOWN METAL (OVERCURRENT STRESS)
QUALITY RELATED (SCRATCHED METAL, BONDING,
WRONG PELLET-OR PACKAGE).
MOISTURE (PLASTIC USED IN WRONG APPLICATION)
October 1978
GOLD
1.0
MIL
WlRES
T.C. BONDED
STEEL
LEAD FRAME
PERCENT
35
25
20
DEPRESSED EPOXY
MOUNT PAD DIE ATTACH
SPOT GOLD FRAME
SOLDER COATED
15 Figure 4. Cross-sectlonal:vlew of a typical dual-In-lIne
5 plastic-encapsulated Integrated circult.
9
operating-life tests of devices from five manufac-
VDD
turers.9
IN
*INTRINSIC DIODES
Figure 5. Improved input protection network for new
CD4000B Integrated circuits.
Specific types of CMOS
devices that have been evaluated include standard
A-series,products in hermetically sealed ceramic
packages,4'""80 B-series devices,"5""""'" beamlead
contractors."""""""'""2
sealed-junction devices,9 CMOS/SOS devices,'339"2
and others.
s~
CC
Results of accelerated-life
stress tests. A considerable amount of data has been generated during
qualification and conformance testing of CD4000A
series CMOS devices for MIL-M-38510, Class A.
These data indicate excellent package integrity lone
failure in a total of 729 devices tested to Group B
qualification tests) and excellent stability4"9"45 (only
one failure in a total of 1504 devices tested to Group
C qualification tests). Conformance test data on
more than 2.3 million device-hours of accelerated-life
stress testing at 125 OC on a wide variety of circuits,
from gates to MSI devices, show only five degradational failures and three inoperable failures, which
corresponds to a functional failure rate at 125 IC of
0.14 percent per 1000 hours, at a 60-percent confidence level.9
Much of the available data on CMOS reliability
has been generated by accelerated-operating-life
stress tests. A typical figure for reliability of
hermetically sealed CMOS devices (ceramic
packages) is on the order of 0.1 percent per 1000
hours at a 60-percent confidence level) for devices
operated at 1250C with VDD of 10 volts. This is
based
on more
than 9 million device-hours of
Table 2.
Effect of activation energies
on extrapolated failure rates.
ACTIVATION
ENERGY
0.3 eV
1.3 eV
10
FAILURE RATE (%/1000 hours)
VERSUS TEMPERATURE
1250C
550C
250C
0.1
0.1
0.02
0.00004
0.005
0.0000005
Reliability effects of operating temperature. Since
the thermal activation energy for failure of MOS
devices by the more prevalent failure mechanisms,
such as alkali ion migration in the thermally grown
gate oxide in an electric field, -is relatively high, the
overall thermal activation energy for failure of MOS
ICs, including CMOS devices, tends to be high.
Reported thermal activation energies for CMOS IC
failure rates range from 0.3 eV to 1.3 eV; In some
cases, a low acceleration factor is used to extrapolate results of accelerated tests, and it is
pointed out that the actual acceleration factor is
believed to be higher. Where experimental data is
presented to support an activation energy, the value
arrived at is frequently on the order of 1 eV.
The implications of these various activation
energies are apparent in Table 2, which shows the effect6 of extrapolating the extremes reported in activation energies, 0.3 eV and 1.3 eV. Both have been
taken as 0.1 percent per 1000 hours at 125 IC.
Reliability effects of operating voltage. A number
of manufacturers have shown increases in failure
rates of CMOS products as a result of increasing
operating voltage under accelerated stress conditions in operating-life tests.""9,23'29"36'37"41 Possible effects of higher operating voltage, on MOS ICs include increased chip temperature, accelerated motion of alkali ions, increased susceptibility to
surface-charge spreading and to field inversion, and'
increased incidence of oxide breakdown. Oxide
breakdown in MOS structures has been studied by a
number of investigators, and has been considered
by some to follow Peek's law in that the time to
failure is inversely related to the fourth power of the
applied voltage.23
The effect of operating voltage on relative failure
rate of CD4000A series and CD4000B series devices
is shown in Table 3. The higher reliability of B series
devices at higher voltages is attributed to the ability to electrically test devices at higher voltages, and
to operation at a smaller percentage of actual device
breakdown voltage.3 Functional and DC parameter
testing on CD4000B series parts is performed at
RCA at 2.8 volts and at 22 volts, whereas CD4000A
series devices are tested at 2.8 volts and at 17 volts.
Failure rates of plastic-encapsulated CMOS ICs.
Some data is available on comparative reliability of
Table 3.
Relative failure rates at 1250C at
virious applied voltages.
APPLIED
VOLTAGE
5
CD4000
A SERIES
1
B SERIES
-
10
3
1
15
10
3
20
-
6
CD4000
COMPUTER
similar devices in hermetic versus plastic packages.
In general, operating-life failure rates are reported
to bq several times higher for devices in plastic as
for those that are hermetically sealed. It is generally
not possible, hoWever, to take the available data and
make specific quantitative conclusions about the effect of plastic encapsulation on the reliability of a
given type of MOS IC. One reason why this cannot
be done, even though the same wafer processing is
applied to both plastic-encapsulated and hermetically sealed devices, is that there are many differences
in the assembly and test sequences other than the
packaging. For example, devices intended for highreliability applications may be subjected to more
stringent visual inspection criteria, may be assembled under very closely controlled conditions with
considerable documentation, may be electrically
tested under wide ranges of conditions (such as
temperature ranges between -55 OC and 125 0C),
and may be subjected to various screens, electrical
tests, burn-ins, and lot-acceptance criteria. Obviously, such techniques, while more costly, are effective
in eliminating a certain number of potentially less
reliable (freak) devices from the main population.
The failure rate of plastic-encapsulated MOS
devices can be considered to be the sum of the
specific failure rates of the total system, including
failure mechanisms occurring on the chip, in the interconnection system external to the chip, and in
the package. While unsuitable plastics can adversely affect the reliability of susceptible chips, plastic
encapsulation cannot provide a chip reliability in excess of that which would be encountered in a dry, inert ambient. Accordingly, the reliability of many
plastic-encapsulated devices, particularly under
lower humidity conditions, is limited by the reliability of the encapsulated chip, rather than by any
reliability limitations imposed by the plastic. A
failure rate on the order of 0.1 percent per 1000
hours at 850C, at the 60 percent upper confidence
level, can be expected for high-quality plasticencapsulated commercial-type MOS ICs prepared
by a mature, well-controlled process.23
Figure 6 shows the failtre rate of plasticencapsulated CMOS devices as a function of ambient water-vapor pressure, and indicates the degree
of improvement in packaging attained in recent
years.5
Reliability effects of device complexity. A
number of authors have dealt with the effect of chip
complexity on failure rate. It is now generally
agreed that increasing chip complexity increases
the failure rate per packaged part, but reduces the
failure rate per gate or per function accomplished.
The overall failure rate may be considered as the
sum of the failure rates due to wire bonds, to failures
that would occur with a chip of any size, and to chip
failures at localized defects, which is an areadependent factor.5'28 The failure rate due to wire
bonds is simply the product of the failure rate per
wire, such as 0.0001 percent per 1000 hours, times
the number of wires. The failure rate of chips due to
October 1978
20.
/
0
,
__1-
a-
I.)
C.)
1
0.5__
100
2
4
6
8
_
1,000
2
AGE AT FAILURE-HOURS
Figure 6. Weibull plot of results of 85°C185% relative
humidity test on CMOS devices.
localized defects increases with increasing chip area
but is not linearly dependent on the area of the chip;
it is considered to increase less rapidly than chip
size, owing to the tendency of localized defects to
cluster rather than to occur at random. (The considerations here are somewhat similar to those that
have been shown to apply to the effect of chip size or
circuit complexity on IC yield.)100°104 Complex ICs
are thus more reliable per gate, and the use of complex ICs in electronic equipment to perform the
same functions as a larger number of less complex
devices will in general result in substantially im-proved equipment reliability.
Field failure rates. Failure rates under field-use
conditions are much lower than failure rates under
accelerated stress conditions typically used by
device manufacturers to evaluate reliability. The
prediction of failure rates under field conditions requires the use of an acceleration factor to extrapolate high-temperature accelerated-stress
reliability data. Frequently, the acceleration factors
selected have been excessively conservative, with
some based on very low activation energies that
represent early bipolar IC reliability experience. In
general, the Arrhenius equation continues to be considered appropriate for expressing the effect of
temperature on failure rates.
Recent data on the reliability of CMOS ICs in
satellites105 includes a total of over 100 million
device-hours of operation of CD4000A series devices
at 25-125 OC with no failures, which corresponds to a
failure rate of 0.0009 percent per 1000 hours at a 60
percent confidence level.104 Field failure rates for
plastic-encapsulated CMOS ICs, at operating
temperature up to 550C, can be considered to be on
the order of 0.001-0.01 percent per 1000 hours at a
60 percent confidence level. Obviously, variations
will occur depending upon type, design, process,
11
manufacturer, screens applied, voltage, and severity
of the ambient conditions.
Radiation hardening. Ionizing radiation is a
specific type of environmental stress that can produce severe degradation in the electrical properties
of silicon ICs. Early MOS devices were sensitive to
ionizing radiation, with degradation occuring at a
level as low as 103 rads. Recent studies have
generated a considerable amount of information
concerning the effect of the thermally grown oxide
purity, growth conditions, and annealing conditions
on susceptibility to radiation damage. As a result of
these studies, it is now possible to modify the processing conditions to produce CMOS integrated circuits with considerably improved radiation hardness.4,9106-12 CMOS ICs guaranteed (by testing) to
withstand 1 X 106 rads became commercially
availablels in early 1978.
Reliability effects of process
technology trends
A number of trends in CMOS fabrication
technology affect IC reliability. Important recent
trends include increased chip complexity (more
functional devices per chip), 01-I5,20,801141-122 use of
devices with smaller geometries,123-128 and increased
use of automation and of better process-monitoring
techniques.129'31 Wafer processing trends include
use of improved materials.132'13 improved
photolithography and etching techniques,134'135 increased use of ion implantation, 1.137 improved
metallization, and more effective passivation
layers.'38-140 Process moodifications have also been
devised to substantially improve the radiation hardness of MOS oxides. Advances have also been made
in encapsulation techniques, in plastic materials,141
and in testing of completed devices.
Ion implantation provides a high-purity, veryclosely controlled source of dopant atoms. This, in
turn, permits tighter distributions of the electrical
characteristics of transistors. High chip complexity
makes possible higher gate-to-pin ratios, decreasing
the probability of failure due to wire bonds,
packages, or external interconnections of various
types, such as. soldered conffections in electronic
equipment. Moreover, with chips of high complexity, the failure rate per logic gate tends to be lower
than that of gates on chips of low complexity. These
and other advantages, plus immunity to noise, have
resulted in very wide use of CMOS ICs in electronic
systems, with predictions of even wider use in the
next several years.142-147 A number of authors have
indicated that CMOS/SOS is particularly well suited
to fabrication of VLSI circuits.10"4'4
The reliability of MOS IC chips is not at present
limited by the inherent properties of silicon, silicon
dioxide, aluminum, or thin-film polycrystalline
silicon; further improvements being made in chip
design and processing will continue to increase the
reliability of MOS ICs in all types of packages.
12
The net result of MOS process changes made in recent years has been to lower costs of all types, to
permit more complex circuits to be fabricated
economically, and to produce products with
substantially improved reliability, both in plastic
and in hermetic packages.
Reliability of CMOS vs. other MOS devices
Data on comparisons of the reliability of CMOS
ICs with that of other MOS technologies, such-as
p-channel or n-channel MOS circuits, or with that of
bipolar ICs such as TTL circuits, indicates that
when circuits of equal complexity, prepared by
mature, well-controlled processes are compared at
the same operating temperature, there are no
systematic differences among devices incorporating
the major MOS technologies, between MOS devices
with aluminum and polycrystalline silicon gates, or
between MOS and bipolar ICs."99,23,30148149
The most reliable integrated circuits are those
specifically designed for high reliability; fabricated
by mature, well-controlled processes; and screened
at all stages to remove freak devices that deviate
from the main population and are susceptible to early failure. Even the most reliable devices available
today are not limited in reliability by the properties
of materials; further substantial improvements in
CMOS device reliability are possible and are being
made by improvements in CMOS circuit design,
processing, packaging, and testing.
Conclusion
The reliability of CMOS ICs is equal to that of
bipolar ICs of equal complexity, when each type is
prepared by a well-controlled process and operated
at the same temperature. The reliability of CMOS
ICs in plastic depends on the design, process, circuit, manufacturer, degree of testing and screening,
and on the application, as well as on packaging.
Plastic packages are satisfactory for the majority of
all MOS IC applications.
No major differences in the reliability of products
of equal functional complexity, made with the major
MOS technologies (PMOS, CMOS, or NMOS), or of
products made with aluminum or silicon gates, are
evident in the available reliability data. Furthermore, the reliability of MOS devices can be considered to be equal to that of bipolar digital circuits
of equal complexity when each type is prepared by a
well-controlled process and operated at the same
temperature.
The potential failure mechanisms of CMOS
devices are now well understood, and CMOS devices
are being made by processes that minimize susceptibility of those devices to electrical degradation or
catastrophic failure. Process changes made in recent
years have lowered costs as well as substantially improved the reliability of CMOS ICs. M
COMPUTER
References
1. R. W. Ahrons and P. D. Gardner, "Interaction of
Technology and Performance in Complementary
Symmetry MOS Integrated Circuits," IEEE J.
Solid-State Circuits, VoL SC-5, Feb. 1970, pp. 24-29.
2. T. G. Athanas, "Development of COS/MOS
Technology," Solid-State Technology, Vol. 17, No.
6, June 1974, pp. 54-59.
3. G. B. Herzog, et al., "COS/MOS Product Design,"
RCA Engineer, Vol. 21, No. 4, Dec. 1975/Jan. 1976,
pp. 35-59.
4. "High-Reliability Devices," SSD-230, RCA Solid
State Division, Somerville, N.J., Aug. 1976.
5. L. J. Gallace, H. L. Pujol and G. L. Schnable,
"CMOS Reliability," ST-6561, RCA Solid State
Division, Somerville, N.J., Sept. 1976; also in Proc.
27th Electronic Components Conf, May 1977, pp.
496-512.
6. E. C. Douglas and A. G. F. Dingwall, "Ion Implantation for Threshold Control in COS/MOS
Circuits," IEEE Trans. Electron Devices, Vol.
ED-21, June 1974, pp. 324-331.
7. S. S. Eaton, "Sapphire Brings out the Best in
C-MOS," Electronics, Vol. 48, No. 12, June 12,
1975, pp. 115-120.
8. R. S. Ronen and F. B. Micheletti, "Recent SOS
Technology, Advances and Applications," Solid
State Technology, Vol. 18, No. 8, Aug. 1975, pp.
39-46.
9. G. L. Schnable, E. M. Reiss, and M. Vincoff,
"Reliability of Hermetically-Sealed CMOS Integrated Circuits," EASCON '76 Record, Sept.
1976, pp. 143A to 143-G.
10. J. Borel, "Advanced MOSFET Technologies: A
Review," Solid State Circuits 1976 (ESSCIRC, Toulouse), Editions du Journal de Physique, Paris,
1977, pp. 69-87.
11. Y. Nishi, "Silicon on Sapphire Technology," ibid.,
pp. 89-116.
12. A. Capell, D. Knoblock, L. Mather, and L. Lopp,
"Process Refinements Bring C-MOS on Sapphire
into Commercial Use," Electronics, Vol. 50, No. 11,
May 26, 1977, pp. 99-105.
13. R. A. Bishop, "L. S. I. CMOS Applications,"
Microelectron. and Reliab., Vol. 16, No. 4, Apr.
1977, pp. 461-475.
14. J. Hilibrand, "LSI Technology Choices," RCA
Engineer, Vol. 23, No. 1, June/July 1977, pp. 14-19.
15. A. G. F. Dingwall and R. E. Stricker, "CIL: A New
High-Speed High-Density Bulk CMOS
Technology," IEEE J. Solid-State Circ., Vol. SC-12,
Aug. 1977, pp. 344-348.
16. W. H. White, "Versatile Bulk CMOS," EASCON 77
Record, Sept. 1977, pp. 30-5A to 30-5D.
17. A. C. Ipri and J. C. Sarace, "Integrated Circuit Process and Design Rule Evaluation Techniques,"
RCA Rev., Vol. 38, Sept. 1977, pp. 323-350.
18. A. Aitken and P. Kung, "The Influence of Design
and Process Parameters on the Reliability of CMOS
Integrated Circuits," Microelectron. and Reliab.,
Vol. 17, Jan. 1978, pp. 201-210.
19. N. Snyderman, "Seniconductor Materials," Electronic News, Mar. 20, 1978, pp. 86-88.
20. M. Lassus and J.-P. Founaud, "Modern Physics
Brings Semiconductor Technology to a Turning
Point," Microelectron. and Reliab., Vol. 16, No. 4,
1977, pp. 367-387.
21. H. Khajezadeh and A. S. Rose, "Reliability Evaluation of Trimetal Integrated Circuits in Plastic
Packages," 15th Ann. Proc. Reliab. Phys., 1977, pp.
244-249.
October 1978
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22. D. Blandford, "Industry Standard for B-Series
CMOS," Microelectron. and Reliab., Vol. 16, No. 4,
1977, pp. 449-460.
23. G. L. Schnable, "Reliability of MOS Devices in
Plastic Packages," Proc. of the Tech. Program Intern'l Microelectronics Conf, 1976, pp. 82-91.
24. W. Eccleston and M. Pepper, "Modes of Failure of
MOS Devices," Microelectron. and Reliab., Vol. 10,
No. 10, Oct. 1971, pp. 325-338.
25. G. L. Schnable and R. S. Keen, "On Failure
Mechanisms in Large-Scale Integrated Circuits," in
Advances in Electronics and Electron Physics, Vol.
30, L. Marton, Editor, Academic Press, New York,
1971, pp. 79-138.
26. G. L. Schnable, H. J. Ewald, and E. S. Schlegel,
"MOS Integrated Circuit Reliability," IEEE
Trans. Reliab., Vol. R-21, Feb. 1972, pp. 12-19.
27. E. D. Colbourne, G. P. Coverley, and S. K. Behera,
"Reliability of MOS LSI Circuits," Proc. IEEE,
Vol. 62, Feb. 1974, pp. 244-259.
28. D. J. Burns and V. C. Kapfer, "A Comparative
Reliability Evaluation of C/MOS-A Maturing
Technology," Proc. 1975 Ann. Reliab. and Maint.
Symp., Jan. 1975, pp. 354-359.
29. J. Kinney, "Solid Statements from Solid State
Scientific, Inc.," Reliability Bulletin No. 25, Solid
State Scientific, Inc., Montgomeryville, Pa., Sept.
1975.
30. M. N. Vincoff and G. L. Schnable, "Reliability of
Complementary MOS Integrated Circuits," IEEE
Trans. Reliab., Vol. R-24, Oct. 1975, pp. 255-259.
31. L. Mattera, "Component Reliability, Part
I: Failure Data Bears Watching," Electronics, Vol.
48, No. 20, Oct. 2, 1975, pp. 91-98; "Reliability
Revisited: Failure-Rate Comparisons are Given a
Second Look," Electronics, Vol. 48, No. 26, Dec. 25,
1975, pp. 83-85.
32. M. Stitch, G. M. Johnson, B. P. Kirk, and J. B.
Brauer, "Microcircuit Accelerated Testing Using
High Temperature Operating Tests," IEEE Trans.
Reliab., Vol. R-24, Oct. 1975, pp. 238-250; "Addendum," IEEE Trans. Reliab., Vol. R-25, No. 2, Apr.
1976, p. 62.
33. J. S. Smith and D. D. Talada, "A CMOS/SOS
Reliability Study," 14th Ann. Proc. Reliab. Phys.,
1976, pp. 23-32.
34. T. J. Kobylarz and A. J. Graf, "Long Term Dormant Storage Testing, Initial Results," Proc. 1976
Ann. Reliab. and Maint. Symp., Jan. 1976, pp.
176-181.
35. R. P. Schuster and R. D. Fischer, "Analysis of Electronic Component Screening Programs and Their
Cost Effectiveness," IEEE Trans. Mfg. TechnoL,
Vol. MFT-5, June 1976, pp. 37-43.
36. "Reliability Report-1976 CMOS Life Stress
Testing," Motorola Semiconductor Products, Inc.,
Austin, Tex., June 1976.
37. "Reliability Report-1976 CMOS Plastic IC
Packaging System," Motorola Semiconductor
Products, Inc., Austin, Tex. June 1976.
38. G. M. Johnson, "Accelerated Testing Highlights
CMOS Failure Modes," EASCON '76 Record, Sept.
1976, pp. 142-A to 142-I.
39. G. Caswell and S. Cohen, "A Reliability Study of
CMOS/SOS Technology," GOMAC '76 Proceedings, Nov. 1976, pp. 84-87.
40. S. Kumar, "Failure Mechanism in MOS Devices
versus HC1 Gettering," Proc. Advanced Techniques in Failure Analysis Symp.-1976, Feb. 1976,
pp. 104-109.
14
41. "Semiconductor Data Library/CMOS," Vol. 5,
Series B, Motorola Semiconductor Products, Inc.,
Austin, Tex., 1976, pp. 3-2 to 3-3, 6-2 to 6-20.
42. W. E. Ham, M. S. Abrahams, J. Blanc, and C. J.
Buiocchi, "The Study of Microcircuits by Transmission Electron Microscopy," RCA Rev., Vol. 38,
Sept. 1977, pp. 351-389.
43. M. E. Levy, "An Investigation of Flaws in Complex
CMOS Devices by a Scanning Photoexcitation
Technique," 15th Ann. Proc. Reliab. Phys., 1977,
pp. 44-53.
44. G. M. Johnson and M. Stitch, "Microcircuit Accelerated Testing Reveals Life Limiting Failure
Modes,'" 15th Ann. Proc. Reliab. Phys., 1977, pp.
179-195.
45. B. Maximow, E. M. Reiss, and S. Kukunaris, "Accelerated Testing of Class A CMOS Integrated Circuits," 15th Ann. Proc. Reliab. Phys., 1977, pp.
212-216.
46. A. Shumka, E. L. Miller, and R. R. Piety, "Failure
Modes and Analysis Techniques for CMOS
Microcircuits," Proc. ATFA-77, Sept. 1977, pp.
75- 87.
47. J. M. Patterson, "Failures Due to Pinholes in
Polysilicon Conductors on CMOS Memory
Devices," Proc. ATFA-77, Sept. 1977, pp. 60-63.
48. M. J. Fox, "A Comparison of the Performance of
Plastic and Ceramic Encapsulations Based on
Evaluation of CMOS Integrated Circuits,"
Microelectron. and Reliab., Vol. 16, No. 3, 1977, pp.
251-254.
49. "Memory/LSI, 1977," Second Edition, MDR-7,
Reliability Analysis Center, Rome Air Development Center, 1977.
50. T. T. Sheng and R. B. Marcus, "Gate Oxide Thinning at the Isolation Oxide Wall," J. Electrochem.
Soc., Vol. 125, Mar. 1978, pp. 432-434.
51. R. J. Mattauch and W. M. Howle, Jr., "Field
Strength Degradation in Si-SiO2-Polycrystalline Si
Structures," IEEE J. of Solid-State Circ., Vol.
SC-11, Oct. 1976, pp. 732-735.
52. M. R. Child, D. W. Ranasinghe, and D. White, "Applications of the Scanning Electron Microscope in
the Development of Microtechnology," Proc.
ATFA-77, Sept. 1977, pp. 323-344.
53. R. M. Anderson and D. R. Kerr, "Evidence for Surface Asperity Mechanism of Conductivity in Oxide
Grown on Polycrystalline Silicon," J. Appl Phys.,
Vol. 48, Nov. 1977, pp. 4834-4836.
54. H. M. Naguib and L. H. Hobbs, "The Reduction of
Poly-Si Dissolution and Contact Resistance at Al/nPoly-Si Interfaces in Integrated Circuits," J. Electrochem. Soc., Vol. 125, Jan. 1978, pp. 169-171.
55. R. Allan, "The Failure Tracers," IEEE Spectrum,
Vol. 13, No. 10, Oct. 1976, pp. 33-39.
56. E. R. Hnatek, "Semiconductor Memory Attrition
Summary," IEEE 1976 Semiconductor Test Symposium Digest, Oct. 1976, pp. 35-40.
57. C. R. Barrett and R. C. Smith, "Failure Modes and
Reliability of Dynamic RAMs," System Design-A
Discipline in Transition, COMPCON 77 Spring
Digest, Feb. 1977, pp. 179-182.
58. J.C. McDonald and P. T. McCracken, "Testing for
High Reliability," ibid., pp. 190-191.
59. E. R. Hnatek, "Microprocessor Device Reliability,"
Microprocessors, Vol. 1, June 1977, pp. 299-303.
60. D. S. Peck, "Current Status of Integrated-Circuit
Reliability," Proc. Int. Conf. on Thin- and ThickFilm Technology, Augsburg, Germany, Sept. 1977,
pp. 223-228.
COMPUTER
61. C. H. Sie, R. A. Youngblood, J. H. Liao, and A.
Turk, "Soft Failure Modes in MOS RAMs," 15th
Ann. Proc. Reliab. Phys. 1977, pp. 27-32.
62. R. V. Pappu, E. Harris, and M. Yates, "Screening
63.
64.
65.
66.
67.
68.
69.
Methods and Experience with MOS Memory,"
Microelectron. and Reliab., Vol. 17, Jan. 1978, pp.
193-199.
B. Hall, "The Microprocessor Failure Rate Predictions," Microelectron. and Reliab., Vol. 17, No. 1,
Jan. 1978, pp. 211-221.
J. W. Peeples, "Influence of Electrical Bias Level
on 85/85 Test Results of Plastic Encapsulated 4K
RAMs," 16th Ann. Proc. Reliab. Phys., 1978.
B. E. Deal, "The Current Understanding of Charges
in the Thermally Oxidized Silicon Structure," J.
Electrochem. Soc., Vol. 121, June 1974, pp.
198C-205C.
R. Williams, "Properties of the Silicon-SiO2 Interface," J. Vac. Sci. Technol., Vol. 14, Sept./Oct. 1977,
pp. 1106-1111.
E. H. Nicollian, "Electrical Properties of the SiSiO2 Interface and its Influence on Device Performance and Stability," J. Vac. Sci. TechnoL, Vol. 14,
Sept./Oct. 1977, pp. 1112-1121.
P. Solomon, "Breakdown in Silicon Oxide-A
Review," J. Vac. Sci. Technol., Vol. 14, Sept./Oct.
1977, pp. 1122-1130.
B. R. Singh and P. Balk, "Oxidation of Silicon in the
Presence of Chlorine and Chlorine Compounds," J.
Electrochem. Soc., Vol. 125, Mar. 1978, pp. 453-461.
0
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TX 75265.
70. W. S. DeForest, Photoresist, McGraw-Hill Book
Co., New York, 1975.
71. E. I. Gordon and D. R. Herriott, "Pathways in
Device Lithography," IEEE Trans. Electron.
Devices, Vol. ED-22, July 1975, pp. 371-375.
72. K. A. Pickar, "Ion Implantation in
Silicon-Physics, Processing and Microelectronic
Devices," in Applied Solid State Science, Vol. 5,
edited by R. Wolfe, Academic Press, New York,
1975, pp. 151-249.
73. E. Philofsky and E. L. Hall, "A Review of the
Limitations of Aluminum Thin Films on Semiconductor Devices," IEEE Trans. on Pts. Hbr. Pkg.,
Vol. PHP-11, Dec. 1975, pp. 281-290.
74. A. J. Learn, "Evolution and Current Status of
Aluminum Metallization," J. Electrochem. Soc.,
Vol. 123, June 1976, pp. 894-906.
75. P. B. Ghate, J. C. Blair, and C. R. Fuller, "Metallization in Microelectronics," Thin Solid Films, Vol. 45,
Aug. 15, 1977, pp. 69-84.
76. G. L. Schnable, W. Kern, and R. B. Comizzoli,
"Passivation Coatings on Silicon Devices," J. Electrochem. Soc., Vol. 122, Aug. 1975, pp. 1092-1103.
77. W. Kern and R. S. Rosler, "Advances in Deposition
Processes for Passivation Films," J. Vac. Sci.
TechnoL., Vol. 14, Sept./Oct. 1977, pp. 1082-1099.
78. J. M. Lock, et al., Proc. Symp. Plastic Encapsulated
Semicond. Dev., (symposium held at the Royal
Signals and Radar Establishment, Malvern,
England, May 1976), pp. 1-13 /17.
79. C. H. Taylor, "Plastic Encapsulated Semiconductor
Devices-A Bibliography," Microelectron. and
Reliab., Vol. 16, No. 6, 1977, pp. 701-704.
80. J. Lyman, "Demands of LSI are Turning Chip
Makers Towards Automation, Production Innovations," Electronics, Vol. 50, No. 15, July 21, 1977,
pp. 81-92.
TEXAS INSTRUM ENTS
INCORPORATED
An equal opportunity employer M/F
Iq
-
8L A. H. Agajanian, "Semiconducting Devices: A
Bibliography of Fabrication Technology, Properties, and Applications," IFI/Plenum Data Co., New
York, 1976.
October 1978
15
82. R. C. Olberg and J. L. Bozarth, "Factors Contributing to the Corrosion of the Aluminum Metal
on Semiconductor Devices Packaged in Plastics,"
Microelectron. and Reliab., Vol. 15, No. 6, 1976, pp.
601-611.
83. R. B. Comizzoli, "Aluminum Corrosion in the
Presence of Phosphosilicate Glass and Moisture,"
RCA Rev., Vol. 37, Dec. 1976,- pp. 483-490.
84. B. Reich, "Bias Influence on Corrosion of Plastic
Encapsulated Device Metal Systems," IEEE
Trans. on Reliab., Vol. R-25, Dec. 1976, pp. 296-298.
85. E. P. G. T. van de Ven and H. Koelmans, "The
Anodic Corrosion of Aluminum," J. Electrochem.
Soc., Vol. 123, Jan. 1976, pp. 143-144.
86. W. M. Paulson and R. P. Lorigan, "The Effect of
Impurities on the Corrosion of Aluminum
Metallization," 14th Ann. Proc. Reliab. Phys., 1976,
pp. 42-47.
87. F. Neighbour and B. R. White, "Factors Governing
Aluminum Interconnection Corrosion in Plastic Encapsulated Microelectronic Devices," Microelectron. and Reliab., Vol. 16, No. 2, 1977, pp. 161-164.
88. A. Quach and W. L. Hunter, "A Study of Properties
of Plastics Used for Semiconductor
Encapsulation," J. Electronic Mtls., Vol. 6, May
1977, pp. 319-331.
89. N. L. Sbar and R. P. Kozakiewicz, "New Acceleration Factors for Temperature, Humidity, Bias
Testing," 16th Ann. Proc. Reliab. Phys., 1978, pp.
161-178.
90. M. Lenzlinger, '-'Gate Protection of MIS Devices,"
IEEE Trans. Electron Devices, Vol. ED-18, Apr.
1971, pp. 249-257.
91. L. W. Linholm and R. F. Plachy, "Electrostatic
Gate Protection Using an Arc Gap Device," 11th
Ann. Proc. Reliab. Phys., 1973, pp. 198-202.
92. C. E. Jowett, Electrostatics in the Electronics Environment, Halstead Press, New York, 1976, pp.
55-70, 107-113, 117-128.
93. "RCA COS/MOS Integrated Circuits," SSD-250,
RCA Solid State, Sommerville, N.J., July 1977.
94. F. S. Hickernell and J. J. Crawford, "Voltage
Breakdown Characteristics of Close Spaced
Aluminum Arc Gap Structures on Oxidized
Silicon," 15th Ann. Proc. Reliab. Phys., 1977, pp.
128-131.
95. R. K. Pancholy, "Gate Protection for CMOS/SOS,"
14th Ann. Proc. Reliab. Phys., 1977, pp. 132-137.
96. L. J. Gallace and H. L. Pujol, "The Evaluation of
CMOS Static-Charge Protection Networks and
Failure Mechanisms Associated with Overstress
Conditions as Related to Device Life," 15th Ann.
Proc. Reliab. Phys., 1977, pp. 149-157.
97. T. S. Speakman, "A Model for the Failure of
Bipolar Silicon Integrated Circuits Subjected to
Electrostatic Discharge," 12th Ann. Proc. Reliab.
Phys., 1974, pp. 60-69.
98. A. C. Trigonis, "Electrostatic Discharge in
Microcircuits," Proc. 1976 Annual Reliab. and
Maint. Symp., Jan. 1976, pp. 162-169.
99. R. L. Minear and G. A. Dodson, "Effects of Electrostatic Discharge on Linear Bipolar Integrated
Circuits," 15th Ann. Proc. Reliab. Phys., 1977, pp.
138-143.
100. E. I. Muehldorf, "Fault Clustering: Modeling and
Observation on Experimental LSI Chips," IEEE J.
Solid-State Cir., Vol. SC-10, Aug. 1975, pp. 237-244.
101. C. H. Stapper, "LSI Yield Modeling and Process
Monitoring," IBM J. Res. Develop., Vol. 20, May
1976, pp. 228-234.
16
102. G. E. Moore, "The Cost Structure of the Semiconductor Industry and Its Implications for Consumer
Electronics," IEEE Trans. Cons. Electr., Vol.
CE-23, No. 1, pp. x-xvi, Feb. 1977.
103. 0. Paz and T. R. Lawson, Jr., "Modification of
Poisson Statistics-Modeling Defects Introduced
by Diffusion," IEEE J. Solid-State Circ., Vol.
SC-12, Oct. 1977, pp. 540-546.
104. L. J. Gallace, H. L. Pujol, E. M. Reiss, G. L. Schnable, and M. N. Vincoff, "CMOS Reliability," RCA
Engineer, Vol. 23, No. 2, Aug./Sept. 1977, pp. 61-69.
105. G. J. Brucker, R. S. Ohanian, and E. G.
Stassinopoulos, "Successful Large-Scale Use of
CMOS Devices on Spacecraft Traveling Through
Intense Radiation Belts," IEEE Trans. on Aerosp.
and Electron. Syst., Vol. AES-12, Jan. 1976, pp.
23-29.
106. W. R. Dawes, Jr., G. F. Derbenwick, and B. L.
Gregory, "Process Technology for RadiationHardened CMOS Integrated Circuits," IEEE J.
Solid-State Circ., Vol. SC-li, Aug. 1976, pp.
459-465.
107. E. M. Reiss, "Radiation-Hardened CMOS," 1976
Govt. Microcirc. Appl. Conf (GOMAC) Digest,
Nov. 1976, pp. 154-157.
108. C. W. Gwyn, "Radiation Effects in the Insulator
Region of MOS Devices," in Oxides and Oxide
Films, Vol. 4, edited by J. W. Diggle and A. K. Vijh,
Marcel Dekker, Inc., New York, 1976, pp. 99-168.
109. H. Borkan, "Radiation Hardening of CMOS Technologies-An Overview," IEEE Trans. Nucl. Sci.,
Vol. NS-24, Dec. 1977, pp. 2043-2046.
110. A. Pikor and E. M. Reiss, "Technological Advances
in Manufacture of Radiation-Hardened CMOS Integrated Circuits," IEEE Trans. Nucl. Sci., Vol.
NS-24, Dec. 1977, pp. 2047-2050.
111. T. J. Sanders, "CMOS Hardness Assurance
Through Process Controls and Optimized Design
Procedures," IEEE Trans. Nucl Sci., Vol. NS-24,
Dec. 1977, pp. 2051-2055.
112. A. London, D. A. Matteucci, and R. C. Wang,
"Establishment of a Radiation-Hardened CMOS
Manufacturing Process," IEEE Trans. Nucl. Sci.,
Vol. NS-24, Dec. 1977, pp. 2056-2059.
113. B. LeBoss, "News Update," Electronics, Vol. 51,
No. 4, Feb. 16, 1978, p. 8.
114. D. A. Hodges, "A Review and Projection of
Semiconductor Components for Digital Storage,"
Proc. IEEE, Vol. 63, Aug. 1975, pp. 1136-1147.
115. J. Cunningham and J. Jaffe, "Insight into RAM
Costs Aids Memory-System Design," Electronics,
Vol 48, No. 25, Dec. 11, 1975, pp. 101-103.
116. J. Luecke, "Overview of Semiconductor
Technology Trends," Computers... by the Millions,
for the Millions, COMPCON 76 Fall Digest, Sept.
1976, pp. 52-55.
117. R. J. Koppel and I. Maltz, "Predicting the Real
Costs of Semiconductor-Memory Systems," Electronics, Vol. 49, No. 24, Nov. 25, 1976, pp. 117-122.
118. L. Altman, "Five Technologies Squeezing More
Performance from LSI Chips," Electronics, Vol. 50,
No. 17, Aug. 18, 1977, pp. 91-112.
119. R. Falkenberg, "Future Semiconductor
Memories-A System Designer's View,"
WESCON/77 Record, Sept. 1977, pp. 17/2-1 to
17/2-4.
120. A. G. F. Dingwall, R. E. Stricker, and J. 0. Sinniger, "A High Speed Bulk CMOS- C2L
Microprocessor," IEEE J. Solid-State Circ., Vol.
SC-12, Oct. 1977, pp. 457-462.
121. R. G. Stewart, "High-Density CMOS ROM
Arrays," ibid., pp. 502-506.
COMPUTER
122. G. Kasouf and S. Mercurio, "Evaluation of
LSI/MSI Reliability Models," Proc. 1978 Ann. Rel.
Maint. Symp., Jan. 1978, pp. 443-446.
123. R. W. Keyes, "Physical Limits in Digital Electronics," Proc. IEEE, Vol. 63, May 1975, pp.
740-767.
124. G. Meusburger and R. Sigusch, "Scaling of n-MOS
Devices: Experimental Verification of an LSI Concept," Siemens Forsch. u. Entwickl Ber., Vol. 5,
No. 6, 1976, pp. 332-337.
125. D. Widman and K.-U. Stein, "Semiconductor Technologies with Reduced Dimensions," Solid State
Circuits 1976 (ESSCIRC, Toulouse), Editions du
Journal de Physique, Paris, 1977, pp. 29-49.
126. G. R. Madland, "The Future of Silicon
Technology," Solid State Technol., Vol. 20, No. 8,
Aug. 1977, pp. 91-99.
127. K.-U. Stein, "Noise-Induced Error Rate as Limiting
Factor for Energy per Operation in Digital IC's,"
IEEEJ. Solid-State Circ., Vol. SC-12, Oct. 1977, pp.
527-530.
128. W. Myers, "The Limits of Silicon," Computer, Vol.
11, No. 4, Apr. 1978, pp. 79-80.
129. P. Wang, "An IC Factory in the New Age-An
Overview," in Semiconductor Silicon 1977, edited
by H. R. Huff and E. Sirtl, The Electrochemical
Society, Inc., Princeton, N.J., 1977, pp. 932-943.
130. P. Wang, "A LSI Factory of the New Age," Japan.
J. AppL Phys., Vol. 17, Suppl. 17-1, 1978, pp. 3-7.
131. "Harris Wafer Fab: Automation Boosts Yields in
4-Inchers," Electronics, Vol. 51, No. 8, Apr. 13,
1978, pp. 80-81.
132. B. E. Deal, "New Developments in Materials and
Processing Aspects of Silicon Device Technology,"
Japan. J. Appl. Phys., Vol. 16, Suppl. 16-1,1977, pp.
29-35.
133. Semiconductor Silicon 1977, edited by H. R. Huff
and E. Sirtl, The Electrochemical Society,
Princeton, N.J., 1977.
134. "Projection Printing and Product Mix will
Transform Masking Needs by 1980," Electron.
Pkg. and Prod., Vol. 16, No. 2, Feb. 1977, p. 11.
135. J. B. Houston, Jr., et al., "Developments in Semiconductor Microlithography II," Proc. of the Soc. of
Photo-Optical Inst. Eng., Vol. 100, Apr. 1977, pp.
1-174.
136. J. L. Stone and J. C. Plunkett, "Recent Advances in
Ion Implantation-A State of the Art Review,"
Solid State Technol., Vol. 19, No. 6, June 1976, pp.
35-44.
137. R. J. Duchynski, "Ion Implantation for Semiconductor Devices," Solid State Technol., Vol. 20, No.
11, Nov. 1977, pp. 53-58; Western Electric Eng.,
Vol. 21, No. 2, Apr. 1977, pp. 59-66.
138. R. Reichelderfer, et al., "Plasma Technology," Solid
State Technol., Vol. 21, No.4, Apr. 1978, pp.87-121.
139. A. K. Sinha, H. J. Levinstein, T. E. Smith, G. Quintana, and S. E. Haszko, "Reactive Plasma
Deposited Si-N Films for MOS-LSI Passivation," J.
Electrochem, Soc., Vol. 125, Apr. 1978, pp. 601-608.
140. M. Shibagaki, Y. Horiike, and T. Yamazaki, "Low
Temperature Silicon Nitride Deposition Using
Microwave-Excited Active Nitrogen," Japan. J.
AppL Phys., Vol. 17, Suppl. 17-1, 1978, pp. 215-221.
141. Proc. ERADCOM Symp. on Plastic Encapsulated/Polymer Sealed Semiconductors for Army
Equipment, Symposium held at Fort Monmouth,
N.J., May 1978.
142. B. LeBoss, "C-MOS Gets a Rise Out of LSI," Electronics, Vol. 50, No. 21, Oct. 13, 1977, pp. 65-66.
October 1978
143. "Worldwide Equipment Sales to Top $100 Billion,"
Electronics, Vol. 51, No. 1, Jan. 5, 1978, pp.
125-148.
144. M. Gold and D. Hanson, "C/MOS MPU Applications Spur RCA Deal with Intel," Electronic News,
Vol. 23, No. 1179, Apr. 10, 1978, pp. 22, 26.
145. "RCA to Make Intel Parts Using SOS," Electronics, Vol. 51, No. 8, Apr. 13, 1978, pp. 41-42.
146. W. F. Arnold, "SOS Pact has 'em Guessing," Electronics, Vol. 51, No. 9, Apr. 27, 1978, pp. 94-95.
147. Y. Nishi and H. Hara, "Physics and Device Technology of Silicon on Sapphire," Japan. J. Appl
Phys., Vol. 17, Suppl. 17-1, 1978, pp. 27-35.
148. L. C. Hamiter, Jr., "How Reliable are MOS IC's?
As Good as Bipolars, Says NASA," Electronics,
Vol. 42, No. 13, June 23, 1969, pp. 106-110.
149. D. A. Hodges, "Components for Semiconductor
Memories," 1973 IEEE INTERCON Technical Papers, Solid State, Mar. 1973, pp. 2/1-1 to 2/1-2.
George L. Schnable is head of solid
state process research in RCA Laboratories' Integrated Circuit Technology
Center. He has been involved in electronic materials and process technology R&D for 25 years, both at RCA
and at Philco-Ford. He is the author or
coauthor of more than 50 publications
and holds 20 US patents. He is a member of a number of societies, including
the American Chemical Society and the IEEE. He received a BS degree in chemistry from Albright College
and holds MS and PhD degrees from the University of
Pennsylvania.
Larry J. Gallace is manager of the
Reliability Engineering Laboratory in
RCA's Solid State Division in New
Jersey. He joined RCA in 1958 and has
t: f g'l0worked predominantly in the area of
-0
\% !wreliability
ft a
engineering. Since 1972, he
has been heavily involved in developing test methods for characterizing
* £g;g l the reliability of CMOS devices. He
has been a recipient of RCA team
awards for silicon power transistor engineering. He holds
a BS degree in mathematics and an MS degree in applied
and mathematical statistics, both from Rutgers University.
Henry L. Pujol is manager of engineering, assembly, and test at RCA's Solid
State Division in West Palm Beach,
Florida. He joined RCA in 1969 and
has been responsible for the design of
many standard CD4000 series circuits.
He has been responsible for worldwide
market planning of CMOS standard
parts and for the application engineering of MOS logic products, including
custom-circuit support, product specifications, and test
specifications. He holds a BSEE from City College of New
York and an MSEE from Rutgers University.
17